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path: root/drivers/clk/imx/clk-imx7d.c
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2024-06-21clk: imx: add CLK_SET_RATE_PARENT for lcdif_pixel_src for i.MX7DPeng Fan1-1/+1
Add flag 'CLK_SET_RATE_PARENT' to 'IMX7D_LCDIF_PIXEL_ROOT_SRC' to propagate rate changes from LCDIF pixel clock to video PLL to provide more accurate clock rate for LCDIF pixel clock. Signed-off-by: Peng Fan <[email protected]> Reviewed-by: Abel Vesa <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Abel Vesa <[email protected]>
2024-06-21clk: imx: Remove CLK_SET_PARENT_GATE for DRAM mux for i.MX7DPeng Fan1-2/+2
For i.MX7D DRAM related mux clock, the clock source change should ONLY be done done in low level asm code without accessing DRAM, and then calling clk API to sync the HW clock status with clk tree, it should never touch real clock source switch via clk API, so CLK_SET_PARENT_GATE flag should NOT be added, otherwise, DRAM's clock parent will be disabled when DRAM is active, and system will hang. Signed-off-by: Peng Fan <[email protected]> Reviewed-by: Abel Vesa <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Abel Vesa <[email protected]>
2023-01-29clk: imx: remove clk_count of imx_register_uart_clocksPeng Fan1-1/+1
The clk count has been get with of_clk_get_parent_count, there is no need to pass clk_count from users. Signed-off-by: Peng Fan <[email protected]> Reviewed-by: Abel Vesa <[email protected]> Signed-off-by: Abel Vesa <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2022-11-25clk: imx: rename imx_obtain_fixed_clk_hw() to imx_get_clk_hw_by_name()Dario Binacchi1-2/+2
The imx_obtain_fixed_clk_hw name was wrong and misleading. Renaming it to imx_get_clk_hw_by_name clarifies the purpose of the function, and will allow it to be used not only for fixed rate clocks but also in wider contexts. No functional changes intended. The replacements were made with the following command: grep -rl 'imx_obtain_fixed_clk_hw' ./ | \ xargs sed -i 's/imx_obtain_fixed_clk_hw/imx_get_clk_hw_by_name/g' Tested on a BSH SystemMaster (SMM) S2 board. Signed-off-by: Dario Binacchi <[email protected]> Reviewed-by: Abel Vesa <[email protected]> Signed-off-by: Abel Vesa <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2022-04-12clk: imx: Remove the snvs clockJacky Bai1-1/+0
The SNVS moudule is not used only by the linux, it may also used by other SW component is secure world. No sense to populate it in linux, so remove it. Signed-off-by: Jacky Bai <[email protected]> Reviewed-by: Abel Vesa <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Abel Vesa <[email protected]>
2022-03-04clk: imx7d: Remove audio_mclk_root_clkAbel Vesa1-1/+0
The audio_mclk_root_clk was added as a gate with the CCGR121 (0x4790), but according to the reference manual, there is no such gate. The CCGR121 belongs to ECSPI2 and it is not shared. Fixes: 8f6d8094b215b57 ("ARM: imx: add imx7d clk tree support") Reported-by: David Wolfe <[email protected]> Signed-off-by: Abel Vesa <[email protected]> Reviewed-by: Peng Fan <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2021-04-04clk: imx: Fix reparenting of UARTs not associated with stdoutAdam Ford1-21/+1
Most if not all i.MX SoC's call a function which enables all UARTS. This is a problem for users who need to re-parent the clock source, because any attempt to change the parent results in an busy error due to the fact that the clocks have been enabled already. clk: failed to reparent uart1 to sys_pll1_80m: -16 Instead of pre-initializing all UARTS, scan the device tree to see which UART clocks are associated to stdout, and only enable those UART clocks if it's needed early. This will move initialization of the remaining clocks until after the parenting of the clocks. When the clocks are shutdown, this mechanism will also disable any clocks that were pre-initialized. Fixes: 9461f7b33d11c ("clk: fix CLK_SET_RATE_GATE with clock rate protection") Suggested-by: Aisheng Dong <[email protected]> Signed-off-by: Adam Ford <[email protected]> Reviewed-by: Abel Vesa <[email protected]> Tested-by: Ahmad Fatoum <[email protected]> Signed-off-by: Abel Vesa <[email protected]>
2020-09-07clk: imx: fix i.MX7D peripheral clk mux flagsPeng Fan1-65/+66
According to RM, Page 574, Chapter 5.2.6.4.3 Peripheral clock slice, "IP clock slices must be stopped to change the clock source.". So we must have CLK_SET_PARENT_GATE flag to avoid glitch. Signed-off-by: Peng Fan <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2020-08-22clk: imx: Explicitly include bits.hAnson Huang1-0/+1
It is better to explicitly include the required header file rather then get it through some recursive include. Signed-off-by: Anson Huang <[email protected]> Acked-by: Stephen Boyd <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2020-03-16clk: imx7d: Add PXP clockLaurent Pinchart1-0/+1
The PXP has a single CCGR clock gate, gating both the IPG_CLK_ROOT and the MAIN_AXI_CLK_ROOT. Add a single clock to cover both. Signed-off-by: Laurent Pinchart <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2019-10-28clk: imx: imx7d: use imx_obtain_fixed_clk_hw to simplify codePeng Fan1-2/+2
imx_obtain_fixed_clk_hw could be used to simplify code to replace __clk_get_hw(of_clk_get_by_name(node, "name")) Signed-off-by: Peng Fan <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2019-07-17Merge tag 'clk-for-linus' of ↵Linus Torvalds1-484/+500
git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux Pull clk updates from Stephen Boyd: "This round of clk driver and framework updates is heavy on the driver update side. The two main highlights in the core framework are the addition of an bulk clk_get API that handles optional clks and an extra debugfs file that tells the developer about the current parent of a clk. The driver updates are dominated by i.MX in the diffstat, but that is mostly because that SoC has started converting to the clk_hw style of clk registration. The next big update is in the Amlogic meson clk driver that gained some support for audio, cpu, and temperature clks while fixing some PLL issues. Finally, the biggest thing that stands out is the conversion of a large part of the Allwinner sunxi-ng driver to the new clk parent scheme that uses less strings and more pointer comparisons to match clk parents and children up. In general, it looks like we have a lot of little fixes and tweaks here and there to clk data along with the normal addition of a handful of new drivers and a couple new core framework features. Core: - Add a 'clk_parent' file in clk debugfs - Add a clk_bulk_get_optional() API (with devm too) New Drivers: - Support gated clk controller on MIPS based BCM63XX SoCs - Support SiLabs Si5341 and Si5340 chips - Support for CPU clks on Raspberry Pi devices - Audsys clock driver for MediaTek MT8516 SoCs Updates: - Convert a large portion of the Allwinner sunxi-ng driver to new clk parent scheme - Small frequency support for SiLabs Si544 chips - Slow clk support for AT91 SAM9X60 SoCs - Remove dead code in various clk drivers (-Wunused) - Support for Marvell 98DX1135 SoCs - Get duty cycle of generic pwm clks - Improvement in mmc phase calculation and cleanup of some rate defintions - Switch i.MX6 and i.MX7 clock drivers to clk_hw based APIs - Add GPIO, SNVS and GIC clocks for i.MX8 drivers - Mark imx6sx/ul/ull/sll MMDC_P1_IPG and imx8mm DRAM_APB as critical clock - Correct imx7ulp nic1_bus_clk and imx8mm audio_pll2_clk clock setting - Add clks for new Exynos5422 Dynamic Memory Controller driver - Clock definition for Exynos4412 Mali - Add CMM (Color Management Module) clocks on Renesas R-Car H3, M3-N, E3, and D3 - Add TPU (Timer Pulse Unit / PWM) clocks on Renesas RZ/G2M - Support for 32 bit clock IDs in TI's sci-clks for J721e SoCs - TI clock probing done from DT by default instead of firmware - Fix Amlogic Meson mpll fractional part and spread sprectrum issues - Add Amlogic meson8 audio clocks - Add Amlogic g12a temperature sensors clocks - Add Amlogic g12a and g12b cpu clocks - Add TPU (Timer Pulse Unit / PWM) clocks on Renesas R-Car H3, M3-W, and M3-N - Add CMM (Color Management Module) clocks on Renesas R-Car M3-W - Add Clock Domain support on Renesas RZ/N1" * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (190 commits) clk: consoldiate the __clk_get_hw() declarations clk: sprd: Add check for return value of sprd_clk_regmap_init() clk: lochnagar: Update DT binding doc to include the primary SPDIF MCLK clk: Add Si5341/Si5340 driver dt-bindings: clock: Add silabs,si5341 clk: clk-si544: Implement small frequency change support clk: add BCM63XX gated clock controller driver devicetree: document the BCM63XX gated clock bindings clk: at91: sckc: use dedicated functions to unregister clock clk: at91: sckc: improve error path for sama5d4 sck registration clk: at91: sckc: remove unnecessary line clk: at91: sckc: improve error path for sam9x5 sck register clk: at91: sckc: add support to free slow clock osclillator clk: at91: sckc: add support to free slow rc oscillator clk: at91: sckc: add support to free slow oscillator clk: rockchip: export HDMIPHY clock on rk3228 clk: rockchip: add watchdog pclk on rk3328 clk: rockchip: add clock id for hdmi_phy special clock on rk3228 clk: rockchip: add clock id for watchdog pclk on rk3328 clk: at91: sckc: add support for SAM9X60 ...
2019-07-12Merge branches 'clk-rpi-cpufreq', 'clk-tegra', 'clk-simplify-provider.h', ↵Stephen Boyd1-0/+1
'clk-sprd' and 'clk-at91' into clk-next - Support for CPU clks on Raspberry Pi devices - Slow clk support for AT91 SAM9X60 SoCs * clk-rpi-cpufreq: clk: raspberrypi: register platform device for raspberrypi-cpufreq firmware: raspberrypi: register clk device clk: bcm283x: add driver interfacing with Raspberry Pi's firmware clk: bcm2835: remove pllb * clk-tegra: clk: tegra: Do not enable PLL_RE_VCO on Tegra210 clk: tegra: Warn if an enabled PLL is in IDDQ clk: tegra: Do not warn unnecessarily clk: tegra210: fix PLLU and PLLU_OUT1 * clk-simplify-provider.h: clk: consoldiate the __clk_get_hw() declarations clk: Unexport __clk_of_table clk: Remove ifdef for COMMON_CLK in clk-provider.h * clk-sprd: clk: sprd: Add check for return value of sprd_clk_regmap_init() clk: sprd: Check error only for devm_regmap_init_mmio() clk: sprd: Switch from of_iomap() to devm_ioremap_resource() * clk-at91: clk: at91: sckc: use dedicated functions to unregister clock clk: at91: sckc: improve error path for sama5d4 sck registration clk: at91: sckc: remove unnecessary line clk: at91: sckc: improve error path for sam9x5 sck register clk: at91: sckc: add support to free slow clock osclillator clk: at91: sckc: add support to free slow rc oscillator clk: at91: sckc: add support to free slow oscillator clk: at91: sckc: add support for SAM9X60 dt-bindings: clk: at91: add bindings for SAM9X60's slow clock controller clk: at91: sckc: add support to specify registers bit offsets clk: at91: sckc: sama5d4 has no bypass support
2019-07-12clk: consoldiate the __clk_get_hw() declarationsStephen Rothwell1-0/+1
Without this we were getting errors like: In file included from drivers/clk/clkdev.c:22:0: drivers/clk/clk.h:36:23: error: static declaration of '__clk_get_hw' follows non-static declaration include/linux/clk-provider.h:808:16: note: previous declaration of '__clk_get_hw' was here Fixes: 59fcdce425b7 ("clk: Remove ifdef for COMMON_CLK in clk-provider.h") fixes: 73e0e496afda ("clkdev: Always allocate a struct clk and call __clk_get() w/ CCF") Signed-off-by: Stephen Rothwell <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2019-06-07clk: imx7d: Switch to clk_hw based APIAbel Vesa1-484/+499
Switch the entire clk-imx7d driver to clk_hw based API. This allows us to move closer to a clear split between consumer and provider clk APIs. Signed-off-by: Abel Vesa <[email protected]> Reviewed-by: Stephen Boyd <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2019-05-30treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 159Thomas Gleixner1-7/+1
Based on 1 normalized pattern(s): the code contained herein is licensed under the gnu general public license you may obtain a copy of the gnu general public license version 2 or later at the following locations http www opensource org licenses gpl license html http www gnu org copyleft gpl html extracted by the scancode license scanner the SPDX license identifier GPL-2.0-or-later has been chosen to replace the boilerplate/reference in 161 file(s). Signed-off-by: Thomas Gleixner <[email protected]> Reviewed-by: Richard Fontana <[email protected]> Reviewed-by: Allison Randal <[email protected]> Reviewed-by: Kate Stewart <[email protected]> Cc: [email protected] Link: https://lkml.kernel.org/r/[email protected] Signed-off-by: Greg Kroah-Hartman <[email protected]>
2019-04-29clk: imx: correct i.MX7D AV PLL num/denom offsetAnson Huang1-2/+2
According reference manual, i.MX7D's audio/video PLL's num/denom register offset are 0x20/0x30, they are different from i.MX6's audio/video PLL, correct it by introducing new offset variables for audio/video PLL and using runtime assignment based on PLL type. Signed-off-by: Anson Huang <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2019-03-08Merge branches 'clk-of-refcount', 'clk-mmio-fixed-clock', 'clk-remove-clps', ↵Stephen Boyd1-0/+1
'clk-socfpga-parent' and 'clk-struct-size' into clk-next - Various DT of_node refcount fixes - Support for fixed rate clks populated from an MMIO register - Remove clps711x driver as the board support is gone * clk-of-refcount: clk: dove: fix refcount leak in dove_clk_init() clk: mv98dx3236: fix refcount leak in mv98dx3236_clk_init() clk: armada-xp: fix refcount leak in axp_clk_init() clk: kirkwood: fix refcount leak in kirkwood_clk_init() clk: armada-370: fix refcount leak in a370_clk_init() clk: vf610: fix refcount leak in vf610_clocks_init() clk: imx7d: fix refcount leak in imx7d_clocks_init() clk: imx6sx: fix refcount leak in imx6sx_clocks_init() clk: imx6q: fix refcount leak in imx6q_clocks_init() clk: samsung: exynos4: fix refcount leak in exynos4_get_xom() clk: socfpga: fix refcount leak clk: ti: fix refcount leak in ti_dt_clocks_register() clk: qoriq: fix refcount leak in clockgen_init() clk: highbank: fix refcount leak in hb_clk_init() * clk-mmio-fixed-clock: clk: Add Fixed MMIO clock driver dt-bindings: clk: Add bindings for Fixed MMIO clock * clk-remove-clps: clk: clps711x: Remove board support * clk-socfpga-parent: clk: socfpga: Don't have get_parent for single parent ops * clk-struct-size: clk: imx: imx7ulp: use struct_size() in kzalloc()
2018-12-28clk: imx7d: fix refcount leak in imx7d_clocks_init()Yangtao Li1-0/+1
The of_find_compatible_node() returns a node pointer with refcount incremented, but there is the lack of use of the of_node_put() when done. Add the missing of_node_put() to release the refcount. Signed-off-by: Yangtao Li <[email protected]> Fixes: 8f6d8094b215 ("ARM: imx: add imx7d clk tree support") Signed-off-by: Stephen Boyd <[email protected]>
2018-11-06clk: imx7d: remove UART1 clock settingAnson Huang1-3/+0
There are clock assignments in all i.MX7D dtb files for UART1, below is the example in imx7d-sdb.dts, so setting UART1 clock in clock driver is NOT necessary, actually, module clocks setting should be done in module driver. &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1>; assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>; assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>; status = "okay"; }; Signed-off-by: Anson Huang <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2018-10-17clk: imx7d: remove CLK_IS_CRITICAL flag for arm_a7_root_clkAnson Huang1-1/+1
i.MX7D uses virtual cpu clock of "arm" clock to be child clock of "arm_a7_root_clk" and it is with CLK_IS_CRITICAL flag set, so no need to add CLK_IS_CRITICAL flag for keeping "arm_a7_root_clk" use count correct, latest clock tree is as below in clk_summary: pll_arm_main 1 1 0 792000000 0 pll_arm_main_bypass 1 1 0 792000000 0 pll_arm_main_clk 1 1 0 792000000 0 arm_a7_src 1 1 0 792000000 0 arm_a7_cg 1 1 0 792000000 0 arm_a7_div 1 1 0 792000000 0 arm_a7_root_clk 1 1 0 792000000 0 arm 1 1 0 792000000 Signed-off-by: Anson Huang <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2018-10-16clk: imx: imx7d: remove clks_init_on arrayAnson Huang1-19/+8
Clock framework will enable those clocks registered with CLK_IS_CRITICAL flag, so no need to have clks_init_on array during clock initialization now. Signed-off-by: Anson Huang <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2018-10-16clk: imx: imx7d: remove unnecessary clocks from clks_init_on arrayAnson Huang1-2/+1
On i.MX7D, IMX7D_NAND_USDHC_BUS_ROOT_CLK is NOT necessary for system, and IMX7D_AHB_CHANNEL_ROOT_CLK is NOT existing at all, remove them from clks_init_on array. Signed-off-by: Anson Huang <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2018-07-09clk: imx7d: add IMX7D_MU_ROOT_CLKOleksij Rempel1-0/+1
This clock is needed for iMX mailbox driver Signed-off-by: Oleksij Rempel <[email protected]> Reviewed-by: Dong Aisheng <[email protected]> Reviewed-by: Fabio Estevam <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2018-06-04Merge branches 'clk-imx7d', 'clk-hisi-stub', 'clk-mvebu', 'clk-imx6-epit' ↵Stephen Boyd1-1/+3
and 'clk-debugfs-simple' into clk-next * clk-imx7d: clk: imx7d: reset parent for mipi csi root clk: imx7d: fix mipi dphy div parent * clk-hisi-stub: clk/driver/hisi: Consolidate the Kconfig for the CLOCK_STUB * clk-mvebu: clk: mvebu: use correct bit for 98DX3236 NAND * clk-imx6-epit: clk: imx6: add EPIT clock support * clk-debugfs-simple: clk: Return void from debug_init op clk: remove clk_debugfs_add_file() clk: tegra: no need to check return value of debugfs_create functions clk: davinci: no need to check return value of debugfs_create functions clk: bcm2835: no need to check return value of debugfs_create functions clk: no need to check return value of debugfs_create functions
2018-06-01clk: imx7d: reset parent for mipi csi rootRui Miguel Silva1-0/+2
To guarantee that we do not get Overflow in image FIFO the outer bandwidth has to be faster than inputer bandwidth. For that it must be possible to set a faster frequency clock. So set new parent to sys_pfd3 clock for the mipi csi block. Acked-by: Shawn Guo <[email protected]> Signed-off-by: Rui Miguel Silva <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2018-06-01clk: imx7d: fix mipi dphy div parentRui Miguel Silva1-1/+1
Fix the mipi dphy root divider to mipi_dphy_pre_div, this would remove a orphan clock and set the correct parent. before: cat clk_orphan_summary enable prepare protect clock count count count rate accuracy phase ---------------------------------------------------------------------------------------- mipi_dphy_post_div 1 1 0 0 0 0 mipi_dphy_root_clk 1 1 0 0 0 0 cat clk_dump | grep mipi_dphy mipi_dphy_post_div 1 1 0 0 0 0 mipi_dphy_root_clk 1 1 0 0 0 0 after: cat clk_dump | grep mipi_dphy mipi_dphy_src 1 1 0 24000000 0 0 mipi_dphy_cg 1 1 0 24000000 0 0 mipi_dphy_pre_div 1 1 0 24000000 0 0 mipi_dphy_post_div 1 1 0 24000000 0 0 mipi_dphy_root_clk 1 1 0 24000000 0 0 Fixes: 8f6d8094b215 ("ARM: imx: add imx7d clk tree support") Acked-by: Dong Aisheng <[email protected]> Signed-off-by: Rui Miguel Silva <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2018-06-01clk: imx7d: correct enet clock CCGR registersAnson Huang1-4/+6
Correct enet clock gates as below: CCGR6: IMX7D_ENET_AXI_ROOT_CLK (enet1 and enet2 bus clocks) CCGR112: IMX7D_ENET1_TIME_ROOT_CLK, IMX7D_ENET1_IPG_ROOT_CLK CCGR113: IMX7D_ENET2_TIME_ROOT_CLK, IMX7D_ENET2_IPG_ROOT_CLK Just rename unused IMX7D_ENETx_REF_ROOT_CLK for IMX7D_ENETx_IPG_ROOT_CLK instead of adding new clocks. Based on Andy Duan's patch from the NXP kernel tree. Signed-off-by: Anson Huang <[email protected]> Acked-by: Rob Herring <[email protected]> Reviewed-by: Stefan Agner <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2018-06-01clk: imx7d: correct enet phy ref clock gatesAnson Huang1-2/+1
IMX7D_ENET_PHY_REF_ROOT_DIV supplies clock for PHY directly, there is no clock gate after it, rename it to IMX7D_ENET_PHY_REF_ROOT_CLK to avoid device tree change. Signed-off-by: Anson Huang <[email protected]> Reviewed-by: Stefan Agner <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2018-04-06clk: imx7d: Move clks_init_on before any clock operationsDong Aisheng1-7/+7
For init on clocks we should move it at the first place in imx7d_clocks_init() before any clock operations, else the clock operation may fail in case the clock is still not on. Acked-by: Ranjani Vaidyanathan <[email protected]> Signed-off-by: Dong Aisheng <[email protected]> Signed-off-by: Irina Tirdea <[email protected]> Signed-off-by: Abel Vesa <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2018-04-06clk: imx7d: Correct ahb clk parent selectAnson Huang1-1/+1
Design team change the ahb's clk parent options but did NOT update the DOC accordingly in time, so the AHB/IPG's clk rate in clk tree is incorrect, AHB is 67.5MHz and IPG is 33.75MHz, but using scope to monitor them, they are actually 135MHz and 67.5MHz, update the clk parent option to make clk tree info correct. Signed-off-by: Anson Huang <[email protected]> Signed-off-by: Irina Tirdea <[email protected]> Signed-off-by: Abel Vesa <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2018-04-06clk: imx7d: Correct dram pll typeAnson Huang1-1/+3
DRAM PLL is a audio/video type PLL, need to correct it to get correct ops of PLL. There is a test_div placed before DRAM PLL's gate, so add this test div clk. Signed-off-by: Anson Huang <[email protected]> Signed-off-by: Irina Tirdea <[email protected]> Signed-off-by: Abel Vesa <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2018-04-06clk: imx7d: Add USB clock informationPeter Chen1-1/+8
Add USB clock information, the pll_usb_main_clk is USB_PLL at CCM which is the output of USBOTG2 PHY. Signed-off-by: Peter Chen <[email protected]> Signed-off-by: Irina Tirdea <[email protected]> Signed-off-by: Abel Vesa <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2018-03-14Merge tag 'clk-imx-4.17-misc' of ↵Stephen Boyd1-40/+44
git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into clk-imx Pull i.MX clock misc updates from Shawn Guo: - A correction on i.MX6SX CKO clock mux options. - A fix on i.MX7D Video PLL clock tree to include the missing dividers. - Update i.MX6UL/ULL clock driver to add epdc_podf instead of sim_podf clock for i.MX6ULL. * tag 'clk-imx-4.17-misc' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: clk: imx6ull: Add epdc_podf instead of sim_podf clk: imx: imx7d: correct video pll clock tree clk: imx: imx6sx: update cko mux options
2018-03-01clk: imx: imx7d: correct video pll clock treeAnson Huang1-40/+44
There is a test divider and post divider in video PLL, test divider is placed before post divider, all clocks that can select parent from video PLL should be from post divider, NOT from pll_video_main, below are clock tree dump before and after this patch: Before: pll_video_main pll_video_main_bypass pll_video_main_clk lcdif_pixel_src lcdif_pixel_cg lcdif_pixel_pre_div lcdif_pixel_post_div lcdif_pixel_root_clk After: pll_video_main pll_video_main_bypass pll_video_main_clk pll_video_test_div pll_video_post_div lcdif_pixel_src lcdif_pixel_cg lcdif_pixel_pre_div lcdif_pixel_post_div lcdif_pixel_root_clk Signed-off-by: Anson Huang <[email protected]> Reviewed-by: Fabio Estevam <[email protected]> Acked-by: Dong Aisheng <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2018-02-28clk: imx: imx7d: add the Keypad Port module clockStefan Agner1-0/+1
According to the i.MX7D Reference Manual, the Keypad Port module (KPP) requires this clock gate to be enabled. Signed-off-by: Stefan Agner <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2018-02-28clk: imx7d: add CAAM clockRui Miguel Silva1-0/+1
Add CAAM clock so that we could use the Cryptographic Acceleration and Assurance Module (CAAM) hardware block. Cc: Michael Turquette <[email protected]> Cc: Stephen Boyd <[email protected]> Cc: [email protected] Cc: "Horia Geantă" <[email protected]> Cc: Aymen Sghaier <[email protected]> Cc: Fabio Estevam <[email protected]> Cc: Peng Fan <[email protected]> Cc: "David S. Miller" <[email protected]> Cc: Lukas Auer <[email protected]> Reviewed-by: Fabio Estevam <[email protected]> Signed-off-by: Rui Miguel Silva <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2018-02-22clk: imx: imx7d: add the snvs clockAnson Huang1-0/+1
According to the i.MX7D Reference Manual, SNVS block has a clock gate, accessing SNVS block would need this clock gate to be enabled, add it into clock tree so that SNVS module driver can operate this clock gate. Signed-off-by: Anson Huang <[email protected]> Acked-by: Dong Aisheng <[email protected]> Reviewed-by: Fabio Estevam <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2017-11-02clk: imx: imx7d: Remove ARM_M0 clockAdriana Reus1-9/+0
IMX7d does not have an M0 Core and this particular clock doesn't seem connected to anything else. Remove this entry from the CCM driver. Signed-off-by: Adriana Reus <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2017-11-02clk: imx: imx7d: Fix parent clock for OCRAM_CLKAdriana Reus1-1/+1
The parent of OCRAM_CLK should be axi_main_root_clk and not axi_post_div. before: axi_src 1 1 332307692 0 0 axi_cg 1 1 332307692 0 0 axi_pre_div 1 1 332307692 0 0 axi_post_div 1 1 332307692 0 0 ocram_clk 0 0 332307692 0 0 main_axi_root_clk 1 1 332307692 0 0 after: axi_src 1 1 332307692 0 0 axi_cg 1 1 332307692 0 0 axi_pre_div 1 1 332307692 0 0 axi_post_div 1 1 332307692 0 0 main_axi_root_clk 1 1 332307692 0 0 ocram_clk 0 0 332307692 0 0 Reference Doc: i.MX 7D Reference Manual - Chap 5, p 516 (https://www.nxp.com/docs/en/reference-manual/IMX7DRM.pdf) Fixes: 8f6d8094b215 ("ARM: imx: add imx7d clk tree support") Signed-off-by: Adriana Reus <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2017-08-30clk: imx: constify clk_div_tableArvind Yadav1-2/+2
clk_div_table are not supposed to change at runtime. All functions working with clk_div_table provided by <linux/clk-provider.h> work with const clk_div_table. So mark the non-const structs as const. Signed-off-by: Arvind Yadav <[email protected]> Acked-by: Shawn Guo <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2017-06-19clk: imx7d: create clocks behind rawnand clock gateStefan Agner1-2/+4
The rawnand clock gate gates two clocks, NAND_USDHC_BUS_CLK_ROOT and NAND_CLK_ROOT. However, the gate has been in the chain of the latter only. This does not allow to use the NAND_USDHC_BUS_CLK_ROOT only, e.g. as required by APBH-Bridge-DMA. Add new clocks which represent the clock after the gate, and use a shared clock gate to correctly model the hardware. Signed-off-by: Stefan Agner <[email protected]> Tested-by: Fabio Estevam <[email protected]> Acked-by: Han Xu <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2017-06-01clk: imx7d: Fix the powerdown bit location of PLL DDRFabio Estevam1-1/+1
According to the MX7D Reference Manual the powerdown bit of CCM_ANALOG_PLL_DDRn register is bit 20, so fix it accordingly. Signed-off-by: Fabio Estevam <[email protected]> Reviewed-by: Stefan Agner <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2017-04-19clk: imx7d: fix USDHC NAND clockStefan Agner1-2/+1
The USDHC NAND root clock is not gated by any CCM clock gate. Remove the bogus gate definition. Signed-off-by: Stefan Agner <[email protected]> Acked-by: Dong Aisheng <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2017-04-19clk: imx7d: add the missing ipg_root_clkDong Aisheng1-1/+2
Add the missing ipg_root_clk which actually is already used by many orphan clks in current tree. Cc: Shawn Guo <[email protected]> Cc: Fabio Estevam <[email protected]> Reviewed-by: Stefan Agner <[email protected]> Tested-by: Stefan Agner <[email protected]> Signed-off-by: Dong Aisheng <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2017-04-19clk: clk-imx7d: fix ahb clk definitionDong Aisheng1-3/+2
MX7D ahb clk actually has no LPCG gate, current LPCG offset 0x4200 used actually is for adc, not ahb. After fix, correct ocram_s_clk parent accordingly as well. Cc: Shawn Guo <[email protected]> Cc: Fabio Estevam <[email protected]> Reviewed-by: Stefan Agner <[email protected]> Tested-by: Stefan Agner <[email protected]> Signed-off-by: Dong Aisheng <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2017-01-20clk: imx7d: Add the OCOTP clockFabio Estevam1-0/+1
Add the OCOTP so that this hardware block can be used. Signed-off-by: Fabio Estevam <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2016-08-30clk: imx7d: Add PLL_AUDIO_TEST_DIV/POST_DIV clocksFabio Estevam1-40/+61
Currently we see the following error when using the SAI audio driver on mx7: Division by zero in kernel. CPU: 0 PID: 1 Comm: swapper/0 Not tainted 4.8.0-rc3-next-20160823 Hardware name: Freescale i.MX7 Dual (Device Tree) Backtrace: [<c010b70c>] (dump_backtrace) from [<c010b8a8>] (show_stack+0x18) r6:60000013 r5:ffffffff r4:00000000 r3:00000000 [<c010b890>] (show_stack) from [<c03e9324>] (dump_stack+0xb0/0xe) [<c03e9274>] (dump_stack) from [<c010b578>] (__div0+0x18/0x20) r8:00000000 r7:ffffffff r6:ffffffff r5:00000000 r4:00000000 r3:0 [<c010b560>] (__div0) from [<c03e795c>] (Ldiv0_64+0x8/0x18) [<c06cd860>] (divider_get_val) from [<c06cda28>] (clk_divider_se) This error happens due to the lack of definition of the IMX7D_PLL_AUDIO_TEST_DIV/IMX7D_PLL_AUDIO_POST_DIV clocks. Add support for them. Tested on a imx7s-warp board. Signed-off-by: Fabio Estevam <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2016-08-19clk: imx7d: Add SAI IPG clocksFabio Estevam1-3/+10
The SAI_IPG clocks are enabled by the same bits that control SAI_ROOT_CLK clocks, so represent them as shared clocks. Signed-off-by: Fabio Estevam <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2016-08-19clk: imx7d: Add the clock for SDMAFabio Estevam1-0/+1
Add IMX7D_SDMA_CORE_CLK clock so that SDMA can be functional. Signed-off-by: Fabio Estevam <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>