aboutsummaryrefslogtreecommitdiff
path: root/drivers/clk/imx/clk-imx7d.c
AgeCommit message (Collapse)AuthorFilesLines
2016-08-11clk: imx7d: do not set the parent of IMX7D_ENET_AXI_ROOT_SRCFabio Estevam1-2/+0
Booting the kernel on a imx7s-warp leads to several warnings like these: [ 0.000000] ------------[ cut here ]------------ [ 0.000000] WARNING: CPU: 0 PID: 0 at kernel/locking/lockdep.c:3536 lock_release+0x2f8/0x330 [ 0.000000] releasing a pinned lock [ 0.000000] ------------[ cut here ]------------ [ 0.000000] WARNING: CPU: 0 PID: 0 at kernel/locking/lockdep.c:2722 trace_hardirqs_on_caller+0x1ac/0x1f4 [ 0.000000] DEBUG_LOCKS_WARN_ON(unlikely(early_boot_irqs_disabled)) [ 0.000000] ---[ end trace cb88537fdc8fa201 ]--- [ 0.000000] bad: scheduling from the idle thread! [ 0.000000] CPU: 0 PID: 0 Comm: swapper/0 Tainted: G W 4.7.0-rc7-next-20160715 #404 [ 0.000000] ------------[ cut here ]------------ [ 0.000000] WARNING: CPU: 0 PID: 0 at kernel/time/sched_clock.c:179 sched_clock_register+0x44/0x1f8 [ 0.000000] Modules linked in: [ 0.000591] ------------[ cut here ]------------ [ 0.000610] WARNING: CPU: 0 PID: 0 at kernel/time/sched_clock.c:179 sched_clock_register+0x44/0x1f8 [ 0.002084] ------------[ cut here ]------------ [ 0.002104] WARNING: CPU: 0 PID: 0 at init/main.c:576 start_kernel+0x258/0x3b0 [ 0.002114] Interrupts were enabled early This fix is along the same lines as 5e33ebff7edd ("clk: imx7d: do not set parent of ethernet time/ref clocks") and the explanation from that commit is: "The reason for the warning is that setting the parent enables the ENET PLL since we are using CLK_OPS_PARENT_ENABLE. Enabling the ENET PLL can cause clk_pllv3_wait_lock to sleep. See also: commit fc8726a2c021 ("clk: core: support clocks which requires parents enable (part 2)")." imx7s-warp does not even use the FEC interface, so we should not really configure the parent of IMX7D_ENET_AXI_ROOT_SRC in the common MX7 clock driver code. The dts file should use the assigned-clocks/assigned-clock-parents method, so simply remove the configuration of IMX7D_ENET_AXI_ROOT_SRC parent. Signed-off-by: Fabio Estevam <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2016-07-12clk: imx7d: do not set parent of ethernet time/ref clocksStefan Agner1-9/+0
All device trees currently in mainline specify the time clock parent using the assigned-clocks/assigned-clock-parents method, there is no need to statically assign the parent in the core clock driver. Also all current boards provide an Ethernet reference clock for the PHY externally, hence configuring the internal PHY reference clock. Furthermore, and the actual driver of this patch, specify ethernet related parents at that early point in boot leads to a warning: bad: scheduling from the idle thread! The reason for the warning is that setting the parent enables the ENET PLL since we are using CLK_OPS_PARENT_ENABLE. Enabling the ENET PLL can cause clk_pllv3_wait_lock to sleep. See also: commit fc8726a2c021 ("clk: core: support clocks which requires parents enable (part 2)"). Note that setting the ENET AXI root clock parent also requires ENET PLL to be enabled. However, U-Boot typically leaves the ENET PLL on, hence when the framework sets the parent of the first clock, it does not need to wait for the PLL to come up. But because there is currently no user of that clock, the PLL gets disabled after setting the parent. Therefore, subsequent reparenting calls of any clock which somehow rely on the ENET PLL, need to reenable the ENET PLL which leads to a sleep. Removing those subsequent reparenting calls works around this issue. Also remove comments. The code is really verbose enough. Signed-off-by: Stefan Agner <[email protected]> Tested-by: Fabio Estevam <[email protected]> Signed-off-by: Michael Turquette <[email protected]> Link: lkml.kernel.org/r/[email protected]
2016-07-01clk: imx7d: only enable minimum required clocksDong Aisheng1-8/+10
Formerly clk core does not support imx7d clock type well that all its clock operations requires the parent clock on. Therefore we enabled all clocks by default in clock driver initialization for other module clocks operate well. After patch 'clk: imx7d: using api with flag CLK_OPS_PARENT_ENABLE', clk core can handle such clock type well, so we don't have to enable them all by default anymore. Instead, we only enable a minimum required set of clocks. Cc: Michael Turquette <[email protected]> Cc: Stephen Boyd <[email protected]> Cc: Shawn Guo <[email protected]> Signed-off-by: Dong Aisheng <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2016-07-01clk: imx7d: using api with flag CLK_OPS_PARENT_ENABLEDong Aisheng1-357/+357
i.MX7D requires all clocks operations including enable/disable, rate change and re-parent with its parent clock on. Changing to the correct APIs to tell clk core such requirement. Cc: Michael Turquette <[email protected]> Cc: Stephen Boyd <[email protected]> Cc: Shawn Guo <[email protected]> Signed-off-by: Dong Aisheng <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2016-06-12clk: imx: fix pll clock parentsDong Aisheng1-6/+6
pllx_bypass_src mux shouldn't be the parent of pllx clock since it's only valid when when pllx BYPASS bit is set. Thus it is actually one parent of pllx_bypass only. Instead, pllx parent should be fixed to osc according to reference manual. Other plls have the same issue. e.g. before fix, the pll tree is: osc 6 6 24000000 0 0 pll1_bypass_src 0 0 24000000 0 0 pll1 0 0 792000000 0 0 pll1_bypass 0 0 792000000 0 0 pll1_sys 0 0 792000000 0 0 After the fix, it's: osc 6 6 24000000 0 0 pll1 0 0 792000000 0 0 pll1_bypass 0 0 792000000 0 0 pll1_sys 0 0 792000000 0 0 Signed-off-by: Dong Aisheng <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2016-06-12clk: imx7d: correct dram pll typeAnson Huang1-1/+1
DRAM PLL is a audio/video type PLL, need to correct it to get correct ops of PLL. Signed-off-by: Anson Huang <[email protected]> Signed-off-by: Dong Aisheng <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2016-06-12clk: imx7d: correct dram root clk parent selectAnson Huang1-1/+1
DRAM root clk should be either from pll dram main clk or dram alt root clk. Signed-off-by: Anson Huang <[email protected]> Signed-off-by: Dong Aisheng <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2016-05-03clk: imx7d: fix ahb clock mux 1Stefan Agner1-1/+1
The clock parent of the AHB root clock when using mux option 1 is the SYS PLL 270MHz clock. This is specified in Table 5-11 Clock Root Table of the i.MX 7Dual Applications Processor Reference Manual. While it could be a documentation error, the 270MHz parent is also mentioned in the boot ROM configuration in Table 6-28: The clock is by default at 135MHz due to a POST_PODF value of 1 (=> divider of 2). Signed-off-by: Stefan Agner <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2016-04-06clk: imx: add ckil clock for i.MX7Gary Bisson1-1/+2
Add the necessary clock to use the ckil on i.MX7. Inspired from the following patch: https://github.com/boundarydevices/linux-imx6/commit/b80e8271 Signed-off-by: Troy Kisky <[email protected]> Signed-off-by: Gary Bisson <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2015-12-02clk: imx: Replace clk error check with imx_check_clocks()Bai Ping1-4/+1
As we already have a 'imx_check_clocks' to do the clock error check, so cleanup the error check code. Signed-off-by: Bai Ping <[email protected]> Acked-by: Stephen Boyd <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2015-12-02clk: imx: Add a virtual arm clk on i.mx7dBai Ping1-0/+6
Add a virtual arm clk to abstract the actual steps when changing the ARM core frequency.So we can using the 'cpufreq-dt' driver on i.MX7D/Solo. Signed-off-by: Bai Ping <[email protected]> Acked-by: Lucas Stach <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2015-10-09clk: imx7d: add ADC root clockHaibo Chen1-0/+1
Add ADC root clock support in imx7d clock tree. Signed-off-by: Haibo Chen <[email protected]> Acked-by: Stephen Boyd <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2015-09-25clk: imx7d: retain early UART clocks during kernel initLucas Stach1-0/+13
Make sure to keep UART clocks enabled during kernel init if earlyprintk or earlycon are active. Signed-off-by: Lucas Stach <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2015-06-03ARM: imx: add imx7d clk tree supportFrank Li1-0/+860
Add i.MX7D clk tree support. Enable all clock to bring up imx7. Clock framework need be modified a little since imx7d change clock design. otherwise system will halt and block the other part upstream. All clock refine need wait for Dong Aisheng's patch clk: support clocks which requires parent clock on during operation Or other solution ready. Signed-off-by: Anson Huang <[email protected]> Signed-off-by: Adrian Alonso <[email protected]> Signed-off-by: Frank Li <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
Powered by cgit, Gruvboxed by Blaster4385.