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path: root/drivers/clk/actions
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2023-08-22clk: actions: Convert to devm_platform_ioremap_resource()Yangtao Li1-3/+1
Use devm_platform_ioremap_resource() to simplify code. Signed-off-by: Yangtao Li <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
2023-07-19clk: Explicitly include correct DT includesRob Herring2-3/+1
The DT of_device.h and of_platform.h date back to the separate of_platform_bus_type before it as merged into the regular platform bus. As part of that merge prepping Arm DT support 13 years ago, they "temporarily" include each other. They also include platform_device.h and of.h. As a result, there's a pretty much random mix of those include files used throughout the tree. In order to detangle these headers and replace the implicit includes with struct declarations, users need to explicitly include the correct includes. Acked-by: Dinh Nguyen <[email protected]> Acked-by: Krzysztof Kozlowski <[email protected]> # samsung Acked-by: Heiko Stuebner <[email protected]> #rockchip Acked-by: Chanwoo Choi <[email protected]> Acked-by: Geert Uytterhoeven <[email protected]> Reviewed-by: AngeloGioacchino Del Regno <[email protected]> Reviewed-by: Luca Ceresoli <[email protected]> # versaclock5 Signed-off-by: Rob Herring <[email protected]> Link: https://lore.kernel.org/r/[email protected] Acked-by: Abel Vesa <[email protected]> #imx Signed-off-by: Stephen Boyd <[email protected]>
2023-06-08clk: actions: composite: fact: Switch to determine_rateMaxime Ripard1-6/+12
The Actions composite factor clocks implements a mux with a set_parent hook, but doesn't provide a determine_rate implementation. This is a bit odd, since set_parent() is there to, as its name implies, change the parent of a clock. However, the most likely candidate to trigger that parent change is a call to clk_set_rate(), with determine_rate() figuring out which parent is the best suited for a given rate. The other trigger would be a call to clk_set_parent(), but it's far less used, and it doesn't look like there's any obvious user for that clock. So, the set_parent hook is effectively unused, possibly because of an oversight. However, it could also be an explicit decision by the original author to avoid any reparenting but through an explicit call to clk_set_parent(). The driver does implement round_rate() though, which means that we can change the rate of the clock, but we will never get to change the parent. However, It's hard to tell whether it's been done on purpose or not. Since we'll start mandating a determine_rate() implementation, let's convert the round_rate() implementation to a determine_rate(), which will also make the current behavior explicit. And if it was an oversight, the clock behaviour can be adjusted later on. Cc: "Andreas Färber" <[email protected]> Cc: Manivannan Sadhasivam <[email protected]> Cc: [email protected] Cc: [email protected] Signed-off-by: Maxime Ripard <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
2023-06-08clk: actions: composite: div: Switch to determine_rateMaxime Ripard1-5/+11
The Actions composite divider clocks implements a mux with a set_parent hook, but doesn't provide a determine_rate implementation. This is a bit odd, since set_parent() is there to, as its name implies, change the parent of a clock. However, the most likely candidate to trigger that parent change is a call to clk_set_rate(), with determine_rate() figuring out which parent is the best suited for a given rate. The other trigger would be a call to clk_set_parent(), but it's far less used, and it doesn't look like there's any obvious user for that clock. So, the set_parent hook is effectively unused, possibly because of an oversight. However, it could also be an explicit decision by the original author to avoid any reparenting but through an explicit call to clk_set_parent(). The driver does implement round_rate() though, which means that we can change the rate of the clock, but we will never get to change the parent. However, It's hard to tell whether it's been done on purpose or not. Since we'll start mandating a determine_rate() implementation, let's convert the round_rate() implementation to a determine_rate(), which will also make the current behavior explicit. And if it was an oversight, the clock behaviour can be adjusted later on. Cc: "Andreas Färber" <[email protected]> Cc: Manivannan Sadhasivam <[email protected]> Cc: [email protected] Cc: [email protected] Signed-off-by: Maxime Ripard <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
2023-06-08clk: actions: composite: Add a determine_rate hook for pass clkMaxime Ripard1-0/+1
The Actions "Pass" clock implements a mux with a set_parent hook, but doesn't provide a determine_rate implementation. This is a bit odd, since set_parent() is there to, as its name implies, change the parent of a clock. However, the most likely candidates to trigger that parent change are either the assigned-clock-parents device tree property or a call to clk_set_rate(), with determine_rate() figuring out which parent is the best suited for a given rate. The other trigger would be a call to clk_set_parent(), but it's far less used, and it doesn't look like there's any obvious user for that clock. Similarly, it doesn't look like the device tree using that clock driver uses any of the assigned-clock properties. So, the set_parent hook is effectively unused, possibly because of an oversight. However, it could also be an explicit decision by the original author to avoid any reparenting but through an explicit call to clk_set_parent(). The latter case would be equivalent to setting the determine_rate implementation to clk_hw_determine_rate_no_reparent(). Indeed, if no determine_rate implementation is provided, clk_round_rate() (through clk_core_round_rate_nolock()) will call itself on the parent if CLK_SET_RATE_PARENT is set, and will not change the clock rate otherwise. And if it was an oversight, then we are at least explicit about our behavior now and it can be further refined down the line. Cc: "Andreas Färber" <[email protected]> Cc: Manivannan Sadhasivam <[email protected]> Cc: [email protected] Cc: [email protected] Signed-off-by: Maxime Ripard <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
2022-04-22clk: actions: remove redundant assignment after a mask operationColin Ian King1-1/+1
The assignment operation after a & mask operation is redundant, the &= operator can be replaced with just the & operator. Cleans up a clang-scan warning: drivers/clk/actions/owl-pll.c:28:9: warning: Although the value stored to 'mul' is used in the enclosing expression, the value is never actually read from 'mul' [deadcode.DeadStores] Signed-off-by: Colin Ian King <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
2022-03-11clk: actions: Make sentinel elements more obviousJonathan Neuschäfer3-29/+31
The sentinel elements of various tables in drivers/clk/actions can be a bit hard to recognize. Make them easier to see by changing the style from { 0, 0 } to { /* sentinel */ }. Signed-off-by: Jonathan Neuschäfer <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
2022-03-11clk: actions: Terminate clk_div_table with sentinel elementJonathan Neuschäfer2-1/+2
In order that the end of a clk_div_table can be detected, it must be terminated with a sentinel element (.div = 0). In owl-s900.s, the { 0, 8 } element was probably meant to be just that, so this patch changes { 0, 8 } to { 0, 0 }. Fixes: d47317ca4ade1 ("clk: actions: Add S700 SoC clock support") Fixes: d85d20053e195 ("clk: actions: Add S900 SoC clock support") Signed-off-by: Jonathan Neuschäfer <[email protected]> Reviewed-by: Manivannan Sadhasivam <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
2021-11-02clk/actions/owl-factor.c: remove superfluous headersMianhan Liu1-1/+0
owl-factor.c hasn't use any macro or function declared in linux/slab.h. Thus, these files can be removed from owl-factor.c safely without affecting the compilation of the ./drivers/clk module Signed-off-by: Mianhan Liu <[email protected]> Link: https://lore.kernel.org/r/[email protected] Reviewed-by: Manivannan Sadhasivam <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2021-06-27clk: actions: Add NIC and ETHERNET clock support for Actions S500 SoCCristian Ciocaltea1-1/+16
Add support for the missing NIC and ETHERNET clocks in the Actions Semi Owl S500 SoC clock driver. Additionally, change APB clock parent from AHB to the newly added NIC. Signed-off-by: Cristian Ciocaltea <[email protected]> Reviewed-by: Manivannan Sadhasivam <[email protected]> Link: https://lore.kernel.org/r/d62e4f1f85c5cef05be14d9e8143e88bbddd2e0f.1623354574.git.cristian.ciocaltea@gmail.com Signed-off-by: Stephen Boyd <[email protected]>
2021-06-27clk: actions: Fix AHPPREDIV-H-AHB clock chain on Owl S500 SoCCristian Ciocaltea1-8/+11
There are a few issues with the setup of the Actions Semi Owl S500 SoC's clock chain involving AHPPREDIV, H and AHB clocks: * AHBPREDIV clock is defined as a muxer only, although it also acts as a divider. * H clock is using a wrong divider register offset * AHB is defined as a multi-rate factor clock, but it is actually just a fixed pass clock. Let's provide the following fixes: * Change AHBPREDIV clock to an ungated OWL_COMP_DIV definition. * Use the correct register shift value in the OWL_DIVIDER definition for H clock * Drop the unneeded 'ahb_factor_table[]' and change AHB clock to an ungated OWL_COMP_FIXED_FACTOR definition. Fixes: ed6b4795ece4 ("clk: actions: Add clock driver for S500 SoC") Signed-off-by: Cristian Ciocaltea <[email protected]> Link: https://lore.kernel.org/r/21c1abd19a7089b65a34852ac6513961be88cbe1.1623354574.git.cristian.ciocaltea@gmail.com Reviewed-by: Manivannan Sadhasivam <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2021-06-27clk: actions: Fix bisp_factor_table based clocks on Owl S500 SoCCristian Ciocaltea1-15/+29
The following clocks of the Actions Semi Owl S500 SoC have been defined to use a shared clock factor table 'bisp_factor_table[]': DE[1-2], VCE, VDE, BISP, SENSOR[0-1] There are several issues involved in this approach: * 'bisp_factor_table[]' describes the configuration of a regular 8-rates divider, so its usage is redundant. Additionally, judging by the BISP clock context, it is incomplete since it maps only 8 out of 12 possible entries. * The clocks mentioned above are not identical in terms of the available rates, therefore cannot rely on the same factor table. Specifically, BISP and SENSOR* are standard 12-rate dividers so their configuration should rely on a proper clock div table, while VCE and VDE require a factor table that is a actually a subset of the one needed for DE[1-2] clocks. Let's fix this by implementing the following: * Add new factor tables 'de_factor_table' and 'hde_factor_table' to properly handle DE[1-2], VCE and VDE clocks. * Add a common div table 'std12rate_div_table' for BISP and SENSOR[0-1] clocks converted to OWL_COMP_DIV. * Drop the now unused 'bisp_factor_table[]'. Additionally, drop the CLK_IGNORE_UNUSED flag for SENSOR[0-1] since there is no reason to always keep ON those clocks. Fixes: ed6b4795ece4 ("clk: actions: Add clock driver for S500 SoC") Signed-off-by: Cristian Ciocaltea <[email protected]> Reviewed-by: Manivannan Sadhasivam <[email protected]> Link: https://lore.kernel.org/r/e675820a46cd9930d8d576c6cae61d41c1a8416f.1623354574.git.cristian.ciocaltea@gmail.com Signed-off-by: Stephen Boyd <[email protected]>
2021-06-27clk: actions: Fix SD clocks factor table on Owl S500 SoCCristian Ciocaltea1-4/+2
Drop the unsupported entries in the factor table used for the SD[0-2] clocks definitions on the Actions Semi Owl S500 SoC. Fixes: ed6b4795ece4 ("clk: actions: Add clock driver for S500 SoC") Signed-off-by: Cristian Ciocaltea <[email protected]> Reviewed-by: Manivannan Sadhasivam <[email protected]> Link: https://lore.kernel.org/r/196c948d708a22b8198c95f064a0f6b6820f9980.1623354574.git.cristian.ciocaltea@gmail.com Signed-off-by: Stephen Boyd <[email protected]>
2021-06-27clk: actions: Fix UART clock dividers on Owl S500 SoCCristian Ciocaltea1-6/+6
Use correct divider registers for the Actions Semi Owl S500 SoC's UART clocks. Fixes: ed6b4795ece4 ("clk: actions: Add clock driver for S500 SoC") Signed-off-by: Cristian Ciocaltea <[email protected]> Reviewed-by: Manivannan Sadhasivam <[email protected]> Link: https://lore.kernel.org/r/4714d05982b19ac5fec2ed74f54be42d8238e392.1623354574.git.cristian.ciocaltea@gmail.com Signed-off-by: Stephen Boyd <[email protected]>
2020-07-21clk: actions: Add Actions S500 SoC Reset Management Unit supportCristian Ciocaltea1-0/+78
Add Reset Management Unit (RMU) support for Actions Semi S500 SoC. Signed-off-by: Cristian Ciocaltea <[email protected]> Reviewed-by: Manivannan Sadhasivam <[email protected]> Link: https://lore.kernel.org/r/3fba2e6f0edfac97cb8c6ce60f95c24852578eac.1593788312.git.cristian.ciocaltea@gmail.com Signed-off-by: Stephen Boyd <[email protected]>
2020-07-21clk: actions: Add APB, DMAC, GPIO clock support for Actions S500 SoCCristian Ciocaltea1-0/+9
Add support for the missing APB, DMAC and GPIO clocks in the Actions Semi S500 SoC clock driver. Signed-off-by: Cristian Ciocaltea <[email protected]> Link: https://lore.kernel.org/r/87964ae012e513597b8b4c7be2e7ac332a70087a.1593788312.git.cristian.ciocaltea@gmail.com Reviewed-by: Manivannan Sadhasivam <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2020-07-21clk: actions: Fix h_clk for Actions S500 SoCCristian Ciocaltea1-1/+1
The h_clk clock in the Actions Semi S500 SoC clock driver has an invalid parent. Replace with the correct one. Fixes: ed6b4795ece4 ("clk: actions: Add clock driver for S500 SoC") Signed-off-by: Cristian Ciocaltea <[email protected]> Reviewed-by: Manivannan Sadhasivam <[email protected]> Link: https://lore.kernel.org/r/c57e7ebabfa970014f073b92fe95b47d3e5a70b1.1593788312.git.cristian.ciocaltea@gmail.com Signed-off-by: Stephen Boyd <[email protected]>
2019-09-19Merge branches 'clk-cdce-regulator', 'clk-bcm', 'clk-evict-parent-cache' and ↵Stephen Boyd1-4/+3
'clk-actions' into clk-next - Add regulator support to the cdce925 clk driver - Add support for Raspberry Pi 4 bcm2711 SoCs - Evict parents from parent cache when they're unregistered * clk-cdce-regulator: clk: clk-cdce925: Add regulator support dt-bindings: clock: cdce925: Add regulator documentation * clk-bcm: clk: bcm2835: Mark PLLD_PER as CRITICAL clk: bcm2835: Add BCM2711_CLOCK_EMMC2 support clk: bcm2835: Introduce SoC specific clock registration dt-bindings: bcm2835-cprman: Add bcm2711 support * clk-evict-parent-cache: clk: Evict unregistered clks from parent caches * clk-actions: clk: actions: Fix factor clk struct member access
2019-09-17clk: actions: Fix factor clk struct member accessManivannan Sadhasivam1-4/+3
Since the helper "owl_factor_helper_round_rate" is shared between factor and composite clocks, using the factor clk specific helper function like "hw_to_owl_factor" to access its members will create issues when called from composite clk specific code. Hence, pass the "factor_hw" struct pointer directly instead of fetching it using factor clk specific helpers. This issue has been observed when a composite clock like "sd0_clk" tried to call "owl_factor_helper_round_rate" resulting in pointer dereferencing error. While we are at it, let's rename the "clk_val_best" function to "owl_clk_val_best" since this is an owl SoCs specific helper. Fixes: 4bb78fc9744a ("clk: actions: Add factor clock support") Signed-off-by: Manivannan Sadhasivam <[email protected]> Reviewed-by: Stephen Boyd <[email protected]> Link: https://lkml.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
2019-08-16clk: actions: Don't reference clk_init_data after registrationStephen Boyd1-2/+3
A future patch is going to change semantics of clk_register() so that clk_hw::init is guaranteed to be NULL after a clk is registered. Avoid referencing this member here so that we don't run into NULL pointer exceptions. Cc: Manivannan Sadhasivam <[email protected]> Signed-off-by: Stephen Boyd <[email protected]> Link: https://lkml.kernel.org/r/[email protected] [[email protected]: Move name to after checking for error or NULL hw] Acked-by: Manivannan Sadhasivam <[email protected]>
2019-05-21treewide: Add SPDX license identifier - Makefile/KconfigThomas Gleixner2-0/+2
Add SPDX license identifiers to all Make/Kconfig files which: - Have no license information of any form These files fall under the project license, GPL v2 only. The resulting SPDX license identifier is: GPL-2.0-only Signed-off-by: Thomas Gleixner <[email protected]> Signed-off-by: Greg Kroah-Hartman <[email protected]>
2019-05-01clk: actions: Use the correct style for SPDX License IdentifierNishad Kamdar9-9/+9
This patch corrects the SPDX License Identifier style in header files related to Clock Drivers for Actions Semi Socs. For C header files Documentation/process/license-rules.rst mandates C-like comments (opposed to C source files where C++ style should be used) Changes made by using a script provided by Joe Perches here: https://lkml.org/lkml/2019/2/7/46 Suggested-by: Joe Perches <[email protected]> Signed-off-by: Nishad Kamdar <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2019-02-22clk: actions: Add clock driver for S500 SoCManivannan Sadhasivam3-0/+531
Add common clock driver for Actions Semi S500 SoC. Signed-off-by: Edgar Bernardi Righi <[email protected]> [Mani: cleaned up the driver] Signed-off-by: Manivannan Sadhasivam <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2019-02-21clk: actions: Add configurable PLL delayManivannan Sadhasivam2-7/+25
S500 SoC requires configurable delay for different PLLs. Hence, add a separate macro for declaring a PLL with configurable delay and also modify the existing OWL_PLL_NO_PARENT macro to use default delay so that no need to modify the existing S700/S900 drivers. Signed-off-by: Manivannan Sadhasivam <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2018-10-16clk: actions: Add Actions Semi S900 SoC Reset Management Unit supportManivannan Sadhasivam1-0/+82
Add Reset Management Unit (RMU) support for Actions Semi S900 SoC. Signed-off-by: Manivannan Sadhasivam <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2018-10-16clk: actions: Add Actions Semi S700 SoC Reset Management Unit supportManivannan Sadhasivam1-0/+51
Add Reset Management Unit (RMU) support for Actions Semi S700 SoC. Signed-off-by: Manivannan Sadhasivam <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2018-10-16clk: actions: Add Actions Semi Owl SoCs Reset Management Unit supportManivannan Sadhasivam5-0/+101
Add Reset Management Unit (RMU) support for Actions Semi Owl SoCs. Signed-off-by: Manivannan Sadhasivam <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2018-10-16clk: actions: Cache regmap info in private clock descriptorManivannan Sadhasivam4-6/+8
In order to support the reset controller, regmap info needs to be cached in the private clock descriptor, owl_clk_desc. Hence, save that and also make the clock descriptor struct non const. Signed-off-by: Manivannan Sadhasivam <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2018-07-25clk: actions: Add S700 SoC clock supportSaravanan Sekar3-0/+613
Add Actions Semi S700 SoC clock support Signed-off-by: Parthiban Nallathambi <[email protected]> Signed-off-by: Saravanan Sekar <[email protected]> Reviewed-by: Manivannan Sadhasivam <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2018-07-25clk: actions: Add missing REGMAP_MMIO dependencySaravanan Sekar1-0/+1
Add REGMAP_MMIO as dependency to avoid undefined reference to regmap symbols. Fixes: d85d20053e19 ("clk: actions: Add S900 SoC clock support") Signed-off-by: Saravanan Sekar <[email protected]> Reviewed-by: Andreas Färber <[email protected]> Reviewed-by: Manivannan Sadhasivam <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2018-04-06clk: actions: Add S900 SoC clock supportManivannan Sadhasivam3-0/+734
Add Actions Semi S900 SoC clock support. Signed-off-by: Manivannan Sadhasivam <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2018-04-06clk: actions: Add pll clock supportManivannan Sadhasivam3-0/+287
Add support for Actions Semi PLL clock. Signed-off-by: Manivannan Sadhasivam <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2018-04-06clk: actions: Add composite clock supportManivannan Sadhasivam3-0/+324
Add support for Actions Semi composite clock. This clock consists of gate, mux, divider, factor and fixed factor clocks. Signed-off-by: Manivannan Sadhasivam <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2018-04-06clk: actions: Add fixed factor clock supportManivannan Sadhasivam1-0/+28
Add support for Actions Semi fixed factor clock reusing the clk ops from common clock driver. Signed-off-by: Manivannan Sadhasivam <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2018-04-06clk: actions: Add factor clock supportManivannan Sadhasivam3-0/+306
Add support for Actions Semi factor clock together with helper functions to be used in composite clock. Signed-off-by: Manivannan Sadhasivam <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2018-04-06clk: actions: Add divider clock supportManivannan Sadhasivam3-0/+170
Add support for Actions Semi divider clock together with helper functions to be used in composite clock. Signed-off-by: Manivannan Sadhasivam <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2018-04-06clk: actions: Add mux clock supportManivannan Sadhasivam3-0/+122
Add support for Actions Semi mux clock together with helper functions to be used in composite clock. Signed-off-by: Manivannan Sadhasivam <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2018-04-06clk: actions: Add gate clock supportManivannan Sadhasivam3-0/+151
Add support for Actions Semi gate clock together with helper functions to be used in composite clock. Signed-off-by: Manivannan Sadhasivam <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2018-04-06clk: actions: Add common clock driver supportManivannan Sadhasivam4-0/+137
Add support for Actions Semi common clock driver with generic structures and interface functions. Signed-off-by: Manivannan Sadhasivam <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
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