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2015-09-22x86/numachip: Introduce Numachip2 timer mechanismsDaniel J Blueman1-0/+9
Add 1GHz 64-bit Numachip2 clocksource timer support for accurate system-wide timekeeping, as core TSCs are unsynchronised. Additionally, add a per-core clockevent mechanism that interrupts via the platform IPI vector after a programmed period. [ tglx: Taking it through x86 due to dependencies ] Signed-off-by: Daniel J Blueman <[email protected]> Acked-by: Steffen Persvold <[email protected]> Cc: Daniel Lezcano <[email protected]> Link: http://lkml.kernel.org/r/[email protected] Signed-off-by: Thomas Gleixner <[email protected]>
2015-09-22x86/numachip: Add Numachip IPI optimisationsDaniel J Blueman1-0/+1
When sending IPIs, first check if the non-local part of the source and destination APIC IDs match; if so, send via the local APIC for efficiency. Secondly, since the AMD BIOS-kernel developer guide states IPI delivery will occur invarient of prior deliver status, avoid polling the delivery status bit for efficiency. Signed-off-by: Daniel J Blueman <[email protected]> Acked-by: Steffen Persvold <[email protected]> Cc: Daniel Lezcano <[email protected]> Link: http://lkml.kernel.org/r/[email protected] Signed-off-by: Thomas Gleixner <[email protected]>
2015-09-22x86/numachip: Add Numachip2 APIC supportDaniel J Blueman2-0/+36
Introduce support for Numachip2 remote interrupts via detecting the right ACPI SRAT signature. Access is performed via a fixed mapping in the x86 physical address space. Signed-off-by: Daniel J Blueman <[email protected]> Acked-by: Steffen Persvold <[email protected]> Cc: Daniel Lezcano <[email protected]> Link: http://lkml.kernel.org/r/[email protected] Signed-off-by: Thomas Gleixner <[email protected]>
2015-09-22x86/numachip: Cleanup Numachip supportDaniel J Blueman1-116/+2
Drop unused code and includes in Numachip header files and APIC driver. Additionally, use the 'numachip1' prefix on Numachip1-specific functions; this prepares for adding Numachip2 support in later patches. Signed-off-by: Daniel J Blueman <[email protected]> Acked-by: Steffen Persvold <[email protected]> Cc: Daniel Lezcano <[email protected]> Link: http://lkml.kernel.org/r/[email protected] Signed-off-by: Thomas Gleixner <[email protected]>
2012-12-07x86/PCI: Add NumaChip remote PCI supportDaniel J Blueman1-0/+19
Add NumaChip-specific PCI access mechanism via MMCONFIG cycles, but preventing access to AMD Northbridges which shouldn't respond. Signed-off-by: Daniel J Blueman <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]>
2011-12-05x86: Add NumaChip supportSteffen Persvold1-0/+167
Adds support for Numascale NumaChip large-SMP systems. It is needed to enable the booting of more than ~168 cores. v2: - [Steffen] enumerate only accessible northbridges - [Daniel] rediffed and validated against 3.1-rc10 v3: - [Daniel] use x86_init core numbering override - [Daniel] cleanups as per feedback v4: - [Daniel] use updated x86_cpuinit override v5: - drop disabling interrupts locally, as ISR write is atomic; drop delay - added read-mostly annotations where appropriate - require CONFIG_SMP, so drop conditional path Workload tested on 96 cores/16 sockets. Signed-off-by: Steffen Persvold <[email protected]> Signed-off-by: Daniel J Blueman <[email protected]> Cc: Jesse Barnes <[email protected]> Link: http://lkml.kernel.org/r/[email protected] Signed-off-by: Ingo Molnar <[email protected]>
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