| Age | Commit message (Expand) | Author | Files | Lines |
|---|
| 2021-09-08 | trap: cleanup trap_init() | Kefeng Wang | 1 | -5/+0 |
| 2021-07-09 | Merge tag 'riscv-for-linus-5.14-mw0' of git://git.kernel.org/pub/scm/linux/ke... | Linus Torvalds | 1 | -0/+35 |
| 2021-07-06 | riscv: add VMAP_STACK overflow detection | Tong Tiangen | 1 | -0/+35 |
| 2021-06-10 | riscv: xip: support runtime trap patching | Vitaly Wool | 1 | -4/+9 |
| 2021-05-06 | riscv: remove unused handle_exception symbol | Rouven Czerwinski | 1 | -2/+0 |
| 2021-05-06 | Merge tag 'riscv-for-linus-5.13-mw0' of git://git.kernel.org/pub/scm/linux/ke... | Linus Torvalds | 1 | -1/+1 |
| 2021-04-26 | riscv: add __init section marker to some functions | Jisheng Zhang | 1 | -1/+1 |
| 2021-04-15 | riscv: add do_page_fault and do_trap_break into the kprobes blacklist | Jisheng Zhang | 1 | -0/+1 |
| 2021-03-09 | riscv: traps: Fix no prototype warnings | Nanyong Sun | 1 | -0/+1 |
| 2021-01-14 | riscv: Add dump stack in show_regs | Kefeng Wang | 1 | -1/+2 |
| 2021-01-14 | riscv: Add uprobes supported | Guo Ren | 1 | -0/+10 |
| 2021-01-14 | riscv: Add kprobes supported | Guo Ren | 1 | -0/+9 |
| 2020-07-30 | RISC-V: Setup exception vector early | Atish Patra | 1 | -7/+1 |
| 2020-06-18 | maccess: rename probe_kernel_address to get_kernel_nofault | Christoph Hellwig | 1 | -2/+2 |
| 2020-06-09 | irqchip: RISC-V per-HART local interrupt controller driver | Anup Patel | 1 | -2/+0 |
| 2020-05-18 | riscv: Add KGDB support | Vincent Chen | 1 | -0/+5 |
| 2020-04-09 | Merge tag 'riscv-for-linus-5.7' of git://git.kernel.org/pub/scm/linux/kernel/... | Linus Torvalds | 1 | -5/+27 |
| 2020-04-03 | riscv: Unaligned load/store handling for M_MODE | Damien Le Moal | 1 | -3/+24 |
| 2020-03-31 | RISC-V: Add supported for ordered booting method using HSM | Atish Patra | 1 | -1/+1 |
| 2020-03-26 | riscv: add macro to get instruction length | Zong Li | 1 | -1/+2 |
| 2020-03-16 | irqchip/sifive-plic: Enable/Disable external interrupts upon cpu online/offline | Atish Patra | 1 | -1/+1 |
| 2020-02-18 | RISC-V: Don't enable all interrupts in trap_init() | Anup Patel | 1 | -2/+2 |
| 2019-11-05 | riscv: abstract out CSR names for supervisor vs machine mode | Christoph Hellwig | 1 | -8/+8 |
| 2019-10-28 | riscv: for C functions called only from assembly, mark with __visible | Paul Walmsley | 1 | -2/+2 |
| 2019-10-28 | riscv: add missing header file includes | Paul Walmsley | 1 | -0/+1 |
| 2019-10-25 | riscv: cleanup do_trap_break | Christoph Hellwig | 1 | -20/+6 |
| 2019-10-14 | riscv: remove the switch statement in do_trap_break() | Vincent Chen | 1 | -11/+11 |
| 2019-10-07 | riscv: Correct the handling of unexpected ebreak in do_trap_break() | Vincent Chen | 1 | -3/+3 |
| 2019-10-07 | riscv: avoid sending a SIGTRAP to a user thread trapped in WARN() | Vincent Chen | 1 | -1/+1 |
| 2019-10-07 | riscv: avoid kernel hangs when trapped in BUG() | Vincent Chen | 1 | -3/+3 |
| 2019-07-08 | Merge branch 'siginfo-linus' of git://git.kernel.org/pub/scm/linux/kernel/git... | Linus Torvalds | 1 | -5/+6 |
| 2019-06-05 | treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 286 | Thomas Gleixner | 1 | -9/+1 |
| 2019-05-29 | signal: Remove the task parameter from force_sig_fault | Eric W. Biederman | 1 | -2/+2 |
| 2019-05-29 | signal: Explicitly call force_sig_fault on current | Eric W. Biederman | 1 | -1/+1 |
| 2019-05-29 | signal/riscv: Remove tsk parameter from do_trap | Eric W. Biederman | 1 | -3/+4 |
| 2019-05-16 | riscv: Support BUG() in kernel module | Vincent Chen | 1 | -1/+1 |
| 2019-05-16 | riscv: Add the support for c.ebreak check in is_valid_bugaddr() | Vincent Chen | 1 | -3/+17 |
| 2019-05-16 | RISC-V: Access CSRs using CSR numbers | Anup Patel | 1 | -3/+3 |
| 2019-04-25 | riscv: remove duplicate macros from ptrace.h | Christoph Hellwig | 1 | -1/+1 |
| 2018-08-13 | RISC-V: Don't increment sepc after breakpoint. | Jim Wilson | 1 | -1/+0 |
| 2018-06-16 | Merge tag 'riscv-for-linus-4.18-merge_window' of git://git.kernel.org/pub/scm... | Linus Torvalds | 1 | -1/+1 |
| 2018-06-07 | riscv: no __user for probe_kernel_address() | Luc Van Oostenryck | 1 | -1/+1 |
| 2018-04-25 | signal/riscv: Replace do_trap_siginfo with force_sig_fault | Eric W. Biederman | 1 | -8/+2 |
| 2018-04-25 | signal/riscv: Use force_sig_fault where appropriate | Eric W. Biederman | 1 | -8/+1 |
| 2018-04-25 | signal: Ensure every siginfo we send has all bits initialized | Eric W. Biederman | 1 | -0/+1 |
| 2017-09-26 | RISC-V: Init and Halt Code | Palmer Dabbelt | 1 | -0/+180 |