| Age | Commit message (Expand) | Author | Files | Lines |
|---|---|---|---|---|
| 2019-05-16 | RISC-V: Avoid using invalid intermediate translations | Palmer Dabbelt | 1 | -2/+10 |
| 2019-05-16 | RISC-V: Access CSRs using CSR numbers | Anup Patel | 1 | -8/+8 |
| 2019-04-25 | riscv: cleanup the parse_dtb calling conventions | Christoph Hellwig | 1 | -2/+1 |
| 2019-04-25 | riscv: simplify the stack pointer setup in head.S | Christoph Hellwig | 1 | -4/+1 |
| 2019-04-25 | riscv: clear all pending interrupts when booting | Christoph Hellwig | 1 | -1/+2 |
| 2018-11-20 | RISC-V: Build flat and compressed kernel images | Anup Patel | 1 | -0/+10 |
| 2018-10-22 | RISC-V: Use Linux logical CPU number instead of hartid | Atish Patra | 1 | -1/+3 |
| 2018-08-13 | RISC-V: Add the directive for alignment of stvec's value | Zong Li | 1 | -0/+2 |
| 2018-02-20 | Rename sbi_save to parse_dtb to improve code readability | Michael Clark | 1 | -1/+1 |
| 2018-01-30 | riscv: rename sptbr to satp | Christoph Hellwig | 1 | -3/+3 |
| 2017-11-30 | RISC-V: move empty_zero_page definition to C and export it | Olof Johansson | 1 | -3/+0 |
| 2017-09-26 | RISC-V: Init and Halt Code | Palmer Dabbelt | 1 | -0/+157 |