aboutsummaryrefslogtreecommitdiff
path: root/arch/riscv/kernel/cpufeature.c
AgeCommit message (Expand)AuthorFilesLines
2024-09-15Merge patch series "Svvptc extension to remove preventive sfence.vma"Palmer Dabbelt1-0/+1
2024-09-15riscv: Add ISA extension parsing for SvvptcAlexandre Ghiti1-0/+1
2024-07-31riscv: cpufeature: Do not drop Linux-internal extensionsSamuel Holland1-8/+6
2024-07-22riscv: Extend cpufeature.c to detect vendor extensionsCharlie Jenkins1-40/+103
2024-07-12Merge patch series "riscv: Apply Zawrs when available"Palmer Dabbelt1-0/+1
2024-07-12riscv: Add Zawrs support for spinlocksChristoph Müllner1-0/+1
2024-06-26riscv: add ISA extension parsing for ZcmopClément Léger1-0/+1
2024-06-26riscv: add ISA parsing for Zca, Zcf, Zcd and ZcbClément Léger1-1/+54
2024-06-26riscv: add ISA extensions validation callbackClément Léger1-85/+135
2024-06-26riscv: add ISA extension parsing for ZimopClément Léger1-0/+1
2024-05-30riscv: vector: adjust minimum Vector requirement to ZVE32XAndy Chiu1-1/+4
2024-05-30riscv: cpufeature: add zve32[xf] and zve64[xfd] isa detectionAndy Chiu1-1/+40
2024-05-30riscv: cpufeature: call match_isa_ext() for single-letter extensionsAndy Chiu1-6/+5
2024-05-30riscv: vector: add a comment when calling riscv_setup_vsize()Andy Chiu1-0/+3
2024-05-22riscv: cpufeature: Fix extension subset checkingCharlie Jenkins1-1/+1
2024-05-22riscv: cpufeature: Fix thead vector hwcap removalCharlie Jenkins1-2/+6
2024-03-22Merge tag 'riscv-for-linus-6.9-mw2' of git://git.kernel.org/pub/scm/linux/ker...Linus Torvalds1-255/+1
2024-03-13Merge patch series "riscv: Use Kconfig to set unaligned access speed"Palmer Dabbelt1-255/+0
2024-03-13riscv: Set unaligned access speed at compile timeCharlie Jenkins1-272/+0
2024-03-13riscv: Decouple emulated unaligned accesses from access speedCharlie Jenkins1-4/+21
2024-03-13riscv: lib: Introduce has_fast_unaligned_access()Charlie Jenkins1-3/+3
2024-03-12perf: RISC-V: Introduce Andes PMU to support perf event samplingYu Chien Peter Lin1-0/+1
2024-02-29Merge patch series "riscv: cbo.zero fixes"Palmer Dabbelt1-3/+13
2024-02-29riscv: Add a custom ISA extension for the [ms]envcfg CSRSamuel Holland1-2/+12
2024-02-29riscv: Fix enabling cbo.zero when running in M-modeSamuel Holland1-1/+1
2024-02-23RISC-V: Ignore V from the riscv,isa DT property on older T-Head CPUsConor Dooley1-0/+15
2024-01-17Merge patch series "riscv: Add fine-tuned checksum functions"Palmer Dabbelt1-3/+87
2024-01-17riscv: Add static key for misaligned accessesCharlie Jenkins1-3/+87
2024-01-09Merge patch series "riscv: hwprobe: add Zicond, Zacas and Ztso support"Palmer Dabbelt1-0/+2
2024-01-09riscv: add ISA extension parsing for ZacasClément Léger1-0/+1
2024-01-09riscv: add ISA extension parsing for ZtsoClément Léger1-0/+1
2024-01-03RISC-V: Remove the removed single-letter extensionsPalmer Dabbelt1-4/+0
2023-12-12riscv: add ISA extension parsing for ZfaClément Léger1-0/+1
2023-12-12riscv: add ISA extension parsing for Zvfh[min]Clément Léger1-0/+2
2023-12-12riscv: add ISA extension parsing for ZihintntlClément Léger1-0/+1
2023-12-12riscv: add ISA extension parsing for Zfh/Zfh[min]Clément Léger1-0/+2
2023-12-12riscv: add ISA extension parsing for vector cryptoClément Léger1-0/+64
2023-12-12riscv: add ISA extension parsing for scalar cryptoEvan Green1-23/+95
2023-12-12riscv: add ISA extension parsing for ZbcClément Léger1-0/+1
2023-11-10Merge tag 'riscv-for-linus-6.7-mw2' of git://git.kernel.org/pub/scm/linux/ker...Linus Torvalds1-13/+79
2023-11-08Merge tag 'riscv-for-linus-6.7-rc1' of git://git.kernel.org/pub/scm/linux/ker...Linus Torvalds1-5/+12
2023-11-07RISC-V: Probe misaligned access speed in parallelEvan Green1-19/+77
2023-11-05riscv: don't probe unaligned access speed if already doneJisheng Zhang1-0/+4
2023-11-05Merge patch series "Add support to handle misaligned accesses in S-mode"Palmer Dabbelt1-1/+5
2023-11-01riscv: report misaligned accesses emulation to hwprobeClément Léger1-0/+4
2023-11-01riscv: annotate check_unaligned_access_boot_cpu() with __initClément Léger1-1/+1
2023-10-31RISC-V: clarify the QEMU workaround in ISA parserTsukasa OI1-3/+4
2023-10-12RISC-V: Detect Zicond from ISA stringAnup Patel1-0/+1
2023-10-12RISC-V: Detect Smstateen extensionMayuresh Chitale1-0/+1
2023-09-21RISC-V: Enable cbo.zero in usermodeAndrew Jones1-0/+6