| Age | Commit message (Expand) | Author | Files | Lines |
|---|---|---|---|---|
| 2019-11-17 | riscv: clear the instruction cache and all registers when booting | Christoph Hellwig | 1 | -0/+1 |
| 2019-11-17 | riscv: read the hart ID from mhartid on boot | Damien Le Moal | 1 | -0/+1 |
| 2019-11-05 | riscv: abstract out CSR names for supervisor vs machine mode | Christoph Hellwig | 1 | -10/+62 |
| 2019-06-05 | treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 286 | Thomas Gleixner | 1 | -9/+1 |
| 2019-05-16 | RISC-V: Access CSRs using CSR numbers | Anup Patel | 1 | -7/+25 |
| 2019-05-16 | RISC-V: Add interrupt related SCAUSE defines in asm/csr.h | Anup Patel | 1 | -4/+17 |
| 2019-05-16 | RISC-V: Use tabs to align macro values in asm/csr.h | Anup Patel | 1 | -38/+38 |
| 2018-08-13 | RISC-V: add a definition for the SIE SEIE bit | Christoph Hellwig | 1 | -0/+1 |
| 2018-01-30 | riscv: rename sptbr to satp | Christoph Hellwig | 1 | -7/+7 |
| 2018-01-07 | riscv: rename SR_* constants to match the spec | Christoph Hellwig | 1 | -4/+4 |
| 2017-09-26 | RISC-V: Generic library routines and assembly | Palmer Dabbelt | 1 | -0/+132 |