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2024-10-23riscv: dts: starfive: Update ethernet phy0 delay parameter values for Star64E Shattow1-2/+1
Improve function of Star64 bottom network port phy0 with updated delay values. Initial upstream patches supporting Star64 use the same vendor board support package parameters known to result in an unreliable bottom network port. Success acquiring DHCP lease and no dropped packets to ping LAN address: rx 900: tx 1500 1650 1800 1950 rx 750: tx 1650 1800 1950 rx 600: tx 1800 1950 rx 1050: tx 1650 1800 1950 rx 1200: tx 1500 1650 1800 1950 rx 1350: tx 1500 1650 1800 1950 rx 1500: tx 1500 1650 1800 1950 rx 1650: tx 1500 1650 1800 1950 rx 1800: tx 1500 1650 1800 1950 rx 1900: tx 1950 rx 1950: tx 1950 Failure acquiring DHCP lease or many dropped packets: rx 450: tx 1500 1800 1950 rx 600: tx 1200 1350 1650 rx 750: tx 1350 1500 rx 900: tx 1200 1350 rx 1050: tx 1050 1200 1350 1500 rx 1200: tx 1350 rx 1350: tx 1350 rx 1500: tx 1200 1350 rx 1650: tx 1050 1200 1350 rx 1800: tx 1050 1200 1350 rx 1900: tx 1500 1650 1800 rx 1950: tx 1200 1350 Non-functional: rx 0: tx 0 150 300 450 600 750 900 1050 1200 1350 1500 1650 1800 1950 rx 150: tx 0 150 300 450 600 750 900 1050 1200 1350 1500 1650 1800 1950 rx 300: tx 0 150 300 450 600 750 900 1050 1200 1350 1500 1650 1800 1950 rx 450: tx 0 150 300 450 600 750 900 1050 1200 1350 1650 rx 600: tx 0 150 300 450 600 750 900 1050 rx 750: tx 0 150 300 450 600 750 900 1050 1200 rx 900: tx 0 150 300 450 600 750 900 1050 rx 1050: tx 0 150 300 450 600 750 900 rx 1200: tx 0 150 300 450 600 750 900 1050 1200 rx 1350: tx 0 150 300 450 600 750 900 1050 1200 rx 1500: tx 0 150 300 450 600 750 900 1050 rx 1650: tx 0 150 300 450 600 750 900 rx 1800: tx 0 150 300 450 600 750 900 rx 1900: tx 0 150 300 450 600 750 900 1050 1200 1350 rx 1950: tx 0 150 300 450 600 750 900 1050 Selecting the median of all working rx delay values 1500 combined with tx delay values 1500, 1650, 1800, and 1950 only the tx delay value of 1950 (default) is reliable as tested in both Linux 6.11.2 and U-Boot v2024.10 Signed-off-by: E Shattow <[email protected]> CC: [email protected] Fixes: 2606bf583b962 ("riscv: dts: starfive: add Star64 board devicetree") Acked-by: Emil Renner Berthing <[email protected]> Signed-off-by: Conor Dooley <[email protected]>
2024-10-17riscv: dts: starfive: disable unused csi/camss nodesConor Dooley1-2/+0
Aurelien reported probe failures due to the csi node being enabled without having a camera attached to it. A camera was in the initial submissions, but was removed from the dts, as it had not actually been present on the board, but was from an addon board used by the developer of the relevant drivers. The non-camera pipeline nodes were not disabled when this happened and the probe failures are problematic for Debian. Disable them. CC: [email protected] Fixes: 28ecaaa5af192 ("riscv: dts: starfive: jh7110: Add camera subsystem nodes") Closes: https://lore.kernel.org/all/[email protected]/ Reported-by: Aurelien Jarno <[email protected]> Reviewed-by: Emil Renner Berthing <[email protected]> Tested-by: Aurelien Jarno <[email protected]> Reviewed-by: Aurelien Jarno <[email protected]> Signed-off-by: Conor Dooley <[email protected]>
2024-09-08riscv: dts: starfive: jh7110-common: Fix lower rate of CPUfreq by setting ↵Xingyu Wu1-0/+6
PLL0 rate to 1.5GHz CPUfreq supports 4 cpu frequency loads on 375/500/750/1500MHz. But now PLL0 rate is 1GHz and the cpu frequency loads become 250/333/500/1000MHz in fact. The PLL0 rate should be default set to 1.5GHz and set the cpu_core rate to 500MHz in safe. Fixes: e2c510d6d630 ("riscv: dts: starfive: Add cpu scaling for JH7110 SoC") Signed-off-by: Xingyu Wu <[email protected]> Reviewed-by: Hal Feng <[email protected]> Signed-off-by: Conor Dooley <[email protected]>
2024-07-19Merge tag 'tty-6.11-rc1' of ↵Linus Torvalds1-12/+18
git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/tty Pull tty / serial updates from Greg KH: "Here is a small set of tty and serial driver updates for 6.11-rc1. Not much happened this cycle, unlike the previous kernel release which had lots of "excitement" in this part of the kernel. Included in here are the following changes: - dt binding updates for new platforms - 8250 driver updates - various small serial driver fixes and updates - printk/console naming and matching attempt #2 (was reverted for 6.10-final, should be good to go this time around, acked by the relevant maintainers). All of these have been in linux-next for a while with no reported issues" * tag 'tty-6.11-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/tty: (22 commits) Documentation: kernel-parameters: Add DEVNAME:0.0 format for serial ports serial: core: Add serial_base_match_and_update_preferred_console() printk: Add match_devname_and_update_preferred_console() serial: sc16is7xx: hardware reset chip if reset-gpios is defined in DT dt-bindings: serial: sc16is7xx: add reset-gpios dt-bindings: serial: vt8500-uart: convert to json-schema serial: 8250_platform: Explicitly show we initialise ISA ports only once tty: add missing MODULE_DESCRIPTION() macros dt-bindings: serial: mediatek,uart: add MT7988 serial: sh-sci: Add support for RZ/V2H(P) SoC dt-bindings: serial: Add documentation for Renesas RZ/V2H(P) (R9A09G057) SCIF support dt-bindings: serial: renesas,scif: Make 'interrupt-names' property as required dt-bindings: serial: renesas,scif: Validate 'interrupts' and 'interrupt-names' dt-bindings: serial: renesas,scif: Move ref for serial.yaml at the end riscv: dts: starfive: jh7110: Add the core reset and jh7110 compatible for uarts serial: 8250_dw: Use reset array API to get resets dt-bindings: serial: snps-dw-apb-uart: Add one more reset signal for StarFive JH7110 SoC serial: 8250: Extract platform driver serial: 8250: Extract RSA bits serial: imx: stop casting struct uart_port to struct imx_port ...
2024-07-16Merge tag 'soc-dt-6.11' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/socLinus Torvalds6-5/+231
Pull SoC dt updates from Arnd Bergmann: "The devicetree updates are fairly well spread out across platforms, with Qualcomm making up about a third of the total. There are three new SoCs in existing product families this: - NXP i.MX95 is a variant of i.MX93, now with six Cortex-A55 cores instead of just two as well as a GPU and more high-speed I/O devices. - Qualcomm QCS8550 is a variant of SM8550 for IOT devices - Airoha EN7581 is a 10G-PON network chip and related to the MT7981 Wireless router chip from its parent Mediatek. In total there are 58 new machines, including four riscv boards and eight for 32-bit arm. The most exciting new addition is probably a pair of laptops based on the Qualcomm x1e80100 (Snapdragon X1 Elite) chip, the Asus Vivobook S15 and the Lenovo Yoga Slim7x. Other noteworthy new additions are: - A total of 20 Qualcomm based machines, mostly Android devices from Samsung, Motorola and LG, as well as a wireless router and some reference designs - Six NXP i.MX based machines, mostly industrial boards along with some reference designs - Mediatek sees some interesting Filogic based routers including the "OpenWRT One", a few new Chromebooks as well as single-board computers. - Four machines from Solidrun based on Marvell cn913x, replacing the older Armada 8000 based counterparts - The four Amlogic machines are all set top boxes or reference designs for them - The nine new Rockchips machines are mostly single-board computers including some interesting ones based on the rk3588 chip like the ROCK 5 ITX board and the CM3588 with its four NVMe slots - The RISC-V boards are all single-board computers based on Starfive JH7110, Microchip MPFS and Allwinner D1, which all had similar boards already There are also a lot of updates to already supported machines, notably for the TI K3, Rockchips, Freescale and of course Qualcomm platforms" * tag 'soc-dt-6.11' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (846 commits) arm64: dts: allwinner: h616: add crypto engine node riscv: dts: add clock generator for Sophgo SG2042 SoC arm64: dts: rockchip: Add Xunlong Orange Pi 3B dt-bindings: arm: rockchip: Add Xunlong Orange Pi 3B arm64: dts: rockchip: Add Radxa ROCK 3B dt-bindings: arm: rockchip: Add Radxa ROCK 3B mailmap: Update Luca Weiss's email address ARM: dts: ixp4xx: nslu2: beeper uses PWM arm64: dts: rockchip: add ROCK 5 ITX board dt-bindings: arm: rockchip: Add ROCK 5 ITX board arm64: dts: rockchip: Add dma-names to uart1 on Pine64 rk3566 devices arm64: dts: rockchip: Add avdd supplies to hdmi on rock64 arm64: dts: qcom: msm8916-lg-c50: add initial dts for LG Leon LTE arm64: dts: qcom: msm8916-lg-m216: Add initial device tree dt-bindings: arm: qcom: Add msm8916 based LG devices ARM: dts: qcom: msm8960: correct memory base arm64: dts: qcom: ipq9574: Add icc provider ability to gcc dt-bindings: interconnect: Add Qualcomm IPQ9574 support arm64: dts: qcom: sm8150: Add video clock controller node arm64: dts: qcom: pm6150: Add vibrator ...
2024-07-01riscv: dts: starfive: add PCIe dts configuration for JH7110Minda Chen5-0/+167
Add PCIe dts configuraion for JH7110 SoC platform. The Star64 only has one exposed PCIe port, so only the Mars and VisionFive 2 get two enabled. Signed-off-by: Minda Chen <[email protected]> Reviewed-by: Hal Feng <[email protected]> [conor: squash in star64's single exposed port] Signed-off-by: Conor Dooley <[email protected]>
2024-06-24riscv: dts: starfive: jh7110: Add the core reset and jh7110 compatible for uartsHal Feng1-12/+18
Add the core reset for uarts, which is necessary for uarts to work. Signed-off-by: Hal Feng <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Greg Kroah-Hartman <[email protected]>
2024-06-19riscv: dts: starfive: Set EMMC vqmmc maximum voltage to 3.3V on JH7110 boardsShengyu Qu1-1/+1
Currently, for JH7110 boards with EMMC slot, vqmmc voltage for EMMC is fixed to 1.8V, while the spec needs it to be 3.3V on low speed mode and should support switching to 1.8V when using higher speed mode. Since there are no other peripherals using the same voltage source of EMMC's vqmmc(ALDO4) on every board currently supported by mainline kernel, regulator-max-microvolt of ALDO4 should be set to 3.3V. Cc: [email protected] Signed-off-by: Shengyu Qu <[email protected]> Fixes: 7dafcfa79cc9 ("riscv: dts: starfive: enable DCDC1&ALDO4 node in axp15060") Signed-off-by: Conor Dooley <[email protected]>
2024-06-19riscv: dts: starfive: Update flash partition layoutMatthias Brugger1-5/+2
Up to now, the describe flash partition layout has some gaps. Use the whole flash chip by getting rid of the gaps. Suggested-by: Heinrich Schuchardt <[email protected]> Signed-off-by: Matthias Brugger <[email protected]> Reviewed-by: Emil Renner Berthing <[email protected]> Reviewed-by: Heinrich Schuchardt <[email protected]> Signed-off-by: Conor Dooley <[email protected]>
2024-06-19riscv: dts: starfive: add Star64 board devicetreeHenry Bell2-0/+62
The Pine64 Star64 is a development board based on the Starfive JH7110 SoC. The board features: - JH7110 SoC - 4/8 GiB LPDDR4 DRAM - AXP15060 PMIC - 40 pin GPIO header - 1x USB 3.0 host port - 3x USB 2.0 host port - 1x eMMC slot - 1x MicroSD slot - 1x QSPI Flash - 2x 1Gbps Ethernet port - 1x HDMI port - 1x 4-lane DSI - 1x 2-lane CSI - 1x PCIe 2.0 x1 lane Signed-off-by: Henry Bell <[email protected]> Signed-off-by: Conor Dooley <[email protected]>
2024-04-30riscv: dts: starfive: add Milkv Mars board device treeJisheng Zhang2-0/+31
The Milkv Mars is a development board based on the Starfive JH7110 SoC. The board features: - JH7110 SoC - 1/2/4/8 GiB LPDDR4 DRAM - AXP15060 PMIC - 40 pin GPIO header - 3x USB 3.0 host port - 1x USB 2.0 host port - 1x M.2 E-Key - 1x eMMC slot - 1x MicroSD slot - 1x QSPI Flash - 1x 1Gbps Ethernet port - 1x HDMI port - 1x 2-lane DSI and 1x 4-lane DSI - 1x 2-lane CSI Add the devicetree file describing the currently supported features, namely PMIC, UART, I2C, GPIO, SD card, QSPI Flash, eMMC and Ethernet. Signed-off-by: Jisheng Zhang <[email protected]> Reviewed-by: Emil Renner Berthing <[email protected]> Signed-off-by: Conor Dooley <[email protected]>
2024-04-30riscv: dts: starfive: introduce a common board dtsi for jh7110 based boardsJisheng Zhang2-584/+600
This is to prepare for Milkv Mars board dts support in the following patch. Let's factored out common part into .dtsi. Signed-off-by: Jisheng Zhang <[email protected]> Reviewed-by: Emil Renner Berthing <[email protected]> Signed-off-by: Conor Dooley <[email protected]>
2024-04-30riscv: dts: starfive: visionfive 2: add "disable-wp" for tfcardJisheng Zhang1-0/+1
No physical write-protect line is present, so setting "disable-wp". Signed-off-by: Jisheng Zhang <[email protected]> Reviewed-by: Emil Renner Berthing <[email protected]> Signed-off-by: Conor Dooley <[email protected]>
2024-04-30riscv: dts: starfive: visionfive 2: add tf cd-gpiosJisheng Zhang1-1/+1
Per VisionFive 2 1.2B, and 1.3A boards' SCH, GPIO 41 is used as card detect. So add "cd-gpios" property for this. Signed-off-by: Jisheng Zhang <[email protected]> Reviewed-by: Emil Renner Berthing <[email protected]> Signed-off-by: Conor Dooley <[email protected]>
2024-04-30riscv: dts: starfive: visionfive 2: use cpus label for timebase freqJisheng Zhang1-4/+4
As pointed out by Krzysztof "Board should not bring new CPU nodes. Override by label instead." Suggested-by: Krzysztof Kozlowski <[email protected]> Signed-off-by: Jisheng Zhang <[email protected]> Reviewed-by: Emil Renner Berthing <[email protected]> Signed-off-by: Conor Dooley <[email protected]>
2024-04-30riscv: dts: starfive: visionfive 2: update sound and codec dt node nameJisheng Zhang1-2/+2
Use "audio-codec" as the codec dt node name, and "sound" as the simple audio card dt name. Suggested-by: Krzysztof Kozlowski <[email protected]> Signed-off-by: Jisheng Zhang <[email protected]> Reviewed-by: Emil Renner Berthing <[email protected]> Signed-off-by: Conor Dooley <[email protected]>
2024-04-30riscv: dts: starfive: add 'cpus' label to jh7110 and jh7100 soc dtsiJisheng Zhang2-2/+2
Add the 'cpus' label so that we can reference it in board dts files. Signed-off-by: Jisheng Zhang <[email protected]> Reviewed-by: Emil Renner Berthing <[email protected]> Signed-off-by: Conor Dooley <[email protected]>
2024-04-15riscv: dts: starfive: visionfive 2: Remove non-existing I2S hardwareHannah Peuckmann1-58/+0
This partially reverts commit 92cfc35838b2 ("riscv: dts: starfive: Add the nodes and pins of I2Srx/I2Stx0/I2Stx1") This added device tree nodes for I2S hardware that is not actually on the VisionFive 2 board, but connected on the 40pin header. Many different extension boards could be added on those pins, so this should be handled by overlays instead. This also conflicts with the TDM node which also attempts to grab GPIO 44: starfive-jh7110-sys-pinctrl 13040000.pinctrl: pin GPIO44 already requested by 10090000.tdm; cannot claim for 120c0000.i2s Fixes: 92cfc35838b2 ("riscv: dts: starfive: Add the nodes and pins of I2Srx/I2Stx0/I2Stx1") Signed-off-by: Hannah Peuckmann <[email protected]> Reviewed-by: Emil Renner Berthing <[email protected]> Tested-by: Emil Renner Berthing <[email protected]> Signed-off-by: Conor Dooley <[email protected]>
2024-04-15riscv: dts: starfive: visionfive 2: Remove non-existing TDM hardwareHannah Peuckmann1-40/+0
This partially reverts commit e7c304c0346d ("riscv: dts: starfive: jh7110: add the node and pins configuration for tdm") This added device tree nodes for TDM hardware that is not actually on the VisionFive 2 board, but connected on the 40pin header. Many different extension boards could be added on those pins, so this should be handled by overlays instead. This also conflicts with the I2S node which also attempts to grab GPIO 44: starfive-jh7110-sys-pinctrl 13040000.pinctrl: pin GPIO44 already requested by 10090000.tdm; cannot claim for 120c0000.i2s Fixes: e7c304c0346d ("riscv: dts: starfive: jh7110: add the node and pins configuration for tdm") Signed-off-by: Hannah Peuckmann <[email protected]> Reviewed-by: Emil Renner Berthing <[email protected]> Tested-by: Emil Renner Berthing <[email protected]> Signed-off-by: Conor Dooley <[email protected]>
2024-03-26riscv: dts: starfive: Remove PMIC interrupt info for Visionfive 2 boardShengyu Qu1-1/+0
Interrupt line number of the AXP15060 PMIC is not a necessary part of its device tree. Originally the binding required one, so the dts patch added an invalid interrupt that the driver ignored (0) as the interrupt line of the PMIC is not actually connected on this platform. This went unnoticed during review as it would have been a valid interrupt for a GPIO controller, but it is not for the PLIC. The PLIC, on this platform at least, silently ignores the enablement of interrupt 0. Bo Gan is running a modified version of OpenSBI that faults if writes are done to reserved fields, so their kernel runs into problems. Delete the invalid interrupt from the device tree. Cc: [email protected] Reported-by: Bo Gan <[email protected]> Link: https://lore.kernel.org/all/[email protected]/ Signed-off-by: Shengyu Qu <[email protected]> Fixes: 2378341504de ("riscv: dts: starfive: Enable axp15060 pmic for cpufreq") [conor: rewrite the commit message to add more detail] Signed-off-by: Conor Dooley <[email protected]>
2024-03-19Merge tag 'soc-late-6.9' of ↵Linus Torvalds6-1/+332
git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc Pull more ARM SoC updates from Arnd Bergmann: "These are changes that for some reason ended up not making it into the first four branches but that should still make it into 6.9: - A rework of the omap clock support that touches both drivers and device tree files - The reset controller branch changes that had a dependency on late bugfixes. Merging them here avoids a backmerge of 6.8-rc5 into the drivers branch - The RISC-V/starfive, RISC-V/microchip and ARM/Broadcom devicetree changes that got delayed and needed some extra time in linux-next for wider testing" * tag 'soc-late-6.9' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (31 commits) soc: fsl: dpio: fix kcalloc() argument order bus: ts-nbus: Improve error reporting bus: ts-nbus: Convert to atomic pwm API riscv: dts: starfive: jh7110: Add camera subsystem nodes ARM: bcm: stop selecing CONFIG_TICK_ONESHOT ARM: dts: omap3: Update clksel clocks to use reg instead of ti,bit-shift ARM: dts: am3: Update clksel clocks to use reg instead of ti,bit-shift clk: ti: Improve clksel clock bit parsing for reg property clk: ti: Handle possible address in the node name dt-bindings: pwm: opencores: Add compatible for StarFive JH8100 dt-bindings: riscv: cpus: reg matches hart ID reset: Instantiate reset GPIO controller for shared reset-gpios reset: gpio: Add GPIO-based reset controller cpufreq: do not open-code of_phandle_args_equal() of: Add of_phandle_args_equal() helper reset: simple: add support for Sophgo SG2042 dt-bindings: reset: sophgo: support SG2042 riscv: dts: microchip: add specific compatible for mpfs pdma riscv: dts: microchip: add missing CAN bus clocks ARM: brcmstb: Add debug UART entry for 74165 ...
2024-03-06Merge tag 'riscv-dt-for-v6.9' of ↵Arnd Bergmann6-1/+332
https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux into soc/late RISC-V Devicetrees for v6.9 Microchip: Missing bus clocks for the CAN controllers spotted during the creation of a driver for the controllers and a specific compatible for the SiFive PDMA block on PolarFire SoC. Starfive: PWM nodes for the jh7100 and jh7110. Camera subsystem support for the latter. Most notably however is the addition of ethernet support for the jh7110 which finally allows people to use the network on the OG VisionFive and on the Beagle-V Starlight board. This was made possible by the non-standard cache management operations support added for the RZ/Five which could be extended to the ccache present on the jh7100. bindings: Additional clarification for what the reg property represents for cpus and two opencores PWM binding changes - the original addition and an added compatible. The latter is here as the driver patch was not ready but the PWM maintainer told me to go ahead and merge it. Signed-off-by: Conor Dooley <[email protected]> * tag 'riscv-dt-for-v6.9' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux: riscv: dts: starfive: jh7110: Add camera subsystem nodes dt-bindings: pwm: opencores: Add compatible for StarFive JH8100 dt-bindings: riscv: cpus: reg matches hart ID riscv: dts: microchip: add specific compatible for mpfs pdma riscv: dts: microchip: add missing CAN bus clocks riscv: dts: starfive: beaglev-starlight: Setup phy reset gpio riscv: dts: starfive: visionfive-v1: Setup ethernet phy riscv: dts: starfive: jh7100-common: Setup pinmux and enable gmac riscv: dts: starfive: jh7100: Add sysmain and gmac DT nodes riscv: dts: starfive: jh7110: Add PWM node and pins configuration riscv: dts: starfive: jh7100: Add PWM node and pins configuration dt-bindings: pwm: Add bindings for OpenCores PWM Controller Link: https://lore.kernel.org/r/20240305-iodine-moneywise-53797ae9bf6e@spud Signed-off-by: Arnd Bergmann <[email protected]>
2024-03-05riscv: dts: starfive: jh7100: fix root clock namesKrzysztof Kozlowski1-0/+4
JH7100 clock controller driver depends on certain root clock names. Reported-by: Geert Uytterhoeven <[email protected]> Closes: https://lore.kernel.org/all/CAMuHMdWw0dteXO2jw4cwGvzKcL6vmnb96C=qgPgUqNDMtF6X0Q@mail.gmail.com/ Fixes: f03606470886 ("riscv: dts: starfive: replace underscores in node names") Signed-off-by: Krzysztof Kozlowski <[email protected]> Tested-by: Geert Uytterhoeven <[email protected]> Signed-off-by: Conor Dooley <[email protected]>
2024-03-01riscv: dts: starfive: jh7110: Add camera subsystem nodesChanghuang Liang2-0/+116
Add camera subsystem nodes for the StarFive JH7110 SoC. They contain the dphy-rx, csi2rx, camss nodes. Signed-off-by: Changhuang Liang <[email protected]> Signed-off-by: Conor Dooley <[email protected]>
2024-02-13riscv: dts: starfive: replace underscores in node namesKrzysztof Kozlowski2-8/+8
Underscores should not be used in node names (dtc with W=2 warns about them), so replace them with hyphens. Signed-off-by: Krzysztof Kozlowski <[email protected]> Signed-off-by: Conor Dooley <[email protected]>
2024-01-31riscv: dts: starfive: beaglev-starlight: Setup phy reset gpioCristian Ciocaltea1-0/+11
The BeagleV Starlight SBC uses a Microchip KSZ9031RNXCA PHY supporting RGMII-ID which doesn't require any particular setup, other than defining a reset gpio, as opposed to VisionFive V1 for which the RX internal delay had to be adjusted. Co-developed-by: Emil Renner Berthing <[email protected]> Signed-off-by: Emil Renner Berthing <[email protected]> Signed-off-by: Cristian Ciocaltea <[email protected]> Reviewed-by: Jacob Keller <[email protected]> Reviewed-by: Emil Renner Berthing <[email protected]> Signed-off-by: Conor Dooley <[email protected]>
2024-01-31riscv: dts: starfive: visionfive-v1: Setup ethernet phyCristian Ciocaltea1-1/+21
The StarFive VisionFive V1 SBC uses a Motorcomm YT8521 PHY supporting RGMII-ID, but requires manual adjustment of the RX internal delay to work properly. The default RX delay provided by the driver is 1.95 ns, which proves to be too high. Applying a 50% reduction seems to mitigate the issue. Also note this adjustment is not necessary on BeagleV Starlight SBC, which uses a Microchip PHY. Hence, there is no indication of a misbehaviour on the GMAC side, but most likely the issue stems from the Motorcomm PHY. While at it, drop the redundant gpio include, which is already provided by jh7100-common.dtsi. Co-developed-by: Emil Renner Berthing <[email protected]> Signed-off-by: Emil Renner Berthing <[email protected]> Signed-off-by: Cristian Ciocaltea <[email protected]> Reviewed-by: Jacob Keller <[email protected]> Reviewed-by: Andrew Lunn <[email protected]> Reviewed-by: Emil Renner Berthing <[email protected]> Signed-off-by: Conor Dooley <[email protected]>
2024-01-31riscv: dts: starfive: jh7100-common: Setup pinmux and enable gmacCristian Ciocaltea1-0/+84
Add pinmux configuration for DWMAC found on the JH7100 based boards and enable the related DT node, providing a basic PHY configuration. Co-developed-by: Emil Renner Berthing <[email protected]> Signed-off-by: Emil Renner Berthing <[email protected]> Signed-off-by: Cristian Ciocaltea <[email protected]> Reviewed-by: Jacob Keller <[email protected]> Reviewed-by: Emil Renner Berthing <[email protected]> Signed-off-by: Conor Dooley <[email protected]>
2024-01-31riscv: dts: starfive: jh7100: Add sysmain and gmac DT nodesCristian Ciocaltea1-0/+36
Provide the sysmain and gmac DT nodes supporting the DWMAC found on the StarFive JH7100 SoC. Co-developed-by: Emil Renner Berthing <[email protected]> Signed-off-by: Emil Renner Berthing <[email protected]> Signed-off-by: Cristian Ciocaltea <[email protected]> Reviewed-by: Jacob Keller <[email protected]> Reviewed-by: Emil Renner Berthing <[email protected]> Signed-off-by: Conor Dooley <[email protected]>
2024-01-22riscv: dts: starfive: jh7110: Add PWM node and pins configurationWilliam Qiu2-0/+31
Add OpenCores PWM controller node and add PWM pins configuration on VisionFive 2 board. Signed-off-by: William Qiu <[email protected]> Reviewed-by: Emil Renner Berthing <[email protected]> Signed-off-by: Conor Dooley <[email protected]>
2024-01-22riscv: dts: starfive: jh7100: Add PWM node and pins configurationWilliam Qiu2-0/+33
Add OpenCores PWM controller node and add PWM pins configuration on VisionFive 1 board. Signed-off-by: William Qiu <[email protected]> Reviewed-by: Emil Renner Berthing <[email protected]> Signed-off-by: Conor Dooley <[email protected]>
2023-12-13riscv: dts: starfive: Enable SDIO wifi on JH7100 boardsEmil Renner Berthing1-0/+60
Add pinctrl and MMC controller nodes for the Broadcom wifi controller on the BeagleV Starlight and StarFive VisionFive V1 boards. Signed-off-by: Emil Renner Berthing <[email protected]> Signed-off-by: Conor Dooley <[email protected]>
2023-12-13riscv: dts: starfive: Enable SD-card on JH7100 boardsEmil Renner Berthing1-0/+47
Add pinctrl and MMC device tree nodes for the SD-card on the BeagleV Starlight and StarFive VisionFive V1 boards. Signed-off-by: Emil Renner Berthing <[email protected]> Signed-off-by: Conor Dooley <[email protected]>
2023-12-13riscv: dts: starfive: Add JH7100 MMC nodesEmil Renner Berthing1-0/+26
Add device tree nodes for the Synopsis MMC controllers on the StarFive JH7100 SoC. Signed-off-by: Emil Renner Berthing <[email protected]> Signed-off-by: Conor Dooley <[email protected]>
2023-12-13riscv: dts: starfive: Add pool for coherent DMA memory on JH7100 boardsEmil Renner Berthing1-0/+24
The StarFive JH7100 SoC has non-coherent device DMAs, but most drivers expect to be able to allocate coherent memory for DMA descriptors and such. However on the JH7100 DDR memory appears twice in the physical memory map, once cached and once uncached: 0x00_8000_0000 - 0x08_7fff_ffff : Off chip DDR memory, cached 0x10_0000_0000 - 0x17_ffff_ffff : Off chip DDR memory, uncached To use this uncached region we create a global DMA memory pool there and reserve the corresponding area in the cached region. However the uncached region is fully above the 32bit address limit, so add a dma-ranges map so the DMA address used for peripherals is still in the regular cached region below the limit. Link: https://github.com/starfive-tech/JH7100_Docs/blob/main/JH7100%20Data%20Sheet%20V01.01.04-EN%20(4-21-2021).pdf Signed-off-by: Emil Renner Berthing <[email protected]> Signed-off-by: Conor Dooley <[email protected]>
2023-12-13riscv: dts: starfive: Add JH7100 cache controllerEmil Renner Berthing1-0/+13
The StarFive JH7100 SoC also features the SiFive L2 cache controller, so add the device tree nodes for it. Signed-off-by: Emil Renner Berthing <[email protected]> Signed-off-by: Conor Dooley <[email protected]>
2023-12-13riscv: dts: starfive: Mark the JH7100 as having non-coherent DMAsEmil Renner Berthing1-0/+1
The StarFive JH7100 SoC has non-coherent device DMAs, so mark the soc bus as such. Link: https://github.com/starfive-tech/JH7100_Docs/blob/main/JH7100%20Cache%20Coherence%20V1.0.pdf Signed-off-by: Emil Renner Berthing <[email protected]> Signed-off-by: Conor Dooley <[email protected]>
2023-12-13riscv: dts: starfive: Group tuples in interrupt propertiesGeert Uytterhoeven1-4/+4
To improve human readability and enable automatic validation, the tuples in the various properties containing interrupt specifiers should be grouped. Fix this by grouping the tuples of "interrupts-extended" properties using angle brackets. Signed-off-by: Geert Uytterhoeven <[email protected]> Signed-off-by: Emil Renner Berthing <[email protected]> Signed-off-by: Conor Dooley <[email protected]>
2023-10-18Merge tag 'riscv-dt-for-v6.7' of ↵Arnd Bergmann4-2/+212
https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux into soc/dt RISC-V Devicetrees for v6.7 StarFive: Things are a bit slower for StarFive this window, there's only the addition of audio related DT nodes to speak of here. Generic: The SiFive, StarFive and Microchip devicetrees have had my replacement ISA extension detection properties added. Unfortunately, the old "riscv,isa" property never defined exactly what the extensions it contained meant, and people were want to fill it in incorrectly (and call upstream kernel devs idiots for not doing the same). The new properties have explicit definitions and hopefully will stand up better to some of the variation from RVI. Sophgo: Two new SoCs, one is probably the first of several with up/down tuned variants, that have a pair of T-Head c906 cores and appear aimed at the IP camera, smart <insert whatever> etc markets. They are intended to run in AMP mode, with an RTOS on the less powerful core. The other is far more interesting to kernel developers however, the 64-core SG2042, with more recent c920 cores from T-Head at 2 GHz. For both, support is at a very basic stage - some of the same developers are working on them as other T-Head powered SoCs, but hopefully things will move beyond a basic console boot. The goal is for Chen Wang to take over maintaining the Sophgo support once they have some more experience with the process. Signed-off-by: Conor Dooley <[email protected]> * tag 'riscv-dt-for-v6.7' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux: (22 commits) riscv: dts: starfive: convert isa detection to new properties riscv: dts: sifive: convert isa detection to new properties riscv: dts: microchip: convert isa detection to new properties riscv: dts: sophgo: add Milk-V Duo board device tree riscv: dts: sophgo: add initial CV1800B SoC device tree dt-bindings: riscv: Add Milk-V Duo board compatibles dt-bindings: timer: Add SOPHGO CV1800B clint dt-bindings: interrupt-controller: Add SOPHGO CV1800B plic riscv: defconfig: enable SOPHGO SoC riscv: dts: sophgo: add Milk-V Pioneer board device tree riscv: dts: add initial Sophgo SG2042 SoC device tree dt-bindings: interrupt-controller: Add Sophgo sg2042 CLINT mswi dt-bindings: timer: Add Sophgo sg2042 CLINT timer dt-bindings: interrupt-controller: Add Sophgo SG2042 PLIC dt-bindings: riscv: Add T-HEAD C920 compatibles dt-bindings: riscv: add sophgo sg2042 bindings dt-bindings: vendor-prefixes: add milkv/sophgo riscv: Add SOPHGO SOC family Kconfig support riscv: dts: starfive: add assigned-clock* to limit frquency riscv: dts: starfive: Add JH7110 PWM-DAC support ... Link: https://lore.kernel.org/r/20231016-filing-payroll-7aca51b8f1a3@spud Signed-off-by: Arnd Bergmann <[email protected]>
2023-10-15riscv: dts: starfive: convert isa detection to new propertiesConor Dooley2-0/+21
Convert the jh7100 and jh7110 devicetrees to use the new properties "riscv,isa-base" & "riscv,isa-extensions". For compatibility with other projects, "riscv,isa" remains. Signed-off-by: Conor Dooley <[email protected]>
2023-10-12riscv: dts: starfive: visionfive 2: correct spi's ss pinNam Cao1-1/+1
The ss pin of spi0 is the same as sck pin. According to the visionfive 2 documentation, it should be pin 49 instead of 48. Fixes: 74fb20c8f05d ("riscv: dts: starfive: Add spi node and pins configuration") Reviewed-by: Emil Renner Berthing <[email protected]> Signed-off-by: Nam Cao <[email protected]> Signed-off-by: Conor Dooley <[email protected]>
2023-09-30riscv: dts: starfive: add assigned-clock* to limit frquencyWilliam Qiu1-0/+4
In JH7110 SoC, we need to go by-pass mode, so we need add the assigned-clock* properties to limit clock frquency. Signed-off-by: William Qiu <[email protected]> Reviewed-by: Emil Renner Berthing <[email protected]> Signed-off-by: Conor Dooley <[email protected]>
2023-09-13riscv: dts: starfive: Add JH7110 PWM-DAC supportHal Feng2-0/+62
Add PWM-DAC support for StarFive JH7110 SoC. Reviewed-by: Walker Chen <[email protected]> Signed-off-by: Hal Feng <[email protected]> Signed-off-by: Conor Dooley <[email protected]>
2023-09-13riscv: dts: starfive: Add the nodes and pins of I2Srx/I2Stx0/I2Stx1Xingyu Wu2-0/+123
Add I2Srx/I2Stx0/I2Stx1 nodes and pins configuration for the StarFive JH7110 SoC. Signed-off-by: Xingyu Wu <[email protected]> Reviewed-by: Walker Chen <[email protected]> Signed-off-by: Conor Dooley <[email protected]>
2023-09-13riscv: dts: starfive: pinfunc: Fix the pins name of I2STX1Xingyu Wu1-2/+2
These pins are actually I2STX1 clock input, not I2STX0, so their names should be changed. Signed-off-by: Xingyu Wu <[email protected]> Reviewed-by: Walker Chen <[email protected]> Acked-by: Rob Herring <[email protected]> Signed-off-by: Conor Dooley <[email protected]>
2023-09-13riscv: dts: starfive: visionfive 2: Fix uart0 pins sort orderHal Feng1-24/+24
Node uart0_pins should be sorted alphabetically. Signed-off-by: Hal Feng <[email protected]> Signed-off-by: Conor Dooley <[email protected]>
2023-09-13riscv: dts: starfive: visionfive 2: Enable usb0Hal Feng1-0/+1
usb0 was disabled by mistake when merging, so enable it. Fixes: e7c304c0346d ("riscv: dts: starfive: jh7110: add the node and pins configuration for tdm") Signed-off-by: Hal Feng <[email protected]> Signed-off-by: Conor Dooley <[email protected]>
2023-09-12riscv: dts: starfive: fix NOR flash reserved-data partition sizeAurelien Jarno1-1/+1
The Starfive VisionFive 2 has a 16MiB NOR flash, while the reserved-data partition is declared starting at address 0x600000 with a size of 0x1000000. This causes the kernel to output the following warning: [ 22.156589] mtd: partition "reserved-data" extends beyond the end of device "13010000.spi.0" -- size truncated to 0xa00000 It seems to be a confusion between the size of the partition and the end address. Fix that by specifying the right size. Fixes: 8384087a4223 ("riscv: dts: starfive: Add QSPI controller node for StarFive JH7110 SoC") Signed-off-by: Aurelien Jarno <[email protected]> Reviewed-by: Emil Renner Berthing <[email protected]> Signed-off-by: Conor Dooley <[email protected]>
2023-08-15riscv: dts: starfive: fix jh7110 qspi sort orderConor Dooley1-19/+19
Emil pointed out that "13010000 sorts after 12070000". Reshuffle the entries to be in-order. Reported-by: Emil Renner Berthing <[email protected]> Reviewed-by: Emil Renner Berthing <[email protected]> Signed-off-by: Conor Dooley <[email protected]>
2023-08-13riscv: dts: starfive: jh7110: Fix GMAC configurationSamin Guo1-4/+4
Fixed configuration to improve the speed of TCP RX. Before: # iperf3 -s ----------------------------------------------------------- Server listening on 5201 (test #1) ----------------------------------------------------------- Accepted connection from 192.168.1.4, port 47604 [ 5] local 192.168.1.3 port 5201 connected to 192.168.1.4 port 47612 [ ID] Interval Transfer Bitrate [ 5] 0.00-1.00 sec 36.3 MBytes 305 Mbits/sec [ 5] 1.00-2.00 sec 35.6 MBytes 299 Mbits/sec [ 5] 2.00-3.00 sec 36.5 MBytes 306 Mbits/sec [ 5] 3.00-4.00 sec 36.5 MBytes 306 Mbits/sec [ 5] 4.00-5.00 sec 35.7 MBytes 300 Mbits/sec [ 5] 5.00-6.00 sec 35.4 MBytes 297 Mbits/sec [ 5] 6.00-7.00 sec 37.1 MBytes 311 Mbits/sec [ 5] 7.00-8.00 sec 35.6 MBytes 298 Mbits/sec [ 5] 8.00-9.00 sec 36.4 MBytes 305 Mbits/sec [ 5] 9.00-10.00 sec 36.3 MBytes 304 Mbits/sec - - - - - - - - - - - - - - - - - - - - - - - - - [ ID] Interval Transfer Bitrate [ 5] 0.00-10.00 sec 361 MBytes 303 Mbits/sec receiver After: # iperf3 -s ----------------------------------------------------------- Server listening on 5201 (test #1) ----------------------------------------------------------- Accepted connection from 192.168.1.4, port 47710 [ 5] local 192.168.1.3 port 5201 connected to 192.168.1.4 port 47720 [ ID] Interval Transfer Bitrate [ 5] 0.00-1.00 sec 111 MBytes 932 Mbits/sec [ 5] 1.00-2.00 sec 111 MBytes 934 Mbits/sec [ 5] 2.00-3.00 sec 111 MBytes 934 Mbits/sec [ 5] 3.00-4.00 sec 111 MBytes 934 Mbits/sec [ 5] 4.00-5.00 sec 111 MBytes 934 Mbits/sec [ 5] 5.00-6.00 sec 111 MBytes 935 Mbits/sec [ 5] 6.00-7.00 sec 111 MBytes 934 Mbits/sec [ 5] 7.00-8.00 sec 111 MBytes 935 Mbits/sec [ 5] 8.00-9.00 sec 111 MBytes 934 Mbits/sec [ 5] 9.00-10.00 sec 111 MBytes 934 Mbits/sec [ 5] 10.00-10.00 sec 167 KBytes 933 Mbits/sec - - - - - - - - - - - - - - - - - - - - - - - - - [ ID] Interval Transfer Bitrate [ 5] 0.00-10.00 sec 1.09 GBytes 934 Mbits/sec receiver Reviewed-by: Hal Feng <[email protected]> Signed-off-by: Samin Guo <[email protected]> Fixes: 1ff166c97972 ("riscv: dts: starfive: jh7110: Add ethernet device nodes") Reviewed-by: Emil Renner Berthing <[email protected]> [conor: converted to decimal per emil's request] Signed-off-by: Conor Dooley <[email protected]>
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