| Age | Commit message (Expand) | Author | Files | Lines |
|---|
| 2018-01-18 | MIPS: JZ4770: Work around config2 misreporting associativity | Maarten ter Huurne | 1 | -0/+9 |
| 2017-11-02 | License cleanup: add SPDX GPL-2.0 license identifier to files with no license | Greg Kroah-Hartman | 1 | -0/+1 |
| 2017-08-30 | MIPS: CPS: Have asm/mips-cps.h include CM & CPC headers | Paul Burton | 1 | -1/+1 |
| 2017-08-30 | MIPS: CPS: Use change_*, set_* & clear_* where appropriate | Paul Burton | 1 | -14/+5 |
| 2017-08-29 | MIPS: CM: Use BIT/GENMASK for register fields, order & drop shifts | Paul Burton | 1 | -18/+18 |
| 2017-01-03 | MIPS: sc-mips: L2 cache is inclusive of L1 dcache for CM3 | Paul Burton | 1 | -0/+1 |
| 2016-05-13 | MIPS: Add P6600 cases to CPU switch statements | Paul Burton | 1 | -0/+1 |
| 2016-02-29 | MIPS: scache: Fix scache init with invalid line size. | Govindraj Raja | 1 | -4/+9 |
| 2016-02-09 | MIPS: Fix early CM probing | Paul Burton | 1 | -10/+0 |
| 2015-10-26 | MIPS: Enable L2 prefetching for CM >= 2.5 | Paul Burton | 1 | -1/+60 |
| 2015-10-26 | MIPS: Remove invalid check | Andrzej Hajda | 1 | -2/+2 |
| 2015-08-26 | MIPS: Add platform callback before initializing the L2 cache | Markos Chandras | 1 | -0/+10 |
| 2015-08-26 | MIPS: CM3: Add support for CM3 L2 cache. | Paul Burton | 1 | -0/+32 |
| 2015-02-17 | MIPS: mm: scache: Add secondary cache support for MIPS R6 cores | Markos Chandras | 1 | -1/+2 |
| 2015-02-16 | MIPS: Add cases for CPU_QEMU_GENERIC | Leonid Yegoshin | 1 | -0/+1 |
| 2014-03-26 | MIPS: Add cases for CPU_P5600 | James Hogan | 1 | -0/+1 |
| 2014-03-06 | MIPS: Add 1074K CPU support explicitly. | Steven J. Hill | 1 | -0/+1 |
| 2014-01-22 | MIPS: Add support for interAptiv cores | Leonid Yegoshin | 1 | -0/+1 |
| 2014-01-22 | MIPS: Add support for the proAptiv cores | Leonid Yegoshin | 1 | -0/+1 |
| 2013-09-17 | MIPS: Optimize current_cpu_type() for better code. | Ralf Baechle | 1 | -1/+2 |
| 2013-07-14 | MIPS: Delete __cpuinit/__CPUINIT usage from MIPS code | Paul Gortmaker | 1 | -1/+1 |
| 2013-04-05 | MIPS: Fix ISA level which causes secondary cache init bypassing and more | Deng-Cheng Zhu | 1 | -4/+2 |
| 2012-03-28 | Disintegrate asm/system.h for MIPS | David Howells | 1 | -1/+0 |
| 2010-12-17 | MIPS: Fix build errors in sc-mips.c | Kevin Cernekee | 1 | -0/+4 |
| 2010-10-29 | MIPS: Honor L2 bypass bit | Kevin Cernekee | 1 | -4/+30 |
| 2009-09-30 | MIPS: MIPSxx SC: Avoid destructive invalidation on partial L2 cachelines. | Kevin Cernekee | 1 | -0/+5 |
| 2008-03-12 | [MIPS] Fix loads of section missmatches | Ralf Baechle | 1 | -2/+1 |
| 2007-10-11 | [MIPS] Fix "no space between function name and open parenthesis" warnings. | Ralf Baechle | 1 | -1/+1 |
| 2006-06-29 | [MIPS] MIPS32/MIPS64 S-cache fix and cleanup | Atsushi Nemoto | 1 | -32/+3 |
| 2006-06-29 | [MIPS] MIPS32/MIPS64 secondary cache management | Chris Dearman | 1 | -0/+141 |