| Age | Commit message (Expand) | Author | Files | Lines |
|---|
| 2023-12-10 | mips: move cache declarations into header | Arnd Bergmann | 1 | -0/+4 |
| 2022-01-27 | MIPS: Fix build error due to PTR used in more places | Thomas Bogendoerfer | 1 | -2/+2 |
| 2021-02-13 | MIPS: Simplify EVA cache handling | Thomas Bogendoerfer | 1 | -56/+11 |
| 2019-10-31 | MIPS: Loongson64: Rename CPU TYPES | Jiaxun Yang | 1 | -2/+2 |
| 2019-10-09 | MIPS: Provide unroll() macro, use it for cache ops | Paul Burton | 1 | -339/+19 |
| 2018-11-20 | MIPS: c-r4k: Add r4k_blast_scache_node for Loongson-3 | Huacai Chen | 1 | -0/+22 |
| 2018-09-26 | MIPS: MT: Remove obsolete cache flush repeat code | Paul Burton | 1 | -73/+0 |
| 2017-03-28 | new helper: uaccess_kernel() | Al Viro | 1 | -2/+2 |
| 2017-02-13 | MIPS: Fix protected_cache(e)_op() for microMIPS | Paul Burton | 1 | -2/+4 |
| 2017-02-03 | MIPS: Add return errors to protected cache ops | James Hogan | 1 | -20/+35 |
| 2016-12-24 | Replace <asm/uaccess.h> with <linux/uaccess.h> globally | Linus Torvalds | 1 | -1/+1 |
| 2016-07-29 | MIPS: c-r4k: Fix protected_writeback_scache_line for EVA | James Hogan | 1 | -0/+4 |
| 2015-04-10 | MIPS: r4kcache: Use correct base register for MIPS R6 cache flushes | Markos Chandras | 1 | -44/+45 |
| 2015-02-17 | MIPS: asm: r4kcache: Add MIPS R6 cache unroll functions | Markos Chandras | 1 | -2/+148 |
| 2014-12-11 | Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus | Linus Torvalds | 1 | -59/+0 |
| 2014-11-24 | MIPS: Remove a temporary hack for debugging cache flushes in SMTC configuration | Ralf Baechle | 1 | -59/+0 |
| 2014-11-24 | MIPS: r4kcache: Add EVA case for protected_writeback_dcache_line | Markos Chandras | 1 | -0/+4 |
| 2014-06-30 | MIPS: KVM: Reformat code and comments | Deng-Cheng Zhu | 1 | -0/+3 |
| 2014-05-30 | MIPS: Add minimal support for OCTEON3 to c-r4k.c | David Daney | 1 | -0/+2 |
| 2014-05-24 | MIPS: MT: Remove SMTC support | Ralf Baechle | 1 | -3/+2 |
| 2014-03-31 | MIPS: Fix gigaton of warning building with microMIPS. | Ralf Baechle | 1 | -2/+2 |
| 2014-03-26 | MIPS: asm: r4kcache: Add EVA cache flushing functions | Leonid Yegoshin | 1 | -1/+151 |
| 2014-03-26 | MIPS: asm: r4kcache: Add protected cache operation for EVA | Leonid Yegoshin | 1 | -0/+18 |
| 2014-03-26 | MIPS: asm: r4kcache: Build flushing code for instruction cache | Leonid Yegoshin | 1 | -0/+1 |
| 2014-01-15 | MIPS: fix blast_icache32 on loongson2 | Aaro Koskinen | 1 | -21/+22 |
| 2014-01-15 | MIPS: fix case mismatch in local_r4k_flush_icache_range() | Huacai Chen | 1 | -4/+4 |
| 2013-10-29 | MIPS: Loongson: Get rid of Loongson 2 #ifdefery all over arch/mips. | Ralf Baechle | 1 | -11/+30 |
| 2013-02-01 | MIPS: Whitespace cleanup. | Ralf Baechle | 1 | -6/+6 |
| 2011-04-06 | update David Miller's old email address | Justin P. Mattock | 1 | -1/+1 |
| 2009-06-17 | MIPS: Support 64-byte D-cache line size | Kevin Cernekee | 1 | -0/+1 |
| 2008-10-11 | MIPS: Move headfiles to new location below arch/mips/include | Ralf Baechle | 1 | -0/+443 |