aboutsummaryrefslogtreecommitdiff
path: root/arch/mips/include/asm/octeon/cvmx-l2c-defs.h
AgeCommit message (Collapse)AuthorFilesLines
2017-08-07MIPS: Octeon: Fix broken EDAC driver.Steven J. Hill1-1/+36
Commit "MIPS: Octeon: Remove unused L2C types and macros." broke the the EDAC driver. Bring back 'cvmx-l2d-defs.h' file and the missing types for L2C. Fixes: 15f6847923a8 ("MIPS: Octeon: Remove unused L2C types and macros.") Fixes: 15f6847923a8 ("MIPS: Octeon: Remove unused L2C types and macros.") Signed-off-by: Steven J. Hill <[email protected]> Reviewed-by: James Hogan <[email protected]> Cc: [email protected] Cc: <[email protected]> # 4.12+ Patchwork: https://patchwork.linux-mips.org/patch/16906/ Signed-off-by: Ralf Baechle <[email protected]>
2017-04-10MIPS: Octeon: Remove unused L2C types and macros.Steven J. Hill1-3078/+115
Remove all unused bitfields and macros. Convert the remaining bitfields to use __BITFIELD_FIELD instead of #ifdef. [[email protected]: Add inclusions of <uapi/asm/bitfield.h> as necessary.] Signed-off-by: Steven J. Hill <[email protected]> Acked-by: David Daney <[email protected]> Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/15403/ Signed-off-by: Ralf Baechle <[email protected]>
2012-08-31MIPS: OCTEON: Update register definitions.David Daney1-59/+1657
Add support for cn68xx, cn61xx, cn63xx, cn66xx and cnf71XX. Add little-endian register layouts. Patch cvmx-interrupt-rsl.c for changed definition. Signed-off-by: David Daney <[email protected]>
2010-10-29MIPS: Octeon: Update register definitions for CN63XX chipsDavid Daney1-66/+672
The CN63XX is a new 6-CPU SOC based on the new OCTEON II CPU cores. Join some lines back together. This makes some of them exceed 80 columns, but they are uninteresting and this unclutters things. Signed-off-by: David Daney <[email protected]> Patchwork: http://patchwork.linux-mips.org/patch/1668/ Signed-off-by: Ralf Baechle <[email protected]>
2009-01-11MIPS: Add Cavium OCTEON processor CSR definitionsDavid Daney1-0/+963
Here we define the addresses and bit-fields of the Configuration and Status Registers (CSRs) for some of the hardware functional units on the OCTEON SOC. Definitions are needed for: CIU -- Central Interrupt Unit. GPIO -- General Purpose Input Output. IOB -- Input / Output {Busing,Bridge}. IPD -- Input Packet Data unit. L2C -- Level-2 Cache controller. L2D -- Level-2 Data cache. L2T -- Level-2 cache Tag. LED -- Light Emitting Diode controller. MIO -- Miscellaneous Input / Output. POW -- Packet Order / Work unit. Signed-off-by: Tomaso Paoletti <[email protected]> Signed-off-by: David Daney <[email protected]> Signed-off-by: Ralf Baechle <[email protected]>