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2020-09-07MIPS: Remove mach-*/war.hThomas Bogendoerfer1-11/+0
After conversion of all WAR defines we can now remove all mach-*/war.h files. Signed-off-by: Thomas Bogendoerfer <[email protected]>
2020-09-07MIPS: Get rid of BCM1250_M3_WARThomas Bogendoerfer1-2/+0
BCM1250_M3_WAR is depending on CONFIG_CONFIG_SB1_PASS_2_WORKAROUNDS. So using this option directly lets and remove define. Signed-off-by: Thomas Bogendoerfer <[email protected]>
2020-09-07MIPS: Replace SIBYTE_1956_WAR by CONFIG_SB1_PASS_2_WORKAROUNDSThomas Bogendoerfer1-1/+0
SB1250 uart bug is related to PASS 2 workarounds. Use config CONFIG_SB1_PASS_2_WORKAROUNDS directly and get rid of SIBYTE_1956_WAR. Signed-off-by: Thomas Bogendoerfer <[email protected]>
2020-09-07MIPS: Convert MIPS34K_MISSED_ITLB_WAR into a config optionThomas Bogendoerfer1-1/+0
Use a new config option to enable MIPS 34K ITLB workaround and remove define from different war.h files. Signed-off-by: Thomas Bogendoerfer <[email protected]>
2020-09-07MIPS: Convert R10000_LLSC_WAR info a config optionThomas Bogendoerfer1-1/+0
Use a new config option to enabel R1000_LLSC workaound and remove define from different war.h files. Signed-off-by: Thomas Bogendoerfer <[email protected]>
2020-09-07MIPS: Convert ICACHE_REFILLS_WORKAROUND_WAR into a config optionThomas Bogendoerfer1-1/+0
Use a new config option to enable I-cache refill workaround and remove define from different war.h files. Signed-off-by: Thomas Bogendoerfer <[email protected]>
2020-09-07MIPS: Convert TX49XX_ICACHE_INDEX_INV into a config optionThomas Bogendoerfer1-1/+0
Use a new config option to enable TX49XX I-cache index invalidate workaround and remove define from different war.h files. Signed-off-by: Thomas Bogendoerfer <[email protected]>
2020-09-07MIPS: Remove MIPS4K_ICACHE_REFILL_WAR and MIPS_CACHE_SYNC_WARThomas Bogendoerfer1-2/+0
Neither MIPS4K_ICACHE_REFILL_WAR nor MIPS_CACHE_SYNC_WAR are implemented, so removing defines for it won't change anything. Signed-off-by: Thomas Bogendoerfer <[email protected]>
2020-09-07MIPS: Convert R4600_V2_HIT_CACHEOP into a config optionThomas Bogendoerfer1-5/+0
Use a new config option to enable R4600 V2 cacheop hit workaround and remove define from different war.h files. Signed-off-by: Thomas Bogendoerfer <[email protected]>
2020-09-07MIPS: Convert R4600_V1_HIT_CACHEOP into a config optionThomas Bogendoerfer1-1/+0
Use a new config option to enable R4600 V1 cacheop hit workaround and remove define from the different war.h files. Signed-off-by: Thomas Bogendoerfer <[email protected]>
2020-09-07MIPS: Convert R4600_V1_INDEX_ICACHEOP into a config optionThomas Bogendoerfer1-1/+0
Use a new config option to enable R4600 V1 index I-cacheop workaround and remove define from different war.h files. Signed-off-by: Thomas Bogendoerfer <[email protected]>
2020-03-19MIPS: Add header files reference with path prefixbibo mao1-1/+1
There are some common header files which are referenced locally with #includenext method, includenext is tricky method and only used on mips platform. This patech removes includenext method, replace it with defailed pathname prefix for header files. This patch passes to compile on all mips platform with defconfig, and is verified on my loongson64 box. Changes: -------- v2: - Fix compiling issue on malta platform Reported-by: kbuild test robot <[email protected]> Signed-off-by: bibo mao <[email protected]> Signed-off-by: Thomas Bogendoerfer <[email protected]>
2019-07-23MIPS: Remove unused R5432_CP0_INTERRUPT_WARPaul Burton1-1/+0
R5432_CP0_INTERRUPT_WAR is defined as 0 for every system we support, and so the workaround is never used. Remove the dead code. Signed-off-by: Paul Burton <[email protected]> Cc: [email protected]
2017-07-11MIPS16e2: Provide feature overrides for non-MIPS16 systemsMaciej W. Rozycki1-0/+1
Hardcode the absence of the MIPS16e2 ASE for all the systems that do so for the MIPS16 ASE already, providing for code to be optimized away. Signed-off-by: Maciej W. Rozycki <[email protected]> Reviewed-by: James Hogan <[email protected]> Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/16097/ Signed-off-by: Ralf Baechle <[email protected]>
2017-04-12MIPS: mach-rm: Remove recursive include of cpu-feature-overrides.hMarcin Nowakowski1-2/+0
cpu-feautre-overrides.h in mach-rm unnecessarily includes itself, so drop the pointless include Signed-off-by: Marcin Nowakowski <[email protected]> Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/15462/ Signed-off-by: Ralf Baechle <[email protected]>
2015-04-08MIPS: Correct `nofpu' non-functionalityMaciej W. Rozycki1-1/+0
The `cpu_has_fpu' feature flag must not be hardcoded to 1 or the `nofpu' kernel option will be ignored. Remove any such overrides and add a cautionary note. Hardcoding to 0 is fine for FPU-less platforms. Signed-off-by: Maciej W. Rozycki <[email protected]> Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/9694/ Signed-off-by: Ralf Baechle <[email protected]>
2012-12-13MIPS: PMC-Sierra Yosemite: Remove support.Ralf Baechle1-1/+0
Nobody seems to be interested anymore and upstream also never had an ethernet driver. Signed-off-by: Ralf Baechle <[email protected]>
2012-10-11MIPS: Hardwire detection of DSP ASE Rev 2 for systems, as required.Ralf Baechle1-0/+1
Most supported systems currently hardwire cpu_has_dsp to 0, so we also can disable support for cpu_has_dsp2 resulting in a slightly smaller kernel. Signed-off-by: Ralf Baechle <[email protected]>
2008-10-11MIPS: Move headfiles to new location below arch/mips/includeRalf Baechle3-0/+93
Signed-off-by: Ralf Baechle <[email protected]>
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