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2020-10-08MIPS: SGI-IP28: disable use of ll/sc in kernelThomas Bogendoerfer1-1/+1
SGI-IP28 systems only use broken R10k rev 2.5 CPUs, which could lock up, if ll/sc sequences are issued in certain order. Since those systems are all non-SMP, we can disable ll/sc usage in kernel. Signed-off-by: Thomas Bogendoerfer <[email protected]>
2020-09-07MIPS: Remove mach-*/war.hThomas Bogendoerfer1-11/+0
After conversion of all WAR defines we can now remove all mach-*/war.h files. Signed-off-by: Thomas Bogendoerfer <[email protected]>
2020-09-07MIPS: Get rid of BCM1250_M3_WARThomas Bogendoerfer1-2/+0
BCM1250_M3_WAR is depending on CONFIG_CONFIG_SB1_PASS_2_WORKAROUNDS. So using this option directly lets and remove define. Signed-off-by: Thomas Bogendoerfer <[email protected]>
2020-09-07MIPS: Replace SIBYTE_1956_WAR by CONFIG_SB1_PASS_2_WORKAROUNDSThomas Bogendoerfer1-1/+0
SB1250 uart bug is related to PASS 2 workarounds. Use config CONFIG_SB1_PASS_2_WORKAROUNDS directly and get rid of SIBYTE_1956_WAR. Signed-off-by: Thomas Bogendoerfer <[email protected]>
2020-09-07MIPS: Convert MIPS34K_MISSED_ITLB_WAR into a config optionThomas Bogendoerfer1-1/+0
Use a new config option to enable MIPS 34K ITLB workaround and remove define from different war.h files. Signed-off-by: Thomas Bogendoerfer <[email protected]>
2020-09-07MIPS: Convert R10000_LLSC_WAR info a config optionThomas Bogendoerfer1-1/+0
Use a new config option to enabel R1000_LLSC workaound and remove define from different war.h files. Signed-off-by: Thomas Bogendoerfer <[email protected]>
2020-09-07MIPS: Convert ICACHE_REFILLS_WORKAROUND_WAR into a config optionThomas Bogendoerfer1-1/+0
Use a new config option to enable I-cache refill workaround and remove define from different war.h files. Signed-off-by: Thomas Bogendoerfer <[email protected]>
2020-09-07MIPS: Convert TX49XX_ICACHE_INDEX_INV into a config optionThomas Bogendoerfer1-1/+0
Use a new config option to enable TX49XX I-cache index invalidate workaround and remove define from different war.h files. Signed-off-by: Thomas Bogendoerfer <[email protected]>
2020-09-07MIPS: Remove MIPS4K_ICACHE_REFILL_WAR and MIPS_CACHE_SYNC_WARThomas Bogendoerfer1-2/+0
Neither MIPS4K_ICACHE_REFILL_WAR nor MIPS_CACHE_SYNC_WAR are implemented, so removing defines for it won't change anything. Signed-off-by: Thomas Bogendoerfer <[email protected]>
2020-09-07MIPS: Convert R4600_V2_HIT_CACHEOP into a config optionThomas Bogendoerfer1-1/+0
Use a new config option to enable R4600 V2 cacheop hit workaround and remove define from different war.h files. Signed-off-by: Thomas Bogendoerfer <[email protected]>
2020-09-07MIPS: Convert R4600_V1_HIT_CACHEOP into a config optionThomas Bogendoerfer1-1/+0
Use a new config option to enable R4600 V1 cacheop hit workaround and remove define from the different war.h files. Signed-off-by: Thomas Bogendoerfer <[email protected]>
2020-09-07MIPS: Convert R4600_V1_INDEX_ICACHEOP into a config optionThomas Bogendoerfer1-1/+0
Use a new config option to enable R4600 V1 index I-cacheop workaround and remove define from different war.h files. Signed-off-by: Thomas Bogendoerfer <[email protected]>
2019-07-23MIPS: Remove unused R5432_CP0_INTERRUPT_WARPaul Burton1-1/+0
R5432_CP0_INTERRUPT_WAR is defined as 0 for every system we support, and so the workaround is never used. Remove the dead code. Signed-off-by: Paul Burton <[email protected]> Cc: [email protected]
2017-07-11MIPS16e2: Provide feature overrides for non-MIPS16 systemsMaciej W. Rozycki1-0/+1
Hardcode the absence of the MIPS16e2 ASE for all the systems that do so for the MIPS16 ASE already, providing for code to be optimized away. Signed-off-by: Maciej W. Rozycki <[email protected]> Reviewed-by: James Hogan <[email protected]> Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/16097/ Signed-off-by: Ralf Baechle <[email protected]>
2014-08-26MIPS: IP28: Fix/clean spaces.hThomas Bogendoerfer1-7/+0
Broken values for UNCAC_BASE/IO_BASE caused complete breakage of IP28 builds. Only set special PHY_OFFSET and take everything else from generic spaces.h Signed-off-by: Thomas Bogendoerfer <[email protected]> Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/7549/ Signed-off-by: Ralf Baechle <[email protected]> (cherry picked from commit 81832d7e7962a40d08d9fe2e7e71b7887bc30097)
2013-09-17MIPS: Optimize current_cpu_type() for better code.Ralf Baechle1-0/+2
o Move current_cpu_type() to a separate header file o #ifdefing on supported CPU types lets modern GCC know that certain code in callers may be discarded ideally turning current_cpu_type() into a function returning a constant. o Use current_cpu_type() rather than direct access to struct cpuinfo_mips. Signed-off-by: Ralf Baechle <[email protected]> Cc: Steven J. Hill <[email protected]> Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/5833/
2013-07-01Revert "MIPS: make CAC_ADDR and UNCAC_ADDR account for PHYS_OFFSET"Leonid Yegoshin1-3/+6
This reverts commit 3f4579252aa166641861a64f1c2883365ca126c2. It is invalid because the macros CAC_ADDR and UNCAC_ADDR have a kernel virtual address as an argument and also returns a kernel virtual address. Using and physical address PHYS_OFFSET is blatantly wrong for a macro common to multiple platforms. Signed-off-by: Leonid Yegoshin <[email protected]> Acked-by: Steven J. Hill <[email protected]> Cc: [email protected] Cc: Florian Fainelli <[email protected]> Patchwork: https://patchwork.linux-mips.org/patch/5528/ Signed-off-by: Ralf Baechle <[email protected]>
2013-02-01MIPS: Whitespace cleanup.Ralf Baechle2-2/+2
Having received another series of whitespace patches I decided to do this once and for all rather than dealing with this kind of patches trickling in forever. Signed-off-by: Ralf Baechle <[email protected]>
2012-12-13MIPS: PMC-Sierra Yosemite: Remove support.Ralf Baechle1-1/+0
Nobody seems to be interested anymore and upstream also never had an ethernet driver. Signed-off-by: Ralf Baechle <[email protected]>
2012-10-11MIPS: Hardwire detection of DSP ASE Rev 2 for systems, as required.Ralf Baechle1-0/+1
Most supported systems currently hardwire cpu_has_dsp to 0, so we also can disable support for cpu_has_dsp2 resulting in a slightly smaller kernel. Signed-off-by: Ralf Baechle <[email protected]>
2008-10-15MIPS: IP22/28: Switch over to RTC class driverThomas Bogendoerfer1-4/+0
This patchset removes some dead code and creates a platform device for the RTC class driver. Signed-off-by: Thomas Bogendoerfer <[email protected]> Signed-off-by: Ralf Baechle <[email protected]>
2008-10-11MIPS: Move headfiles to new location below arch/mips/includeRalf Baechle4-0/+101
Signed-off-by: Ralf Baechle <[email protected]>
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