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2024-07-05arm64: dts: st: describe power supplies for stm32mp257f-ev1 boardPascal Paillet1-9/+34
Describe power supplies for stm32mp257f-ev1 board. Signed-off-by: Pascal Paillet <[email protected]> Signed-off-by: Alexandre Torgue <[email protected]>
2024-07-05arm64: dts: st: add scmi regulators on stm32mp25Pascal Paillet1-0/+35
Add SCMI regulators description on STM32MP25. Signed-off-by: Pascal Paillet <[email protected]> Signed-off-by: Alexandre Torgue <[email protected]>
2024-07-05arm64: dts: st: enable Ethernet2 on stm32mp257f-ev1 boardChristophe Roullier1-0/+24
ETHERNET2 instance is connected to Realtek PHY in RGMII mode Ethernet is SNSP IP with GMAC5 version. Signed-off-by: Christophe Roullier <[email protected]> Reviewed-by: Marek Vasut <[email protected]> Signed-off-by: Alexandre Torgue <[email protected]>
2024-07-05arm64: dts: st: add eth2 pinctrl entries in stm32mp25-pinctrl.dtsiChristophe Roullier1-0/+59
Add pinctrl entry related to ETH2 in stm32mp25-pinctrl.dtsi ethernet2: RGMII with crystal. Signed-off-by: Christophe Roullier <[email protected]> Reviewed-by: Marek Vasut <[email protected]> Signed-off-by: Alexandre Torgue <[email protected]>
2024-07-05arm64: dts: st: add ethernet1 and ethernet2 support on stm32mp25Christophe Roullier2-0/+100
Both instances ethernet based on GMAC SNPS IP on stm32mp25. GMAC IP version is SNPS 5.3 Signed-off-by: Christophe Roullier <[email protected]> Reviewed-by: Marek Vasut <[email protected]> Signed-off-by: Alexandre Torgue <[email protected]>
2024-07-05arm64: dts: st: add HPDMA nodes on stm32mp251Amelie Delaunay1-0/+69
The High Performance Direct Memory Access (HPDMA) controller is used to perform programmable data transfers between memory-mapped peripherals and memories (or between memories) via linked-lists. There are 3 instances of HPDMA on stm32mp251, using stm32-dma3 driver, with 16 channels per instance and with one interrupt per channel. Channels 0 to 7 are implemented with a FIFO of 8 bytes. Channels 8 to 11 are implemented with a FIFO of 32 bytes. Channels 12 to 15 are implemented with a FIFO of 128 bytes. Thanks to stm32-dma3 bindings, the user can ask for a channel with specific FIFO size. Signed-off-by: Amelie Delaunay <[email protected]> Signed-off-by: Alexandre Torgue <[email protected]>
2024-06-05arm64: dts: st: add power domain on stm32mp25Patrick Delaunay2-0/+25
Add power domains on STM32MP25x SoC for supported low power modes: - CPU_PD0/1: domain for idle of each core Cortex A35 (CStop) - CLUSTER_PD: D1 domain with Stop1 and LP-Stop1 modes support when the Cortex A35 cluster and each device assigned to CPU1=CA35 are deactivated - RET_PD: D1 domain retention (VDDCore is reduced) to support the LPLV-Stop1 mode Signed-off-by: Patrick Delaunay <[email protected]> Signed-off-by: Alexandre Torgue <[email protected]>
2024-06-05arm64: dts: st: add usart6 on stm32mp257f-ev1 boardValentin Caron1-0/+10
Add node for USART6 on stm32mp257f-ev1 board. Signed-off-by: Valentin Caron <[email protected]> Signed-off-by: Alexandre Torgue <[email protected]>
2024-06-05arm64: dts: st: add usart6 pinctrl used on stm32mp257f-ev1 boardValentin Caron1-0/+41
Add pins for USART6 on GPIO connector on stm32mp257f-ev1 board. Signed-off-by: Valentin Caron <[email protected]> Signed-off-by: Alexandre Torgue <[email protected]>
2024-06-05arm64: dts: st: add usart nodes on stm32mp25Valentin Caron1-0/+72
Update device-tree stm32mp251.dtsi to add some USART features. Add u(s)art 1, 3, 4, 5, 6, 7, 8, 9 nodes and compatible, interrupts, clocks, access-controllers properties. Signed-off-by: Valentin Caron <[email protected]> Signed-off-by: Alexandre Torgue <[email protected]>
2024-06-05arm64: dts: st: enable STM32 access controller for RCCGabriel Fernandez1-0/+1
Use an STM32 access controller to filter the registration of clocks. Signed-off-by: Gabriel Fernandez <[email protected]> Signed-off-by: Alexandre Torgue <[email protected]>
2024-06-05arm64: dts: st: OP-TEE async notif on PPI 15 for stm32mp25Etienne Carriere2-1/+7
Define GIC PPI 15 (aka GIC interrupt line 31) for OP-TEE asynchronous notification. Signed-off-by: Etienne Carriere <[email protected]> Signed-off-by: Pascal Paillet <[email protected]> Signed-off-by: Alexandre Torgue <[email protected]>
2024-05-14Merge tag 'irq-core-2024-05-12' of ↵Linus Torvalds1-0/+176
git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip Pull interrupt subsystem updates from Thomas Gleixner: "Core code: - Interrupt storm detection for the lockup watchdog: Lockups which are caused by interrupt storms are not easy to debug because there is no information about the events which make the lockup detector trigger. To make this more user friendly, provide an extenstion to interrupt statistics which allows to take snapshots and an interface to retrieve the delta to the snapshot. Use this new mechanism in the watchdog code to do a two stage lockup analysis by taking the snapshot and printing the deltas for the topmost active interrupts on the second trigger. Note: This contains both the interrupt and the watchdog changes as the latter depend on the former obviously. - Avoid summation loops in the /proc/interrupts output and use the global counter when possible - Skip suspended interrupts on CPU hotplug operations to ensure that they are not delivered before the system resumes the device drivers when coming out of suspend. - On CPU hot-unplug interrupts which are affine to the outgoing CPU are migrated to a different CPU in the affinity mask. This can fail when the CPUs have no vectors left. Instead of giving up try to migrate it to any online CPU and thereby breaking the affinity setting in order to prevent a stale device interrupt which targets an offline CPU - The usual small cleanups Driver code: - Support for the RISCV AIA MSI controller - Make the interrupt allocation for the Loongson PCH controller more flexible to prevent vector exhaustion - The usual set of cleanups and fixes all over the place" * tag 'irq-core-2024-05-12' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (51 commits) irqchip/gic-v3-its: Remove BUG_ON in its_vpe_irq_domain_alloc cpuidle: Avoid explicit cpumask allocation on stack irqchip/sifive-plic: Avoid explicit cpumask allocation on stack irqchip/riscv-aplic-direct: Avoid explicit cpumask allocation on stack irqchip/loongson-eiointc: Avoid explicit cpumask allocation on stack irqchip/gic-v3-its: Avoid explicit cpumask allocation on stack irqchip/irq-bcm6345-l1: Avoid explicit cpumask allocation on stack cpumask: Introduce cpumask_first_and_and() irqchip/irq-brcmstb-l2: Avoid saving mask on shutdown genirq: Reuse irq_is_nmi() genirq/cpuhotplug: Retry with cpu_online_mask when migration fails genirq/cpuhotplug: Skip suspended interrupts when restoring affinity arm64: dts: st: Add interrupt parent to pinctrl on stm32mp251 arm64: dts: st: Add exti1 and exti2 nodes on stm32mp251 ARM: dts: stm32: List exti parent interrupts on stm32mp131 ARM: dts: stm32: List exti parent interrupts on stm32mp151 arm64: Kconfig.platforms: Enable STM32_EXTI for ARCH_STM32 irqchip/stm32-exti: Mark events reserved with RIF configuration check irqchip/stm32-exti: Skip secure events irqchip/stm32-exti: Convert driver to standard PM ...
2024-04-25arm64: dts: st: correct masks for GIC PPI interrupts on stm32mp25Patrick Delaunay2-4/+11
Using GIC_CPU_MASK_SIMPLE(x), x should reflect the number of CPUs. STM32MP251 is a single core Cortex A35, STM32MP253 is a dual core CA35. Fixes: 5d30d03aaf78 ("arm64: dts: st: introduce stm32mp25 SoCs family") Signed-off-by: Patrick Delaunay <[email protected]> Signed-off-by: Alexandre Torgue <[email protected]>
2024-04-25arm64: dts: st: add spi3 / spi8 properties on stm32mp257f-ev1Alain Volmat1-0/+14
Add properties for spi3 and spi8 available on the stm32mp257f-ev1. Both are kept disabled since only used via the gpio expansion connector. Signed-off-by: Alain Volmat <[email protected]> Signed-off-by: Alexandre Torgue <[email protected]>
2024-04-25arm64: dts: st: add spi3/spi8 pins for stm32mp25Alain Volmat1-0/+46
Add the spi3 and spi8 pins used on STM32MP257F-EV1 board. Signed-off-by: Alain Volmat <[email protected]> Signed-off-by: Alexandre Torgue <[email protected]>
2024-04-25arm64: dts: st: add all 8 spi nodes on stm32mp251Alain Volmat1-0/+96
Add the 8 nodes for all spi instances available on the stm32mp251. Signed-off-by: Alain Volmat <[email protected]> Signed-off-by: Alexandre Torgue <[email protected]>
2024-04-25arm64: dts: st: add i2c2 / i2c8 properties on stm32mp257f-ev1Alain Volmat1-0/+20
Add properties for i2c2 and i2c8 available on the stm32mp257f-ev1. i2c2 is enabled since several devices are attached to it while i2c8 is kept disabled since only used via the gpio expansion connector. Signed-off-by: Alain Volmat <[email protected]> Signed-off-by: Alexandre Torgue <[email protected]>
2024-04-25arm64: dts: st: add i2c2/i2c8 pins for stm32mp25Alain Volmat1-0/+36
Add the i2c2 and i2c8 pins used on STM32MP257F-EV1 board. Signed-off-by: Alain Volmat <[email protected]> Signed-off-by: Alexandre Torgue <[email protected]>
2024-04-25arm64: dts: st: add all 8 i2c nodes on stm32mp251Alain Volmat1-0/+104
Add the 8 nodes for all i2c instances available on the stm32mp251. Signed-off-by: Alain Volmat <[email protected]> Signed-off-by: Alexandre Torgue <[email protected]>
2024-04-25arm64: dts: st: add rcc support for STM32MP25Gabriel Fernandez2-38/+110
Add RCC support to manage clocks and resets on the STM32MP25. Signed-off-by: Gabriel Fernandez <[email protected]> Signed-off-by: Alexandre Torgue <[email protected]>
2024-04-25arm64: dts: st: add RIFSC as an access controller for STM32MP25x boardsGatien Chevallier2-19/+21
RIFSC is a firewall controller. Add "st,stm32mp25-rifsc" compatible and reference RIFSC as an access-control-provider. Keep "simple-bus" compatible backward compatibility. Signed-off-by: Gatien Chevallier <[email protected]> Signed-off-by: Alexandre Torgue <[email protected]>
2024-04-23arm64: dts: st: Add interrupt parent to pinctrl on stm32mp251Antonio Borneo1-0/+4
Add exti1 as interrupt parent for the two pin controllers. Add the additional required property st,syscfg. Signed-off-by: Antonio Borneo <[email protected]> Signed-off-by: Thomas Gleixner <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2024-04-23arm64: dts: st: Add exti1 and exti2 nodes on stm32mp251Antonio Borneo1-0/+172
Update the device-tree stm32mp251.dtsi by adding the nodes for exti1 and exti2 interrupt controllers. Signed-off-by: Antonio Borneo <[email protected]> Signed-off-by: Thomas Gleixner <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2024-02-29arm64: dts: st: add video encoder support to stm32mp255Hugues Fruchet2-0/+13
Add VENC hardware video encoder support to STM32MP255. Signed-off-by: Hugues Fruchet <[email protected]> Signed-off-by: Alexandre Torgue <[email protected]>
2024-02-29arm64: dts: st: add video decoder support to stm32mp255Hugues Fruchet2-0/+16
Add VDEC hardware video decoder support to STM32MP255. Signed-off-by: Hugues Fruchet <[email protected]> Signed-off-by: Alexandre Torgue <[email protected]>
2023-12-14arm64: dts: st: add bsec support to stm32mp25Patrick Delaunay1-0/+16
Add BSEC support to STM32MP25 SoC family with SoC information: - RPN = Device part number (BSEC_OTP_DATA9) - PKG = package data register (Bits 2:0 of BSEC_OTP_DATA122) Signed-off-by: Patrick Delaunay <[email protected]> Signed-off-by: Alexandre Torgue <[email protected]>
2023-09-29arm64: dts: st: enable secure arm-wdt watchdog on stm32mp257f-ev1Alexandre Torgue1-0/+5
Enable the watchdog and define the default timeout to 32 seconds. Signed-off-by: Lionel Debieve <[email protected]> Signed-off-by: Alexandre Torgue <[email protected]>
2023-09-22arm64: dts: st: add arm-wdt node for watchdog support on stm32mp251Alexandre Torgue1-0/+6
Add the node to use the ARM SMC watchdog support. It will use a dedicated smc-id to configure and kick the watchdog. Signed-off-by: Lionel Debieve <[email protected]> Signed-off-by: Alexandre Torgue <[email protected]>
2023-09-22arm64: dts: st: add SD-card support on STM32MP257F-EV1 boardYann Gautier1-0/+22
Add the configuration node for SD-card support on STM32MP257F-EV1 board. For the moment it uses a fixed regulator for vmmc, and vqmmc is skipped until regulator driver is available. Signed-off-by: Yann Gautier <[email protected]> Signed-off-by: Alexandre Torgue <[email protected]>
2023-09-22arm64: dts: st: add sdmmc1 pins for stm32mp25Yann Gautier1-0/+54
Add the pins used for SD-card on STM32MP257F-EV1 board. Signed-off-by: Yann Gautier <[email protected]> Signed-off-by: Alexandre Torgue <[email protected]>
2023-09-22arm64: dts: st: add sdmmc1 node in stm32mp251 SoC fileYann Gautier1-0/+13
The SDMMC1 peripheral is used for SD-cards (default on ST boards), or eMMC cards. For the moment it uses the fixed clock ck_flexgen_51, until clock driver is available. Signed-off-by: Yann Gautier <[email protected]> Signed-off-by: Alexandre Torgue <[email protected]>
2023-06-08arm64: dts: st: add stm32mp257f-ev1 board supportAlexandre Torgue3-0/+83
Add STM32MP257F Evaluation board support. It embeds a STM32MP257FAI SoC, with 4GB of DDR4, TSN switch (2+1 ports), 2*USB typeA, 1*USB2 typeC, SNOR OctoSPI, mini PCIe, STPMIC2 for power distribution ... Signed-off-by: Alexandre Torgue <[email protected]>
2023-06-08arm64: dts: st: introduce stm32mp25 pinctrl filesAlexandre Torgue4-0/+232
Three packages exist for stm32mp25 dies. As ball-out is different between them, this patch covers those differences by introducing dedicated pinctrl dtsi files. Each dtsi pinctrl package file describes the package ball-out through gpio-ranges. Available packages are: STM32MP25xAI: 18*18/FCBGA 172 ios STM32MP25xAK: 14*14/FCBGA 144 ios STM32MP25xAL: 10*10/TFBGA 144 ios It includes also the common file used for pin groups definition. Signed-off-by: Alexandre Torgue <[email protected]>
2023-06-08arm64: dts: st: introduce stm32mp25 SoCs familyAlexandre Torgue6-0/+336
STM32MP25 family is composed of 4 SoCs defined as following: -STM32MP251: common part composed of 1*Cortex-A35, common peripherals like SDMMC, UART, SPI, I2C, PCIe, USB3, parallel and DSI display, 1*ETH ... -STM32MP253: STM32MP251 + 1*Cortex-A35 (dual CPU), a second ETH, CAN-FD and LVDS display. -STM32MP255: STM32MP253 + GPU/AI and video encode/decode. -STM32MP257: STM32MP255 + ETH TSN switch (2+1 ports). A second diversity layer exists for security features/ A35 frequency: -STM32MP25xY, "Y" gives information: -Y = A means [email protected] + no cryp IP and no secure boot. -Y = C means [email protected] + cryp IP and secure boot. -Y = D means [email protected] + no cryp IP and no secure boot. -Y = F means [email protected] + cryp IP and secure boot. Signed-off-by: Alexandre Torgue <[email protected]>
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