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2024-06-04arm64: dts: microchip: sparx5_pcb135: move non-MMIO nodes out of axiKrzysztof Kozlowski1-48/+47
simple-bus nodes, so the "axi" node, should not have non-MMIO children as pointed out by simple-bus schema dtbs_check: sparx5_pcb135_emmc.dtb: axi@600000000: sfp-eth60: {'compatible': ... should not be valid under {'type': 'object'} from schema $id: http://devicetree.org/schemas/simple-bus.yaml# Reported-by: Rob Herring <[email protected]> Closes: https://lore.kernel.org/all/CAL_Jsq+PtL3HTKkA_gwTjb_i1mFZ+wW+qwin34HMYmwW7oNDFw@mail.gmail.com/ Signed-off-by: Krzysztof Kozlowski <[email protected]> Signed-off-by: Conor Dooley <[email protected]>
2024-06-04arm64: dts: microchip: sparx5_pcb134: move non-MMIO nodes out of axiKrzysztof Kozlowski1-178/+194
simple-bus nodes, so the "axi" node, should not have non-MMIO children as pointed out by simple-bus schema dtbs_check: sparx5_pcb134.dtb: axi@600000000: i2c-mux-0: {'compatible': ... should not be valid under {'type': 'object'} from schema $id: http://devicetree.org/schemas/simple-bus.yaml# Reported-by: Rob Herring <[email protected]> Closes: https://lore.kernel.org/all/CAL_Jsq+PtL3HTKkA_gwTjb_i1mFZ+wW+qwin34HMYmwW7oNDFw@mail.gmail.com/ Signed-off-by: Krzysztof Kozlowski <[email protected]> Signed-off-by: Conor Dooley <[email protected]>
2024-04-08arm64: dts: microchip: sparx5_pcb135: drop duplicated NOR flashKrzysztof Kozlowski1-9/+0
Since beginning the DTS extended the SPI0 in two places adding two SPI muxes, each with same SPI NOR flash. Both used exactly the same chip-selects, so this was clearly buggy code. Then in commit d0f482bb06f9 ("arm64: dts: sparx5: Add the Sparx5 switch node") one SPI mux was removed, while keeping the SPI NOR flash node. This still leaves duplicated SPI nodes under same chip select 0, reported by dtc W=1 warnings: sparx5_pcb135_board.dtsi:92.10-96.4: Warning (unique_unit_address_if_enabled): /axi@600000000/spi@600104000/flash@0: duplicate unit-address (also used in node /axi@600000000/spi@600104000/spi@0) Steen Hegelund confirmed that in fact there is a SPI mux, thus remove the duplicated node without the mux. Signed-off-by: Krzysztof Kozlowski <[email protected]> Tested-by: Steen Hegelund <[email protected]> Reviewed-by: Steen Hegelund <[email protected]> Signed-off-by: Conor Dooley <[email protected]>
2024-04-08arm64: dts: microchip: sparx5_pcb134: drop duplicated NOR flashKrzysztof Kozlowski1-9/+0
Since beginning the DTS extended the SPI0 in two places adding two SPI muxes, each with same SPI NOR flash. Both used exactly the same chip-selects, so this was clearly buggy code. Then in commit d0f482bb06f9 ("arm64: dts: sparx5: Add the Sparx5 switch node") one SPI mux was removed, while keeping the SPI NOR flash node. This still leaves duplicated SPI nodes under same chip select 0, reported by dtc W=1 warnings: sparx5_pcb134_board.dtsi:277.10-281.4: Warning (unique_unit_address_if_enabled): /axi@600000000/spi@600104000/flash@0: duplicate unit-address (also used in node /axi@600000000/spi@600104000/spi@0) Steen Hegelund confirmed that in fact there is a SPI mux, thus remove the duplicated node without the mux. Signed-off-by: Krzysztof Kozlowski <[email protected]> Tested-by: Steen Hegelund <[email protected]> Reviewed-by: Steen Hegelund <[email protected]> Reviewed-by: Steen Hegelund <[email protected]> Signed-off-by: Conor Dooley <[email protected]>
2024-04-08arm64: dts: microchip: sparx5_pcb135: drop LED unit addressesKrzysztof Kozlowski1-8/+8
GPIO leds should not have unit addresses (no "reg" property), as reported by dtc W=1 warnings: sparx5_pcb135_board.dtsi:18.9-22.5: Warning (unit_address_vs_reg): /leds/led@0: node has a unit name, but no reg or ranges property Signed-off-by: Krzysztof Kozlowski <[email protected]> Reviewed-by: Steen Hegelund <[email protected]> Signed-off-by: Conor Dooley <[email protected]>
2024-04-08arm64: dts: microchip: sparx5_pcb134: drop LED unit addressesKrzysztof Kozlowski1-48/+48
GPIO leds should not have unit addresses (no "reg" property), as reported by dtc W=1 warnings: sparx5_pcb134_board.dtsi:18.9-21.5: Warning (unit_address_vs_reg): /leds/led@0: node has a unit name, but no reg or ranges property Signed-off-by: Krzysztof Kozlowski <[email protected]> Reviewed-by: Steen Hegelund <[email protected]> Signed-off-by: Conor Dooley <[email protected]>
2024-04-08arm64: dts: microchip: sparx5_pcb135: align I2C mux node name with bindingsKrzysztof Kozlowski1-1/+1
DT schema expects node names to match certain. This fixes dtbs_check warnings like: sparx5_pcb135_emmc.dtb: i2c0-imux@0: $nodename:0: 'i2c0-imux@0' does not match '^(i2c-?)?mux' and dtc W=1 warnings: sparx5_pcb135_board.dtsi:132.25-137.4: Warning (simple_bus_reg): /axi@600000000/i2c0-imux@0: missing or empty reg/ranges property Signed-off-by: Krzysztof Kozlowski <[email protected]> Reviewed-by: Steen Hegelund <[email protected]> Signed-off-by: Conor Dooley <[email protected]>
2024-04-08arm64: dts: microchip: sparx5_pcb134: align I2C mux node name with bindingsKrzysztof Kozlowski1-2/+2
DT schema expects node names to match certain. This fixes dtbs_check warnings like: sparx5_pcb134_emmc.dtb: i2c0-emux@0: $nodename:0: 'i2c0-emux@0' does not match '^(i2c-?)?mux' and dtc W=1 warnings: sparx5_pcb134_board.dtsi:398.25-403.4: Warning (unique_unit_address_if_enabled): /axi@600000000/i2c0-imux@0: duplicate unit-address (also used in node /axi@600000000/i2c0-emux@0) Signed-off-by: Krzysztof Kozlowski <[email protected]> Reviewed-by: Steen Hegelund <[email protected]> Signed-off-by: Conor Dooley <[email protected]>
2024-04-08arm64: dts: microchip: sparx5_pcb135: add missing I2C mux unit addressesKrzysztof Kozlowski1-4/+4
The children of I2C mux should be named "i2c", according to DT schema and bindings, and they should have unit address. This fixes dtbs_check warnings like: sparx5_pcb135.dtb: i2c0-imux@0: Unevaluated properties are not allowed ('#address-cells', '#size-cells', 'i2c_sfp1', 'i2c_sfp2', 'i2c_sfp3', 'i2c_sfp4' were unexpected) and dtc W=1 warnings: sparx5_pcb135_board.dtsi:172.23-180.4: Warning (simple_bus_reg): /axi@600000000/sfp-eth60: missing or empty reg/ranges property Signed-off-by: Krzysztof Kozlowski <[email protected]> Reviewed-by: Steen Hegelund <[email protected]> Signed-off-by: Conor Dooley <[email protected]>
2024-04-08arm64: dts: microchip: sparx5_pcb134: add missing I2C mux unit addressesKrzysztof Kozlowski1-20/+20
The children of I2C mux should be named "i2c", according to DT schema and bindings, and they should have unit address. This fixes dtbs_check warnings like: sparx5_pcb134_emmc.dtb: i2c0-imux@0: Unevaluated properties are not allowed ('#address-cells', '#size-cells', 'i2c_sfp1', ... and dtc W=1 warnings: sparx5_pcb134_board.dtsi:548.23-555.4: Warning (simple_bus_reg): /axi@600000000/sfp-eth12: missing or empty reg/ranges property Signed-off-by: Krzysztof Kozlowski <[email protected]> Reviewed-by: Steen Hegelund <[email protected]> Signed-off-by: Conor Dooley <[email protected]>
2024-04-08arm64: dts: microchip: sparx5: correct serdes unit addressKrzysztof Kozlowski1-1/+1
Unit address should match "reg" property, as reported by dtc W=1 warnings: sparx5.dtsi:463.27-468.5: Warning (simple_bus_reg): /axi@600000000/serdes@10808000: simple-bus unit address format error, expected "610808000" Signed-off-by: Krzysztof Kozlowski <[email protected]> Reviewed-by: Steen Hegelund <[email protected]> Signed-off-by: Conor Dooley <[email protected]>
2024-04-08arm64: dts: microchip: sparx5: fix mdio regKrzysztof Kozlowski1-1/+1
Correct the reg address of mdio node to match unit address. Assume the reg is not correct and unit address was correct, because there is already node using the existing reg 0x110102d4. sparx5.dtsi:443.25-451.5: Warning (simple_bus_reg): /axi@600000000/mdio@6110102f8: simple-bus unit address format error, expected "6110102d4" Fixes: d0f482bb06f9 ("arm64: dts: sparx5: Add the Sparx5 switch node") Reviewed-by: Horatiu Vultur <[email protected]> Signed-off-by: Krzysztof Kozlowski <[email protected]> Reviewed-by: Steen Hegelund <[email protected]> Signed-off-by: Conor Dooley <[email protected]>
2023-07-29arm64: dts: microchip: minor whitespace cleanup around '='Krzysztof Kozlowski1-6/+6
The DTS code coding style expects exactly one space before and after '=' sign. Signed-off-by: Krzysztof Kozlowski <[email protected]> Reviewed-by: Steen Hegelund <[email protected]> Signed-off-by: Conor Dooley <[email protected]> Link: https://lore.kernel.org/r/[email protected] [claudiu.beznea: added link] Signed-off-by: Claudiu Beznea <[email protected]>
2023-05-17arm64: dts: sparx5: rename pinctrl nodesMichael Walle2-18/+18
The pinctrl device tree binding will be converted to YAML format. Rename the pin nodes so they end with "-pins" to match the schema. Signed-off-by: Michael Walle <[email protected]> Link: https://lore.kernel.org/r/[email protected] Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Krzysztof Kozlowski <[email protected]>
2023-05-17arm64: dts: microchip: sparx5: correct CPU address-cellsRobert Marko1-3/+3
There is no reason for CPU node #address-cells to be set at 2, so lets change them to 1 and update the reg property accordingly. Signed-off-by: Robert Marko <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Krzysztof Kozlowski <[email protected]>
2023-05-17arm64: dts: microchip: sparx5: do not use PSCI on reference boardsRobert Marko2-1/+13
PSCI is not implemented on SparX-5 at all, there is no ATF and U-boot that is shipped does not implement it as well. I have tried flashing the latest BSP 2022.12 U-boot which did not work. After contacting Microchip, they confirmed that there is no ATF for the SoC nor PSCI implementation which is unfortunate in 2023. So, disable PSCI as otherwise kernel crashes as soon as it tries probing PSCI with, and the crash is only visible if earlycon is used. Since PSCI is not implemented, switch core bringup to use spin-tables which are implemented in the vendor U-boot and actually work. Tested on PCB134 with eMMC (VSC5640EV). Fixes: 6694aee00a4b ("arm64: dts: sparx5: Add basic cpu support") Signed-off-by: Robert Marko <[email protected]> Acked-by: Steen Hegelund <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Krzysztof Kozlowski <[email protected]>
2023-05-17arm64: dts: microchip: add missing cache propertiesKrzysztof Kozlowski1-0/+2
As all level 2 and level 3 caches are unified, add required cache-unified and cache-level properties to fix warnings like: sparx5_pcb125.dtb: l2-cache0: 'cache-level' is a required property Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Krzysztof Kozlowski <[email protected]>
2023-01-28arm64: dts: microchip: use "okay" for statusKrzysztof Kozlowski2-4/+4
"okay" over "ok" is preferred for status property. Reviewed-by: Steen Hegelund <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Krzysztof Kozlowski <[email protected]>
2023-01-13arm64: dts: microchip: drop 0x from unit addressKrzysztof Kozlowski1-1/+1
By coding style, unit address should not start with 0x. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Krzysztof Kozlowski <[email protected]>
2022-06-16arm64: dts: microchip: adjust whitespace around '='Krzysztof Kozlowski2-124/+124
Fix whitespace coding style: use single space instead of tabs or multiple spaces around '=' sign in property assignment. No functional changes (same DTB). Signed-off-by: Krzysztof Kozlowski <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2022-04-26arm64: dts: microchip: align SPI NOR node name with dtschemaKrzysztof Kozlowski4-7/+7
The node names should be generic and SPI NOR dtschema expects "flash". Signed-off-by: Krzysztof Kozlowski <[email protected]> Reviewed-by: Tudor Ambarus <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2022-03-04dts: sparx5: Enable ptp interruptHoratiu Vultur1-2/+3
Add support for ptp interrupt. This interrupt is used when using 2-step timestamping. For each timestamp that is added in a queue, an interrupt is generated. Signed-off-by: Horatiu Vultur <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2021-08-20arm64: dts: sparx5: Add the Sparx5 switch frame DMA supportSteen Hegelund1-2/+3
This adds the interrupt for the Sparx5 Frame DMA. If this configuration is present the Sparx5 SwitchDev driver will use the Frame DMA feature, and if not it will use register based injection and extraction for sending and receiving frames to the CPU. Signed-off-by: Steen Hegelund <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2021-06-24arm64: dts: sparx5: Add the Sparx5 switch nodeSteen Hegelund3-84/+1112
This provides the configuration for the currently available evaluation boards PCB134 and PCB135. The series depends on the following series currently on its way into the kernel: - Sparx5 Reset Driver Link: https://lore.kernel.org/r/[email protected]/ Signed-off-by: Steen Hegelund <[email protected]> Signed-off-by: Lars Povlsen <[email protected]> Signed-off-by: Bjarni Jonasson <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2020-12-10arm64: dts: sparx5: Add SGPIO devicesLars Povlsen4-0/+409
This adds SGPIO devices for the Sparx5 SoC and configures it for the applicable reference boards. Signed-off-by: Lars Povlsen <[email protected]> Reviewed-by: Linus Walleij <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2020-12-10arm64: dts: sparx5: Add reset supportLars Povlsen1-0/+5
This adds reset support to the Sparx5 SoC DT. Signed-off-by: Lars Povlsen <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2020-09-16arm64: dts: sparx5: Add spi-nand devicesLars Povlsen5-0/+67
This patch add spi-nand DT nodes to the applicable Sparx5 boards. Signed-off-by: Lars Povlsen <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2020-09-16arm64: dts: sparx5: Add spi-nor supportLars Povlsen3-0/+80
This add spi-nor device nodes to the Sparx5 reference boards. Signed-off-by: Lars Povlsen <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2020-09-16arm64: dts: sparx5: Add SPI controller and associated mmio-muxLars Povlsen1-0/+30
This adds a SPI controller to the Microchip Sparx5 SoC, as well as the mmio-mux that is required to select the right SPI interface for a given SPI device. Signed-off-by: Lars Povlsen <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2020-09-16arm64: dts: sparx5: Add hwmon temperature sensorLars Povlsen1-0/+7
This adds a hwmon temperature node sensor to the Sparx5 SoC. Signed-off-by: Lars Povlsen <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2020-09-16arm64: dts: sparx5: Add Sparx5 eMMC supportLars Povlsen4-0/+93
This adds eMMC support to the applicable Sparx5 board configuration files. Signed-off-by: Lars Povlsen <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2020-07-28arm64: dts: sparx5: Add i2c devices, i2c muxesLars Povlsen5-0/+360
This patch adds i2c devices and muxes to the Sparx5 reference boards. Link: https://lore.kernel.org/r/[email protected] Reviewed-by: Alexandre Belloni <[email protected]> Signed-off-by: Lars Povlsen <[email protected]> Signed-off-by: Arnd Bergmann <[email protected]>
2020-07-28arm64: dts: sparx5: Add Sparx5 SoC DPLL clockLars Povlsen1-16/+23
This adds a DPLL clock to the Sparx5 SoC. It is used to generate clock to misc peripherals, specifically the SDHCI/eMMC controller. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Lars Povlsen <[email protected]> Signed-off-by: Arnd Bergmann <[email protected]>
2020-07-22arm64: dts: sparx5: Add pinctrl supportLars Povlsen3-0/+36
This add pinctrl support to the Microchip Sparx5 SoC. Link: https://lore.kernel.org/r/[email protected] Reviewed-by: Alexandre Belloni <[email protected]> Signed-off-by: Lars Povlsen <[email protected]> Signed-off-by: Arnd Bergmann <[email protected]>
2020-07-22arm64: dts: sparx5: Add basic cpu supportLars Povlsen10-0/+266
This adds the basic DT structure for the Microchip Sparx5 SoC, and the reference boards, pcb125, pcb134 and pcb135. The two latter have a NAND vs a eMMC centric variant (as a mount option). Link: https://lore.kernel.org/r/[email protected] Reviewed-by: Alexandre Belloni <[email protected]> Signed-off-by: Lars Povlsen <[email protected]> Signed-off-by: Arnd Bergmann <[email protected]>
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