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Add cmu_top, cmu_peric0 clock nodes and
switch USI clocks instead of dummy fixed-rate-clock.
Signed-off-by: Sunyeal Hong <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Krzysztof Kozlowski <[email protected]>
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Add System Memory Management Unit(SysMMU) for dpum also called iommu.
This sysmmu is version 7.4, which has same functionality as exynos850.
DPUM has 4 dma channel, each channel is mapped to one iommu.
Signed-off-by: Kwanghoon Son <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Krzysztof Kozlowski <[email protected]>
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Add dpum clock for sysmmu, dpu.
Signed-off-by: Kwanghoon Son <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Krzysztof Kozlowski <[email protected]>
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Reboot of gs101 SoC can be handled by setting the
bit(SWRESET_SYSTEM[1]) of SYSTEM_CONFIGURATION register(PMU + 0x3a00).
Poweroff of gs101 SoC can be handled by setting bit(DATA[8]) of
PAD_CTRL_PWR_HOLD register (PMU + 0x3e9c).
Tested using "reboot" and "poweroff -p" commands.
Tested-by: Will McVicker <[email protected]>
Signed-off-by: Peter Griffin <[email protected]>
Reviewed-by: Will McVicker <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Krzysztof Kozlowski <[email protected]>
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All known jackpotlte variants have 4GB of RAM, let's use it all.
RAM was set to 3GB from a mistake in the vendor provided DTS file.
Fixes: 06874015327b ("arm64: dts: exynos: Add initial device tree support for Exynos7885 SoC")
Signed-off-by: David Virag <[email protected]>
Reviewed-by: Sam Protsenko <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Krzysztof Kozlowski <[email protected]>
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Add True Random Number Generator (TRNG) node to Exynos850 SoC dtsi.
Signed-off-by: Sam Protsenko <[email protected]>
Reviewed-by: Krzysztof Kozlowski <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Krzysztof Kozlowski <[email protected]>
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The USB phy requires various power supplies to work.
While we don't have a PMIC driver yet, the supplies should still be
added to the DT.
Add some placeholders, which will be replaced with the real ones once
we implement PMIC.
Signed-off-by: André Draszik <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Krzysztof Kozlowski <[email protected]>
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* 'interrupts' & 'cpus' & 'clocks' are standard/common properties as
per the Devicetree Sources (DTS) Coding Style and therefore should be
sorted alphabetically within the standard/common section
* vendor properties should be last
* reg / ranges should be 2nd/3rd (after compatible)
* status should be last
Do so.
Note: I've left the cpus{} node untouched to keep the grouping of
relatedd properties.
Signed-off-by: André Draszik <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Krzysztof Kozlowski <[email protected]>
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The pinctrl instances hsi1, gsactrl, and gsacore need a clock for
register access to work.
Since we haven't implemented the relevant CMUs for the clocks required
by these instances just add empty clocks for now so as to make the DT
pass the validation checks.
Once the clocks are implmented in the gs101 clock driver, these should
be updated then.
Signed-off-by: André Draszik <[email protected]>
Reviewed-by: Tudor Ambarus <[email protected]>
Link: https://lore.kernel.org/r/20240430-samsung-pinctrl-busclock-dts-v2-4-14fc988139dd@linaro.org
Signed-off-by: Krzysztof Kozlowski <[email protected]>
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This bus clock is needed for pinctrl register access to work. Add it.
Signed-off-by: André Draszik <[email protected]>
Reviewed-by: Tudor Ambarus <[email protected]>
Link: https://lore.kernel.org/r/20240430-samsung-pinctrl-busclock-dts-v2-3-14fc988139dd@linaro.org
Signed-off-by: Krzysztof Kozlowski <[email protected]>
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This bus clock is needed for pinctrl register access to work. Add it.
Signed-off-by: André Draszik <[email protected]>
Reviewed-by: Tudor Ambarus <[email protected]>
Link: https://lore.kernel.org/r/20240430-samsung-pinctrl-busclock-dts-v2-2-14fc988139dd@linaro.org
Signed-off-by: Krzysztof Kozlowski <[email protected]>
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This bus clock is needed for pinctrl register access to work. Add it.
Signed-off-by: André Draszik <[email protected]>
Reviewed-by: Tudor Ambarus <[email protected]>
Link: https://lore.kernel.org/r/20240430-samsung-pinctrl-busclock-dts-v2-1-14fc988139dd@linaro.org
Signed-off-by: Krzysztof Kozlowski <[email protected]>
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Enable ufs & ufs phy nodes for Oriole. Also define the ufs regulator node.
ufs regulator is a stub until full s2mpg11 slave pmic support is added.
The gpio defined is for the BOOTLD0 (gs101) signal connected to
UFS_EN(s2mpg11) gpio enabled voltage rail for UFS.
Signed-off-by: Peter Griffin <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Krzysztof Kozlowski <[email protected]>
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Add the ufs controller node and phy node for gs101.
Signed-off-by: Peter Griffin <[email protected]>
Acked-by: André Draszik <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Krzysztof Kozlowski <[email protected]>
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This has some configuration bits such as sharability that
are required by UFS.
Signed-off-by: Peter Griffin <[email protected]>
Reviewed-by: André Draszik <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Krzysztof Kozlowski <[email protected]>
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Pixel 6 (Oriole) has a USB-C connector that can act as host or device.
The USB role is detected dynamically using a MAX77759 TCPCI controller,
but since there is no driver for the MAX77759, the role is defaulted to
peripheral, without any endpoints / ports.
This allows Oriole to be configured as a gadget, e.g. using configfs.
As PMIC regulators are not implemented yet, we rely on USB LDOs being
enabled by the bootloader. A placeholder regulator is used for now.
Signed-off-by: André Draszik <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Krzysztof Kozlowski <[email protected]>
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Add the USB 3.1 Dual Role Device (DRD) controller and USB-PHY nodes for
Google Tensor GS101.
The USB 3.1 DRD controller has the following features:
* compliant with both USB device 3.1 and USB device 2.0 standards
* compliant with USB host 3.1 and USB host 2.0 standards
* supports USB device 3.1 and USB device 2.0 interfaces
* supports USB host 3.1 and USB host 2.0 interfaces
* full-speed (12 Mbps) and high-speed (480 Mbps) modes with USB device
2.0 interface
* super-speed (5 Gbps) mode with USB device 3.1 Gen1 interface
* super-speed plus (10 Gbps) mode with USB device 3.1 Gen2 interface
* single USB port which can be used for USB 3.1 or USB 2.0
* on-chip USB PHY transceiver
* DWC3 compatible
* supports up to 16 bi-directional endpoints
* compliant with xHCI 1.1 specification
Signed-off-by: André Draszik <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Krzysztof Kozlowski <[email protected]>
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Enable the cmu_hsi2 clock management unit. It feeds some of
the high speed interfaces such as PCIe and UFS.
Signed-off-by: Peter Griffin <[email protected]>
Reviewed-by: Tudor Ambarus <[email protected]>
Signed-off-by: André Draszik <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Krzysztof Kozlowski <[email protected]>
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Enable the cmu-hsi0 clock controller. It feeds USB.
Signed-off-by: André Draszik <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Krzysztof Kozlowski <[email protected]>
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Universal Serial Interface (USI) supports three types of serial
interface such as UART, SPI and I2C. Each protocol works independently.
USI can be configured to work as one of these protocols. Define all the
USI nodes from the PERIC blocks (USI0-14), in all their possible
configurations. These blocks have the TX/RX FIFO depth of 64 bytes.
Reviewed-by: Peter Griffin <[email protected]>
Reviewed-by: Alim Akhtar <[email protected]>
Signed-off-by: Tudor Ambarus <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Krzysztof Kozlowski <[email protected]>
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These lines fit 81 characters, which is pretty close to 80.
Join the lines for better readability.
Reviewed-by: Alim Akhtar <[email protected]>
Signed-off-by: Tudor Ambarus <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Krzysztof Kozlowski <[email protected]>
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Move the pinctrl-* properties after clocks so that we keep alphabetic
order and align with the other similar definitions.
Reviewed-by: Alim Akhtar <[email protected]>
Signed-off-by: Tudor Ambarus <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Krzysztof Kozlowski <[email protected]>
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The pinctrl nodes are coming from the shared gs101-pinctrl.dtsi,
thus the pinctrl-0/names shall stay in dtsi. Move them.
Reviewed-by: André Draszik <[email protected]>
Reviewed-by: Alim Akhtar <[email protected]>
Reviewed-by: Peter Griffin <[email protected]>
Signed-off-by: Tudor Ambarus <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Krzysztof Kozlowski <[email protected]>
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The Preferred order for these is pinctrl-0 pinctrl-names.
Update the DTSI & DTS accordingly.
Signed-off-by: André Draszik <[email protected]>
Signed-off-by: Tudor Ambarus <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Krzysztof Kozlowski <[email protected]>
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Define CPU cluster 0 and CPU cluster 1 CMUs, which generate CPU clocks,
and add corresponding CPU clocks to CPU nodes.
Signed-off-by: Sam Protsenko <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Krzysztof Kozlowski <[email protected]>
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Up to now the SPI alias was used as an index into an array defined in
the SPI driver to determine the SPI FIFO depth. Drop the dependency on
the SPI alias and specify the SPI FIFO depth directly into the SPI node.
There are no SPI aliases defined, thus the FIFO depth was determined by
matching the FIFO depth of the I2C node of the same USI parent.
No functional change expected.
Signed-off-by: Tudor Ambarus <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Krzysztof Kozlowski <[email protected]>
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Up to now the SPI alias was used as an index into an array defined in
the SPI driver to determine the SPI FIFO depthj Drop the dependency on
the SPI alias and specify the SPI FIFO depth directly into the SPI node.
The FIFO depth were determined based on the SPI aliases that are defined
in exynos5433-tm2-common.dtsi:
spi0 = &spi_0;
spi1 = &spi_1;
spi2 = &spi_2;
spi3 = &spi_3;
spi4 = &spi_4;
spi-s3c64xx.c driver defines the following fifo_lvl_mask for the
"samsung,exynos5433-spi" compatible:
.fifo_lvl_mask = { 0x1ff, 0x7f, 0x7f, 0x7f, 0x7f, 0x1ff},
Thus spi{0, 4} were considered having 256 byte FIFO depths, and
spi{1, 2, 3} having 64 byte FIFO depths. Update device tree with these
FIFO depths. No functional change expected.
Signed-off-by: Tudor Ambarus <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Krzysztof Kozlowski <[email protected]>
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https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into soc/dt
Samsung DTS ARM64 changes for v6.9
Mostly work around Google GS101 SoC and Pixel phone (Oriole) adding
support for:
1. Multi Core Timer (MCT) clocksource.
2. Several clock controllers (DTS and DT bindings) and use new clocks in
several other device nodes.
3. More serial-interface instances: USI8 and USI12 with I2C.
Exynos850:
1. SPI and DMA controllers (PL330).
* tag 'samsung-dt64-6.9' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux:
arm64: dts: fsd: Add fifosize for UART in Device Tree
arm64: dts: exynos: gs101: minor whitespace cleanup
arm64: dts: exynos: gs101: enable i2c bus 12 on gs101-oriole
arm64: dts: exynos: gs101: define USI12 with I2C configuration
arm64: dts: exynos: gs101: enable cmu-peric1 clock controller
dt-bindings: clock: google,gs101-clock: add PERIC1 clock management unit
arm64: dts: exynos: Add SPI nodes for Exynos850
arm64: dts: exynos: Add PDMA node for Exynos850
arm64: dts: exynos: gs101: use correct clocks for usi_uart
arm64: dts: exynos: gs101: use correct clocks for usi8
arm64: dts: exynos: gs101: sysreg_peric0 needs a clock
arm64: dts: exynos: gs101: enable eeprom on gs101-oriole
arm64: dts: exynos: gs101: define USI8 with I2C configuration
arm64: dts: exynos: gs101: update USI UART to use peric0 clocks
arm64: dts: exynos: gs101: enable cmu-peric0 clock controller
arm64: dts: exynos: gs101: remove reg-io-width from serial
arm64: dts: exynos: gs101: define Multi Core Timer (MCT) node
dt-bindings: clock: exynos850: Add PDMA clocks
dt-bindings: clock: google,gs101-clock: add PERIC0 clock management unit
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Arnd Bergmann <[email protected]>
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The DTS code coding style expects exactly one space before '{' and
around '=' characters.
Reviewed-by: Sam Protsenko <[email protected]>
Reviewed-by: Peter Griffin <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Krzysztof Kozlowski <[email protected]>
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This bus has three USB-related devices attached to it:
0x25: Maxim 77759 Type-C port controller
0x35: Maxim 20339EWB Surge protection IC
0x36: Maxim 77759 Fuel gauge
0x57: NXP PCA9468 Battery charger
0x66: Maxim 77759 PMIC
0x69: Maxim 77759 Charger
where the Maxim 77759 has multiple i2c slave addresses.
These don't have (upstream) Linux drivers yet, but nevertheless we can
enable the bus so as to allow working on them (and to make i2cdetect /
i2cdump / etc. work).
Signed-off-by: André Draszik <[email protected]>
Reviewed-by: Peter Griffin <[email protected]>
Reviewed-by: Tudor Ambarus <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Krzysztof Kozlowski <[email protected]>
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On the gs101-oriole board, i2c bus 12 has various USB-related
controllers attached to it.
Note the selection of the USI protocol is intentionally left for the
board dts file.
Signed-off-by: André Draszik <[email protected]>
Reviewed-by: Sam Protsenko <[email protected]>
Reviewed-by: Tudor Ambarus <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Krzysztof Kozlowski <[email protected]>
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Enable the cmu-peric1 clock controller. It feeds additional USI, I3C
and PWM interfaces / busses.
Note that &sysreg_peric1 needs a clock to be able to access its
registers and now that Linux knows about this clock, we need to add it
in this commit as well so as to keep &sysreg_peric1 working, so that
the clock can be enabled as and when needed.
Signed-off-by: André Draszik <[email protected]>
Reviewed-by: Sam Protsenko <[email protected]>
Reviewed-by: Peter Griffin <[email protected]>
Reviewed-by: Tudor Ambarus <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Krzysztof Kozlowski <[email protected]>
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Some USI blocks can be configured as SPI controllers. Add corresponding
SPI nodes to Exynos850 SoC device tree.
Signed-off-by: Sam Protsenko <[email protected]>
Reviewed-by: Tudor Ambarus <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Krzysztof Kozlowski <[email protected]>
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Enable PDMA node. It's needed for multiple peripheral modules, like SPI.
Use "arm,pl330-broken-no-flushp" quirk, as otherwise SPI transfers in
DMA mode often fail with error like this:
I/O Error: rx-1 tx-1 rx-f tx-f len-786 dma-1 res-(-5)
Signed-off-by: Sam Protsenko <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Krzysztof Kozlowski <[email protected]>
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Wrong pclk clocks have been used in this usi_uart instance here. For
USI and UART, we need the ipclk and pclk, where pclk is the bus clock.
Without it, nothing can work.
It is unclear what exactly is using USI0_UART_CLK, but it is not
required for the IP to be operational at this stage, while pclk is.
This also brings the DT in line with the clock names expected by the
usi and uart drivers.
Fixes: d97b6c902a40 ("arm64: dts: exynos: gs101: update USI UART to use peric0 clocks")
Signed-off-by: André Draszik <[email protected]>
Reviewed-by: Sam Protsenko <[email protected]>
Reviewed-by: Tudor Ambarus <[email protected]>
Tested-by: Tudor Ambarus <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Krzysztof Kozlowski <[email protected]>
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Wrong pclk clocks have been used in this usi8 instance here. For USI
and I2C, we need the ipclk and pclk, where pclk is the bus clock.
Without it, nothing can work.
It is unclear what exactly is using USI8_USI_CLK, but it is not
required for the IP to be operational at this stage, while pclk is.
This also brings the DT in line with the clock names expected by the
usi and i2c drivers.
Fixes: 6d44d1a1fb62 ("arm64: dts: exynos: gs101: define USI8 with I2C configuration")
Signed-off-by: André Draszik <[email protected]>
Reviewed-by: Sam Protsenko <[email protected]>
Reviewed-by: Tudor Ambarus <[email protected]>
Tested-by: Tudor Ambarus <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Krzysztof Kozlowski <[email protected]>
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Without the clock running, we can not access its registers, and now
that we have it, we should add it here so that it gets enabled as
and when needed.
Update the DTSI accordingly.
Signed-off-by: André Draszik <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Krzysztof Kozlowski <[email protected]>
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Enable the eeprom found on the battery connector.
The selection of the USI protocol is done in the board dts file because
the USI CONFIG register comes with a 0x0 reset value, meaning that USI8
does not have a default protocol (I2C, SPI, UART) at reset.
Reviewed-by: Sam Protsenko <[email protected]>
Reviewed-by: Peter Griffin <[email protected]>
Signed-off-by: Tudor Ambarus <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Krzysztof Kozlowski <[email protected]>
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USI8 I2C is used to communicate with an eeprom found on the battery
connector. Define USI8 in I2C configuration.
USI8 CONFIG register comes with a 0x0 reset value, meaning that USI8
doesn't have a default protocol (I2C, SPI, UART) at reset. Thus the
selection of the protocol is intentionally left for the board dts file.
Reviewed-by: Sam Protsenko <[email protected]>
Signed-off-by: Tudor Ambarus <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Krzysztof Kozlowski <[email protected]>
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Get rid of the dummy clock and start using the cmu_peric0 clocks
for the usi_uart and serial_0 nodes.
Tested the serial at 115200, 1000000 and 3000000 baudrates,
everthing went fine.
Reviewed-by: Sam Protsenko <[email protected]>
Signed-off-by: Tudor Ambarus <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Krzysztof Kozlowski <[email protected]>
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Enable the cmu-peric0 clock controller. It feeds USI and I3c.
Reviewed-by: Sam Protsenko <[email protected]>
Reviewed-by: Peter Griffin <[email protected]>
Signed-off-by: Tudor Ambarus <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Krzysztof Kozlowski <[email protected]>
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Remove the reg-io-width property in order to comply with the bindings.
The entire bus (PERIC) on which the GS101 serial resides only allows
32-bit register accesses. The reg-io-width dt property is disallowed
for the "google,gs101-uart" compatible and instead the iotype is
inferred from the compatible.
Reviewed-by: Peter Griffin <[email protected]>
Reviewed-by: Sam Protsenko <[email protected]>
Signed-off-by: Tudor Ambarus <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Krzysztof Kozlowski <[email protected]>
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MCT has one global timer and 8 CPU local timers. The global timer
can generate 4 interrupts, and each local timer can generate an
interrupt making 12 interrupts in total.
Signed-off-by: Peter Griffin <[email protected]>
Reviewed-by: Sam Protsenko <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Krzysztof Kozlowski <[email protected]>
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The cmu_misc clock-names were renamed to just "bus" and "sss" because
naming is local to the module, so cmu_misc is implied. As the bindings
and the device tree have not made a release yet, comply with the
renamed clocks.
Suggested-by: Rob Herring <[email protected]>
Signed-off-by: Tudor Ambarus <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Krzysztof Kozlowski <[email protected]>
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Add initial board support for the Pixel 6 phone code named Oriole. This
has been tested with a minimal busybox initramfs and boots to a shell.
Tested-by: Will McVicker <[email protected]>
Reviewed-by: Sam Protsenko <[email protected]>
Signed-off-by: Peter Griffin <[email protected]>
Reviewed-by: Alim Akhtar <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Krzysztof Kozlowski <[email protected]>
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Google gs101 SoC is a ARMv8 mobile SoC found in the Pixel 6
(oriole), Pixel 6a (bluejay) and Pixel 6 pro (raven) mobile
phones.
It features:
* 4xA55 Little cluster
* 2xA76 Mid cluster
* 2xX1 Big cluster
This commit adds the basic device tree for gs101 (SoC).
Further platform support will be added over time.
Reviewed-by: Sam Protsenko <[email protected]>
Tested-by: Will McVicker <[email protected]>
Signed-off-by: Peter Griffin <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Krzysztof Kozlowski <[email protected]>
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ExynosAutov920 SADK is ExynosAutov920 SoC based SADK(Samsung Automotive
Development Kit) board. It has 16GB(8GB + 8GB) LPDDR5 RAM and 256GB
(128GB + 128GB) UFS.
This is minimal support board device-tree.
* Serial console
* GPIO Key
* PWM FAN
Signed-off-by: Jaewon Kim <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Krzysztof Kozlowski <[email protected]>
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Samsung ExynosAutov920 is ARMv8-based automotive-oriented SoC.
It has AE(Automotive Enhanced) IPs for safety.
* Cortex-A78AE 10-cores
* GIC-600AE
This is minimal support for ExynosAutov920 SoC.
* Enumerate all pinctrl nodes
* Enable Chip-Id
* Serial0 for console
* PWM
Since the clock driver is not yet implemented, it is supported as
fixed-clock.
Signed-off-by: Jaewon Kim <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
[krzysztof: Re-order nodes to match coding style: UFS reset pins,
gpg/gpp in peric0 and peric1, all nodes in the soc@0;
drop fallback compatibles from wakeup-interrupt-controller]
Signed-off-by: Krzysztof Kozlowski <[email protected]>
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ExynosAutov9 pin controller capable of wake-ups is still compatible with
Exynos7, however it does not mux interrupts. Add Exynos7 compatible
fallback to annotate that compatibility and match the bindings.
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Krzysztof Kozlowski <[email protected]>
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Exynos850 pin controller capable of wake-ups is still compatible with
Exynos7, however it does not mux interrupts. Add Exynos7 compatible
fallback to annotate that compatibility and match the bindings.
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Krzysztof Kozlowski <[email protected]>
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