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2024-07-31arm64: dts: fvp: Set stdout-path to serial0 in the chosen nodeDebbie Martin3-3/+9
Add stdout-path to the fast models(FVP and Foundation) devicetrees to specify the primary console. This means that distributions can boot without the need for platform-specific command line parameters i.e. they can use earlycon with no parameters and no console argument is needed at all. Signed-off-by: Debbie Martin <[email protected]> Reviewed-by: Andre Przywara <[email protected]> Message-Id: <[email protected]> Signed-off-by: Sudeep Holla <[email protected]>
2024-07-19Merge tag 'iommu-updates-v6.11' of ↵Linus Torvalds1-0/+1
git://git.kernel.org/pub/scm/linux/kernel/git/iommu/linux Pull iommu updates from Will Deacon: "Core: - Support for the "ats-supported" device-tree property - Removal of the 'ops' field from 'struct iommu_fwspec' - Introduction of iommu_paging_domain_alloc() and partial conversion of existing users - Introduce 'struct iommu_attach_handle' and provide corresponding IOMMU interfaces which will be used by the IOMMUFD subsystem - Remove stale documentation - Add missing MODULE_DESCRIPTION() macro - Misc cleanups Allwinner Sun50i: - Ensure bypass mode is disabled on H616 SoCs - Ensure page-tables are allocated below 4GiB for the 32-bit page-table walker - Add new device-tree compatible strings AMD Vi: - Use try_cmpxchg64() instead of cmpxchg64() when updating pte Arm SMMUv2: - Print much more useful information on context faults - Fix Qualcomm TBU probing when CONFIG_ARM_SMMU_QCOM_DEBUG=n - Add new Qualcomm device-tree bindings Arm SMMUv3: - Support for hardware update of access/dirty bits and reporting via IOMMUFD - More driver rework from Jason, this time updating the PASID/SVA support to prepare for full IOMMUFD support - Add missing MODULE_DESCRIPTION() macro - Minor fixes and cleanups NVIDIA Tegra: - Fix for benign fwspec initialisation issue exposed by rework on the core branch Intel VT-d: - Use try_cmpxchg64() instead of cmpxchg64() when updating pte - Use READ_ONCE() to read volatile descriptor status - Remove support for handling Execute-Requested requests - Avoid calling iommu_domain_alloc() - Minor fixes and refactoring Qualcomm MSM: - Updates to the device-tree bindings" * tag 'iommu-updates-v6.11' of git://git.kernel.org/pub/scm/linux/kernel/git/iommu/linux: (72 commits) iommu/tegra-smmu: Pass correct fwnode to iommu_fwspec_init() iommu/vt-d: Fix identity map bounds in si_domain_init() iommu: Move IOMMU_DIRTY_NO_CLEAR define dt-bindings: iommu: Convert msm,iommu-v0 to yaml iommu/vt-d: Fix aligned pages in calculate_psi_aligned_address() iommu/vt-d: Limit max address mask to MAX_AGAW_PFN_WIDTH docs: iommu: Remove outdated Documentation/userspace-api/iommu.rst arm64: dts: fvp: Enable PCIe ATS for Base RevC FVP iommu/of: Support ats-supported device-tree property dt-bindings: PCI: generic: Add ats-supported property iommu: Remove iommu_fwspec ops OF: Simplify of_iommu_configure() ACPI: Retire acpi_iommu_fwspec_ops() iommu: Resolve fwspec ops automatically iommu/mediatek-v1: Clean up redundant fwspec checks RDMA/usnic: Use iommu_paging_domain_alloc() wifi: ath11k: Use iommu_paging_domain_alloc() wifi: ath10k: Use iommu_paging_domain_alloc() drm/msm: Use iommu_paging_domain_alloc() vhost-vdpa: Use iommu_paging_domain_alloc() ...
2024-07-04arm64: dts: fvp: Enable PCIe ATS for Base RevC FVPJean-Philippe Brucker1-0/+1
Declare that the host controller supports ATS, so the OS can enable it for ATS-capable PCIe endpoints. Acked-by: Sudeep Holla <[email protected]> Signed-off-by: Jean-Philippe Brucker <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Will Deacon <[email protected]>
2024-07-01arm/arm64: dts: arm: Use generic clock and regulator nodenamesRob Herring (Arm)7-25/+25
With the recent defining of preferred naming for fixed clock and regulator nodes, convert the Arm Ltd. boards to use the preferred names. In the cases which had a unit-address, warnings about missing "reg" property are fixed. Signed-off-by: Rob Herring (Arm) <[email protected]> Reviewed-by: Linus Walleij <[email protected]> Reviewed-by: Sudeep Holla <[email protected]> Link: https://lore.kernel.org/[email protected] Signed-off-by: Linus Walleij <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Arnd Bergmann <[email protected]>
2024-06-20arm64: dts: juno: Enable GPURobin Murphy1-1/+0
Both Mali-T620 and Juno's HDLCD are now supported by upstream Mesa in recent distros, so there's little reason not to enable the GPU by default. At the very least it should offer a little extra CI coverage for Panfrost probing and wiggling SCMI. Signed-off-by: Robin Murphy <[email protected]> Acked-by: Liviu Dudau <[email protected]> Link: https://lore.kernel.org/r/07e45a015ff8934c4571617c8e8e90205e430eb6.1718811097.git.robin.murphy@arm.com Signed-off-by: Sudeep Holla <[email protected]>
2024-06-20arm64: dts: juno: add dedicated FPGA syscon compatibleKrzysztof Kozlowski1-1/+2
Each syscon node must come with a dedicated/specific compatible, which is also reported by dtbs_check: juno.dtb: apbregs@10000: compatible: ['syscon', 'simple-mfd'] is too short Signed-off-by: Krzysztof Kozlowski <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Sudeep Holla <[email protected]>
2024-04-29Merge tag 'dt64-cleanup-6.10' of ↵Arnd Bergmann2-4/+4
https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-dt into soc/dt Minor improvements in ARM64 DTS for v6.10 Fixes, which might have practical impact, however things were broken for long enough to justify pushing it regular path: 1. ARM Juno: shorten node names for thermal zones, because Linux drivers have strict limit of 20 characters. 2. HiSilicon: correct size of GIC GICC address space and add missing GICH and GICV spaces, add cache info to properly describe cache topology and solve kernel boot warning. Several cleanups: 1. Use capital "OR" for multiple licenses in SPDX. 2. Correct white-spaces for code readability. 3. Fix W=1 dtc compiler warnings, which should not have practical impact for Amazon, APM, Cavium, Realtek, Socionext Uniphier and Spreadtrum like: - missing unit addresses, - nodes not belonging to soc node, - not using generic node names, - few incorrect unit addresses. * tag 'dt64-cleanup-6.10' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-dt: (28 commits) arm64: dts: cavium: thunder2-99xx: drop redundant reg-names arm64: dts: amazon: alpine-v3: correct gic unit addresses arm64: dts: amazon: alpine-v3: drop cache nodes unit addresses arm64: dts: amazon: alpine-v3: add missing io-fabric unit addresses arm64: dts: amazon: alpine-v2: move non-MMIO node out of soc arm64: dts: amazon: alpine-v2: add missing io-fabric unit addresses arm64: dts: apm: shadowcat: move non-MMIO node out of soc arm64: dts: apm: storm: move non-MMIO node out of soc arm64: dts: cavium: correct unit addresses arm64: dts: cavium: move non-MMIO node out of soc arm64: dts: realtek: rtc16xx: add missing unit address to soc node arm64: dts: realtek: rtd139x: add missing unit address to soc node arm64: dts: realtek: rtd129x: add missing unit address to soc node arm64: dts: uniphier: ld20-global: drop audio codec port unit address arm64: dts: uniphier: ld20-global: use generic node name for audio-codec arm64: dts: uniphier: ld11-global: drop audio codec port unit address arm64: dts: uniphier: ld11-global: use generic node name for audio-codec arm64: dts: sharkl3: add missing unit addresses arm64: dts: whale2: add missing ap-apb unit address arm64: dts: sc9860: move GIC to soc node ... Signed-off-by: Arnd Bergmann <[email protected]>
2024-04-29arm/arm64: dts: Drop "arm,armv8-pmuv3" compatible usageRob Herring1-1/+1
The "arm,armv8-pmuv3" compatible is intended only for s/w models. Primarily, it doesn't provide any detail on uarch specific events. There's still remaining cases for CPUs without any corresponding PMU definition and for big.LITTLE systems which only have a single PMU node (there should be one per core type). Signed-off-by: Rob Herring (Arm) <[email protected]> Reviewed-by: AngeloGioacchino Del Regno <[email protected]> Reviewed-by: Jisheng Zhang <[email protected]> Acked-by: Sudeep Holla <[email protected]> Acked-by: Dinh Nguyen <[email protected]> Acked-by: Heiko Stuebner <[email protected]> Acked-by: Bjorn Andersson <[email protected]> Acked-by: Florian Fainelli <[email protected]> Acked-by: Alim Akhtar <[email protected]> Acked-by: Thierry Reding <[email protected]> Acked-by: Shawn Guo <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Arnd Bergmann <[email protected]>
2024-03-25arm64: dts: juno: fix thermal zone node namesKrzysztof Kozlowski2-4/+4
Linux kernel uses thermal zone node name during registering thermal zones and has a hard-coded limit of 20 characters, including terminating NUL byte. Exceeding the limit will cause failure to configure thermal zone. Reported-by: Rob Herring <[email protected]> Closes: https://lore.kernel.org/all/CAL_JsqKogbT_4DPd1n94xqeHaU_J8ve5K09WOyVsRX3jxxUW3w@mail.gmail.com/ Fixes: fb4d25d7a33f ("arm64: dts: juno: Align thermal zone names with bindings") Reviewed-by: Rob Herring <[email protected]> Acked-by: Sudeep Holla <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Krzysztof Kozlowski <[email protected]>
2023-12-12arm64: dts: juno: Align thermal zone names with bindingsKrzysztof Kozlowski2-12/+12
Thermal bindings require thermal zone node names to match certain patterns: | juno.dtb: thermal-zones: 'big-cluster', 'gpu0', 'gpu1', | 'little-cluster', 'pmic', 'soc' | do not match any of the regexes: | '^[a-zA-Z][a-zA-Z0-9\\-]{1,12}-thermal$', 'pinctrl-[0-9]+' Signed-off-by: Krzysztof Kozlowski <[email protected]> Acked-by: Liviu Dudau <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Sudeep Holla <[email protected]>
2023-08-30Merge tag 'soc-dt-6.6' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/socLinus Torvalds4-20/+16
Pull ARM devicetree updates from Arnd Bergmann: "These are the devicetree updates for Arm and RISC-V based SoCs, mainly from Qualcomm, NXP/Freescale, Aspeed, TI, Rockchips, Samsung, ST and Starfive. Only a few new SoC got added: - TI AM62P5, a variant of the existing Sitara AM62x family - Intel Agilex5, an FPGFA platform that includes an Cortex-A76/A55 SoC. - Qualcomm ipq5018 is used in wireless access points - Qualcomm SM4450 (Snapdragon 4 Gen 2) is a new low-end mobile phone platform. In total, 29 machines get added, which is low because of the summer break. These cover SoCs from Aspeed, Broadcom, NXP, Samsung, ST, Allwinner, Amlogic, Intel, Qualcomm, Rockchip, TI and T-Head. Most of these are development and reference boards. Despite not adding a lot of new machines, there are over 700 patches in total, most of which are cleanups and minor fixes" * tag 'soc-dt-6.6' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (735 commits) arm64: dts: use capital "OR" for multiple licenses in SPDX ARM: dts: use capital "OR" for multiple licenses in SPDX arm64: dts: qcom: sdm845-db845c: Mark cont splash memory region as reserved ARM: dts: qcom: apq8064: add support to gsbi4 uart riscv: dts: change TH1520 files to dual license riscv: dts: thead: add BeagleV Ahead board device tree dt-bindings: riscv: Add BeagleV Ahead board compatibles ARM: dts: stm32: add SCMI PMIC regulators on stm32mp135f-dk board ARM: dts: stm32: STM32MP13x SoC exposes SCMI regulators dt-bindings: rcc: stm32: add STM32MP13 SCMI regulators IDs ARM: dts: stm32: support display on stm32f746-disco board ARM: dts: stm32: rename mmc_vcard to vcc-3v3 on stm32f746-disco ARM: dts: stm32: add pin map for LTDC on stm32f7 ARM: dts: stm32: add ltdc support on stm32f746 MCU arm64: dts: qcom: sm6350: Hook up PDC as wakeup-parent of TLMM arm64: dts: qcom: sdm670: Hook up PDC as wakeup-parent of TLMM arm64: dts: qcom: sa8775p: Hook up PDC as wakeup-parent of TLMM arm64: dts: qcom: sc8280xp: Hook up PDC as wakeup-parent of TLMM arm64: dts: qcom: sdm670: Add PDC riscv: dts: starfive: fix jh7110 qspi sort order ...
2023-08-29arm64: dts: use capital "OR" for multiple licenses in SPDXKrzysztof Kozlowski3-3/+3
Documentation/process/license-rules.rst and checkpatch expect the SPDX identifier syntax for multiple licenses to use capital "OR". Correct it to keep consistent format and avoid copy-paste issues. Signed-off-by: Krzysztof Kozlowski <[email protected]> Reviewed-by: Geert Uytterhoeven <[email protected]> Acked-by: Sudeep Holla <[email protected]> Acked-by: Jernej Skrabec <[email protected]> Acked-by: Geert Uytterhoeven <[email protected]> Acked-by: Florian Fainelli <[email protected]> # Broadcom Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Arnd Bergmann <[email protected]>
2023-07-13arm64: dts: arm: minor whitespace cleanup around '='Krzysztof Kozlowski2-17/+13
The DTS code coding style expects exactly one space before and after '=' sign. Signed-off-by: Krzysztof Kozlowski <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Sudeep Holla <[email protected]>
2023-07-13arm64: dts: arm: Remove the dangling vexpress-v2m-rs1.dtsi symlinkSudeep Holla1-1/+0
Commit 724ba6751532 ("ARM: dts: Move .dts files to vendor sub-directories") moved all arm vendor specific DTS into the sub-directory and updated vexpress-v2f-1xv7-ca53x2.dts accordingly to include vexpress-v2m-rs1.dtsi from the right path. However the symlink was left dangling which is harmless and causes no issue for the build. Just remove the dangling symlink now that it is noticed and reported. Fixes: 724ba6751532 ("ARM: dts: Move .dts files to vendor sub-directories") Cc: Liviu Dudau <[email protected]> Cc: Lorenzo Pieralisi <[email protected]> Cc: Rob Herring <[email protected]> Reported-by: Avram Lubkin <[email protected]> Reported-by: Darren Kenny <[email protected]> Acked-by: Liviu Dudau <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Sudeep Holla <[email protected]>
2023-06-29Merge tag 'soc-dt-6.5' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/socLinus Torvalds1-1/+1
Pull ARM SoC devicetree updates from Arnd Bergmann: "The biggest change this time is for the 32-bit devicetree files, which are all moved to a new location, using separate subdirectories for each SoC vendor, following the same scheme that is used on arm64, mips and riscv. This has been discussed for many years, but so far we never did this as there was a plan to move the files out of the kernel entirely, which has never happened. The impact of this will be that all external patches no longer apply, and anything depending on the location of the dtb files in the build directory will have to change. The installed files after 'make dtbs_install' keep the current location. There are six added SoCs here that are largely variants of previously added chips. Two other chips are added in a separate branch along with their device drivers. - The Samsung Exynos 4212 makes its return after the Samsung Galaxy Express phone is addded at last. The SoC support was originally added in 2012 but removed again in 2017 as it was unused at the time. - Amlogic C3 is a Cortex-A35 based smart IP camera chip - Qualcomm MSM8939 (Snapdragon 615) is a more featureful variant of the still common MSM8916 (Snapdragon 410) phone chip that has been supported for a long time. - Qualcomm SC8180x (Snapdragon 8cx) is one of their earlier high-end laptop chips, used in the Lenovo Flex 5G, which is added along with the reference board. - Qualcomm SDX75 is the latest generation modem chip that is used as a peripherial in phones but can also run a standalone Linux. Unlike the prior 32-bit SDX65 and SDX55, this now has a 64-bit Cortex-A55. - Alibaba T-Head TH1520 is a quad-core RISC-V chip based on the Xuantie C910 core, a step up from all previously added rv64 chips. All of the above come with reference board implementations, those included there are 39 new board files, but only five more 32-bit this time, probably a new low: - Marantec Maveo board based on dhcor imx6ull module - Endian 4i Edge 200, based on the armv5 Marvell Kirkwood chip - Epson Moverio BT-200 AR glasses based on TI OMAP4 - PHYTEC STM32MP1-3 Dev board based on STM32MP15 PHYTEC SOM - ICnova ADB4006 board based on Allwinner A20 On the 64-bit side, there are also fewer addded machines than we had in the recent releases: - Three boards based on NXP i.MX8: Emtop SoM & Baseboard, NXP i.MX8MM EVKB board and i.MX8MP based Gateworks Venice gw7905-2x device. - NVIDIA IGX Orin and Jetson Orin Nano boards, both based on tegra234 - Qualcomm gains support for 6 reference boards on various members of their IPQ networking SoC series, as well as the Sony Xperia M4 Aqua phone, the Acer Aspire 1 laptop, and the Fxtec Pro1X board on top of the various reference platforms for their new chips. - Rockchips support for several newer boards: Indiedroid Nova (rk3588), Edgeble Neural Compute Module 6B (rk3588), FriendlyARM NanoPi R2C Plus (rk3328), Anbernic RG353PS (rk3566), Lunzn Fastrhino R66S/R68S (rk3568) - TI K3/AM625 based PHYTEC phyBOARD-Lyra-AM625 board and Toradex Verdin family with AM62 COM, carrier and dev boards Other changes to existing boards contain the usual minor improvements along with - continued updates to clean up dts files based on dtc warnings and binding checks, in particular cache properties and node names - support for devicetree overlays on at91, bcm283x - significant additions to existing SoC support on mediatek, qualcomm, ti k3 family, starfive jh71xx, NXP i.MX6 and i.MX8, ST STM32MP1 As usual, a lot more detail is available in the individual merge commits" * tag 'soc-dt-6.5' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (926 commits) ARM: mvebu: fix unit address on armada-390-db flash ARM: dts: Move .dts files to vendor sub-directories kbuild: Support flat DTBs install ARM: dts: Add .dts files missing from the build ARM: dts: allwinner: Use quoted #include ARM: dts: lan966x: kontron-d10: add PHY interrupts ARM: dts: lan966x: kontron-d10: fix SPI CS ARM: dts: lan966x: kontron-d10: fix board reset ARM: dts: at91: Enable device-tree overlay support for AT91 boards arm: dts: Enable device-tree overlay support for AT91 boards arm64: dts: exynos: Remove clock from Exynos850 pmu_system_controller ARM: dts: at91: use generic name for shutdown controller ARM: dts: BCM5301X: Add cells sizes to PCIe nodes dt-bindings: firmware: brcm,kona-smc: convert to YAML riscv: dts: sort makefile entries by directory riscv: defconfig: enable T-HEAD SoC MAINTAINERS: add entry for T-HEAD RISC-V SoC riscv: dts: thead: add sipeed Lichee Pi 4A board device tree riscv: dts: add initial T-HEAD TH1520 SoC device tree riscv: Add the T-HEAD SoC family Kconfig option ...
2023-06-21ARM: dts: Move .dts files to vendor sub-directoriesRob Herring1-1/+1
The arm dts directory has grown to 1559 boards which makes it a bit unwieldy to maintain and use. Past attempts stalled out due to plans to move .dts files out of the kernel tree. Doing that is no longer planned (any time soon at least), so let's go ahead and group .dts files by vendors. This move aligns arm with arm64 .dts file structure. There's no change to dtbs_install as the flat structure is maintained on install. The naming of vendor directories is roughly in this order of preference: - Matching original and current SoC vendor prefix/name (e.g. ti, qcom) - Current vendor prefix/name if still actively sold (SoCs which have been aquired) (e.g. nxp/imx) - Existing platform name for older platforms not sold/maintained by any company (e.g. gemini, nspire) The whole move was scripted with the exception of MAINTAINERS and a few makefile fixups. Acked-by: Viresh Kumar <[email protected]> Acked-by: Michal Simek <[email protected]> #Xilinx Acked-by: Krzysztof Kozlowski <[email protected]> Acked-by: Neil Armstrong <[email protected]> Acked-by: Paul Barker <[email protected]> Acked-by: Tony Lindgren <[email protected]> Acked-by: Gregory CLEMENT <[email protected]> Acked-by: Heiko Stuebner <[email protected]> Acked-by: Wei Xu <[email protected]> #hisilicon Acked-by: Geert Uytterhoeven <[email protected]> Acked-by: Nick Hawkins <[email protected]> Acked-by: Baruch Siach <[email protected]> Reviewed-by: Linus Walleij <[email protected]> Reviewed-by: Andre Przywara <[email protected]> Acked-by: Andre Przywara <[email protected]> Reviewed-by: Claudiu Beznea <[email protected]> Acked-by: Peter Rosin <[email protected]> Acked-by: Jesper Nilsson <[email protected]> Acked-by: Sudeep Holla <[email protected]> Acked-by: Florian Fainelli <[email protected]> #broadcom Acked-by: Manivannan Sadhasivam <[email protected]> Reviewed-by: Jisheng Zhang <[email protected]> Acked-by: Patrice Chotard <[email protected]> Acked-by: Romain Perier <[email protected]> Acked-by: Alexandre TORGUE <[email protected]> Acked-by: Shawn Guo <[email protected]> Acked-by: Kunihiko Hayashi <[email protected]> Acked-by: Enric Balletbo i Serra <[email protected]> Signed-off-by: Rob Herring <[email protected]>
2023-05-08arm64: dts: arm: add missing cache propertiesKrzysztof Kozlowski3-0/+3
As all level 2 and level 3 caches are unified, add required cache-unified properties to fix warnings like: foundation-v8.dtb: l2-cache0: 'cache-unified' is a required property Signed-off-by: Krzysztof Kozlowski <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Sudeep Holla <[email protected]>
2022-11-18arm64: dts: fvp: Add information about L1 and L2 cachesSudeep Holla1-0/+73
Add the information about L1 and L2 caches on FVP RevC platform. Though the cache size is configurable through the model parameters, having default values in the device tree helps to exercise and debug any code utilising the cache information without the need of real hardware. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Sudeep Holla <[email protected]>
2022-11-18arm64: dts: fvp: Add SPE to Foundation FVPJames Clark1-0/+5
Add SPE DT node to FVP model. If the model doesn't support SPE (e.g., turned off via parameter), the driver will skip the initialisation accordingly and thus is safe. Signed-off-by: James Clark <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Sudeep Holla <[email protected]>
2022-11-08arm64: dts: Update cache properties for Arm Ltd platformsPierre Gondois7-0/+10
The DeviceTree Specification v0.3 specifies that the cache node "compatible" and "cache-level" properties are required. Cf. s3.8 Multi-level and Shared Cache Nodes The 'cache-unified' property should be present if one of the properties for unified cache is present ('cache-size', ...). Update the relevant device trees nodes accordingly. Signed-off-by: Pierre Gondois <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Sudeep Holla <[email protected]>
2022-11-01arm64: dts: juno: Add thermal critical trip pointsCristian Marussi1-0/+14
When thermnal zones are defined, trip points definitions are mandatory. Define a couple of critical trip points for monitoring of existing PMIC and SOC thermal zones. This was lost between txt to yaml conversion and was re-enforced recently via the commit 8c596324232d ("dt-bindings: thermal: Fix missing required property") Cc: Rob Herring <[email protected]> Cc: Krzysztof Kozlowski <[email protected]> Cc: [email protected] Signed-off-by: Cristian Marussi <[email protected]> Fixes: f7b636a8d83c ("arm64: dts: juno: add thermal zones for scpi sensors") Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Sudeep Holla <[email protected]>
2022-08-15arm64: dts: juno: Add missing MHU secure-irqJassi Brar1-1/+2
The MHU secure interrupt exists physically but is missing in the DT node. Specify the interrupt in DT node to fix a warning on Arm Juno board: mhu@2b1f0000: interrupts: [[0, 36, 4], [0, 35, 4]] is too short Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Jassi Brar <[email protected]> Signed-off-by: Sudeep Holla <[email protected]>
2022-08-15arm64: dts: arm: juno: Remove legacy Coresight 'slave-mode' propertyRob Herring1-2/+0
The 'slave-mode' property is not valid under 'in-ports' as it was the legacy way to find input ports. Warnings are generated from the Coresight schema: arch/arm64/boot/dts/arm/juno-r1.dtb: funnel@20150000: in-ports:port@0:endpoint: Unevaluated properties are not allowed ('slave-mode' was unexpected) From schema: Documentation/devicetree/bindings/arm/arm,coresight-dynamic-funnel.yaml Link: https://lore.kernel.org/r/[email protected] Reviewed-by: Suzuki K Poulose <[email protected]> Signed-off-by: Rob Herring <[email protected]> Signed-off-by: Sudeep Holla <[email protected]>
2022-06-29arm64: dts: juno: Add cache-level property to L2 cachesSudeep Holla3-0/+6
Add the missing cache-level property to L2 caches. This is needed if we need to find the last level cache directly from the device tree cache node. Link: https://lore.kernel.org/r/[email protected] Cc: Liviu Dudau <[email protected]> Cc: Lorenzo Pieralisi <[email protected]> Acked-by: Liviu Dudau <[email protected]> Signed-off-by: Sudeep Holla <[email protected]>
2022-06-14arm64: dts: arm: adjust whitespace around '='Krzysztof Kozlowski2-30/+30
Fix whitespace coding style: use single space instead of tabs or multiple spaces around '=' sign in property assignment. No functional changes (same DTB). Link: https://lore.kernel.org/r/[email protected] Acked-by: Liviu Dudau <[email protected]> Signed-off-by: Krzysztof Kozlowski <[email protected]> Signed-off-by: Sudeep Holla <[email protected]>
2022-06-13arm64: dts: arm/juno: Drop erroneous 'mbox-name' propertyRob Herring1-1/+0
The 'mbox-name' property in the Juno mailbox node is undocumented and unused. It's the consumer side of the mailbox binding that have 'mbox-names' properties. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Rob Herring <[email protected]> Signed-off-by: Sudeep Holla <[email protected]>
2022-06-13arm64: dts: arm/fvp-base-revc: Remove 'panel-dpi' compatibleRob Herring1-1/+1
The rtsm-display panel timing node was removed in commit 928faf5e3e8d ("arm64: dts: fvp: Remove panel timings"). Without the node, 'panel-dpi' is not needed either. Link: https://lore.kernel.org/r/[email protected] Cc: Robin Murphy <[email protected]> Cc: Linus Walleij <[email protected]> Signed-off-by: Rob Herring <[email protected]> Signed-off-by: Sudeep Holla <[email protected]>
2022-04-30arm64: dts: juno: Drop useless 'dma-channels/requests' propertiesKrzysztof Kozlowski1-2/+0
The pl330 DMA controller provides number of DMA channels and requests through its registers, so duplicating this information (with a chance of mistakes) in DTS is pointless. Additionally the DTS used always wrong property names which causes DT schema check failures - the bindings documented 'dma-channels' and 'dma-requests' properties without leading hash sign. Another reason is that the number of requests also does not seem right (should be 8). Link: https://lore.kernel.org/r/[email protected] Reported-by: Rob Herring <[email protected]> Signed-off-by: Krzysztof Kozlowski <[email protected]> Signed-off-by: Sudeep Holla <[email protected]>
2022-04-25arm64: dts: fvp: Align virtio device node names with dtschemaSudeep Holla3-5/+5
Align the virtio mmio device tree node names with the schema to avoid any schema warnings. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Sudeep Holla <[email protected]>
2022-04-25arm64: dts: fvp: Add virtio-rng supportDiego Sueiro3-2/+10
The virtio-rng is available from FVP_Base_RevC-2xAEMvA version 11.17, so add the devicetree node to support it. It is disabled by default to avoid any issues with models that doesn't support it. Link: https://lore.kernel.org/r/ac3be672c636091ee1e079cadce776b1fb7e0b2e.1650543392.git.diego.sueiro@arm.com Signed-off-by: Diego Sueiro <[email protected]> Signed-off-by: Sudeep Holla <[email protected]>
2022-04-25arm64: dts: Add Arm corstone1000 platform supportRui Miguel Silva4-0/+248
Corstone1000 is a platform from arm, which includes pre verified Corstone SSE710 sub-system that combines Cortex-A and Cortex-M processors [0]. These device trees contains the necessary bits to support the Corstone 1000 FVP (Fixed Virtual Platform) [1] and the FPGA MPS3 board Cortex-A35 implementation at Cortex-A35 host side of this platform. [2] 0: https://developer.arm.com/documentation/102360/0000 1: https://developer.arm.com/tools-and-software/open-source-software/arm-platforms-software/arm-ecosystem-fvps 2: https://developer.arm.com/documentation/dai0550/c/ Link: https://lore.kernel.org/r/[email protected] Reviewed-by: Rob Herring <[email protected]> Signed-off-by: Rui Miguel Silva <[email protected]> Signed-off-by: Sudeep Holla <[email protected]>
2022-04-14arm64: dts: juno: add CTI entries to device treeMike Leach8-5/+302
Add Coresight Cross Trigger Interface(CTI) entries to the device tree for all the Juno variants. Link: https://lore.kernel.org/r/[email protected] Reviewed-by: Mathieu Poirier <[email protected]> Signed-off-by: Mike Leach <[email protected]> Signed-off-by: Sudeep Holla <[email protected]>
2022-04-14arm64: dts: juno: Fix SCMI power domain IDs for ETF and CS funnelSudeep Holla2-4/+4
The SCMI power domain ID for all the coresight components is 8 while the previous/older SCPI domain was 0. When adding SCMI variant, couple of instances retained SCPI domain ID by mistake. Fix the same by using the correct SCMI power domain ID of 8. Link: https://lore.kernel.org/r/[email protected] Fixes: 96bb0954860a ("arm64: dts: juno: Add separate SCMI variants") Cc: Robin Murphy <[email protected]> Reported-by: Mike Leach <[email protected]> Acked-by: Robin Murphy <[email protected]> Signed-off-by: Sudeep Holla <[email protected]>
2022-03-08Merge tag 'dt64-cleanup-5.18' of ↵Arnd Bergmann1-1/+1
git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into arm/dt Minor cleanup of ARM64 DTS for v5.18 The DT schema expects DMA controller nodes to follow certain node naming and having dma-cells property. Adjust the DTS files to pass DT schema checks. * tag 'dt64-cleanup-5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux: arm64: dts: lg: align pl330 node name with dtschema arm64: dts: lg: add dma-cells to pl330 node arm64: dts: juno: align pl330 node name with dtschema Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Arnd Bergmann <[email protected]>
2022-03-02arm64: dts: juno: align pl330 node name with dtschemaKrzysztof Kozlowski1-1/+1
Fixes dtbs_check warning: dma@7ff00000: $nodename:0: 'dma@7ff00000' does not match '^dma-controller(@.*)?$' Signed-off-by: Krzysztof Kozlowski <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2022-02-21arm64: dts: juno: Add separate SCMI variantsRobin Murphy5-1/+255
While Juno's SCP firmware initially spoke the SCPI protocol, binary releases since 2018, and the newer open-source codebase, only speak SCMI and thus aren't particularly compatibile with the DTs we currently have upstream. Add a parallel set of variant DTs for boards with up-to-date firmware, replacing the SCPI parts with their new SCMI equivalents. Link: https://lore.kernel.org/r/f3516815104f951a05fc0f799681f77d7968f6ac.1645125063.git.robin.murphy@arm.com Signed-off-by: Robin Murphy <[email protected]> Signed-off-by: Sudeep Holla <[email protected]>
2022-01-26arm64: dts: juno: Remove GICv2m dma-rangeRobin Murphy1-2/+1
Although it is painstakingly honest to describe all 3 PCI windows in "dma-ranges", it misses the the subtle distinction that the window for the GICv2m range is normally programmed for Device memory attributes rather than Normal Cacheable like the DRAM windows. Since MMU-401 only offers stage 2 translation, this means that when the PCI SMMU is enabled, accesses through that IPA range unexpectedly lose coherency if mapped as cacheable at the SMMU, due to the attribute combining rules. Since an extra 256KB is neither here nor there when we still have 10GB worth of usable address space, rather than attempting to describe and cope with this detail let's just remove the offending range. If the SMMU is not used then it makes no difference anyway. Link: https://lore.kernel.org/r/856c3f7192c6c3ce545ba67462f2ce9c86ed6b0c.1643046936.git.robin.murphy@arm.com Fixes: 4ac4d146cb63 ("arm64: dts: juno: Describe PCI dma-ranges") Reported-by: Anders Roxell <[email protected]> Acked-by: Liviu Dudau <[email protected]> Signed-off-by: Robin Murphy <[email protected]> Signed-off-by: Sudeep Holla <[email protected]>
2021-11-03Merge tag 'dt-5.16' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/socLinus Torvalds1-8/+19
Pull ARM SoC DT updates from Arnd Bergmann: "This is a rather large update for the ARM devicetree files, after a few quieter releases, with 775 total commits and 47 branches pulled into this one. There are 5 new SoC types plus some minor variations, and a total of 60 new machines, so I'm limiting the summary to the main noteworthy items: - Apple M1 gain support for PCI and pinctrl, getting a bit closer to a usable system out of the box. - Qualcomm gains support for Snapdragon 690 (aka SM6350) as well as SM7225, 11 new smartphones, and three additional Chromebooks, and improvements all over the place. - Samsung gains support for ExynosAutov9, an automotive version of their smartphone SoC, but otherwise no major changes. - Microchip adds the SAMA5D29 SoC in the SAMA5 family, and a number of improvements for the recently added SAMA7 family. The LAN966 SoC that was added in the platform code does not have dts files yet. Two board files are added for the older at91sam9g20 SoC - Aspeed supports two additional server boards using their AST2600 as BMC, and improves support for qemu models - Rockchip RK3566/RK3688 gets added, along with six new development boards using RK3328/RK3399/RK3566, and one Chromebook tablet. - Two NAS boxes are added using the ARMv4 based Gemini platform - One new board is added to the Intel Arria SoC FPGA family - Marvell adds one network switch based on Armada 381 and the new MOCHAbin 7040 development board - NXP adds support for the S32G2 automotive SoC, two imx6 based ebook readers, and three additional development boards, which is notably less than their usual additions, but they also gain improvements to their many existing boards - STmicroelectronics adds their stm32mp13 SoC family along with a reference board - Renesas adds new versions of their R-Car Gen3 SoCs and many updates for their older generations - Broadcom adds support for a number of Cisco Meraki wireless controllers, along with two new boards and other updates for BCM53xx/BCM47xx networking SoCs and the Raspberry Pi boards - Mediatek improves support for the MT81xx SoCs used in Chromebooks as well as the MT76xx networking SoCs - NVIDIA adds a number of cleanups and additional support for more hardware on the already supported machines - TI K3 adds support for three new boards along with cleanups - Toshiba adds one board for the Visconti family - Xilinx adds five new ZynqMP based machines - Amlogic support is added for the Radxa Zero and two Jethub home automation controllers, along with changes to other machines - Rob Herring continues his work on fixing dtc warnings all over the tree. - Minor updates for TI OMAP, Mstar, Allwinner/sunxi, Hisilicon, Ux500, Unisoc" * tag 'dt-5.16' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (720 commits) arm64: dts: apple: j274: Expose PCI node for the Ethernet MAC address arm64: dts: apple: t8103: Add root port interrupt routing arm64: dts: apple: t8103: Add PCIe DARTs arm64: apple: Add PCIe node arm64: apple: Add pinctrl nodes ARM: dts: arm: Update ICST clock nodes 'reg' and node names ARM: dts: arm: Update register-bit-led nodes 'reg' and node names arm64: dts: exynos: add chipid node for exynosautov9 SoC ARM: dts: qcom: fix typo in IPQ8064 thermal-sensor node Revert "arm64: dts: qcom: msm8916-asus-z00l: Add sensors" arm64: dts: qcom: ipq6018: Remove unused 'iface_clk' property from dma-controller node arm64: dts: qcom: ipq6018: Remove unused 'qcom,config-pipe-trust-reg' property arm64: dts: qcom: sm8350: Add CPU topology and idle-states arm64: dts: qcom: Drop unneeded extra device-specific includes arm64: dts: qcom: msm8916: Drop standalone smem node arm64: dts: qcom: Fix node name of rpm-msg-ram device nodes arm64: dts: qcom: msm8916-asus-z00l: Add sensors arm64: dts: qcom: msm8916-asus-z00l: Add SDCard arm64: dts: qcom: msm8916-asus-z00l: Add touchscreen arm64: dts: qcom: sdm845-oneplus: remove devinfo-size from ramoops node ...
2021-10-26ARM: dts: arm: Update register-bit-led nodes 'reg' and node namesRob Herring1-8/+19
Add a 'reg' entry for register-bit-led nodes on the Arm Ltd platforms. The 'reg' entry is the LED control register address. With this, the node name can be updated to use a generic node name, 'led', and a unit-address. Signed-off-by: Rob Herring <[email protected]> Signed-off-by: Linus Walleij <[email protected]> Cc: Linus Walleij <[email protected]> Cc: Liviu Dudau <[email protected]> Cc: Sudeep Holla <[email protected]> Cc: Lorenzo Pieralisi <[email protected]> Cc: [email protected] Link: https://lore.kernel.org/r/[email protected]' Signed-off-by: Arnd Bergmann <[email protected]>
2021-09-26arm: dts: vexpress: Fix motherboard bus 'interrupt-map'Rob Herring1-45/+0
Commit 078fb7aa6a83 ("arm: dts: vexpress: Fix addressing issues with 'motherboard-bus' nodes") broke booting on a couple of 32-bit VExpress boards. The problem is #address-cells size changed, but interrupt-map was not updated. This results in the timer interrupt (and all the other motherboard interrupts) not getting mapped. As the 'interrupt-map' properties are all just duplicates across boards, just move them into vexpress-v2m.dtsi and vexpress-v2m-rs1.dtsi. Strictly speaking, 'interrupt-map' is dependent on the parent interrupt controller, but it's not likely we'll ever have a different parent than GICv2 on these old platforms. If there was one, 'interrupt-map' can still be overridden. Link: https://lore.kernel.org/r/[email protected] Fixes: 078fb7aa6a83 ("arm: dts: vexpress: Fix addressing issues with 'motherboard-bus' nodes") Cc: Guillaume Tucker <[email protected]> Cc: Liviu Dudau <[email protected]> Cc: Sudeep Holla <[email protected]> Cc: Lorenzo Pieralisi <[email protected]> Cc: [email protected] Reported-by: Reported-by: "kernelci.org bot" <[email protected]> Signed-off-by: Rob Herring <[email protected]> Signed-off-by: Sudeep Holla <[email protected]>
2021-09-17arm: dts: vexpress: Fix addressing issues with 'motherboard-bus' nodesRob Herring7-48/+26
The 'motherboard-bus' node in Arm Ltd boards fails schema checks as 'simple-bus' child nodes must have a unit-address. The 'ranges' handling is also wrong (or at least strange) as the mapping of SMC chip selects should be in the 'arm,vexpress,v2m-p1' node rather than a generic 'simple-bus' node. Either there's 1 too many levels of 'simple-bus' nodes or 'ranges' should be moved down a level. The latter change is more simple, so let's do that. As the 'ranges' value doesn't vary for a given motherboard instance, we can move 'ranges' into the motherboard dtsi files. Link: https://lore.kernel.org/r/[email protected] Cc: Andre Przywara <[email protected]> Cc: Sudeep Holla <[email protected]> Cc: Linus Walleij <[email protected]> Reviewed-by: Linus Walleij <[email protected]> Signed-off-by: Rob Herring <[email protected]> Signed-off-by: Sudeep Holla <[email protected]>
2021-09-14arm: dts: vexpress: Drop unused properties from motherboard nodeRob Herring3-6/+0
Drop the '#interrupt-cells' property in the motherboard node which has no effect as the node is neither an interrupt-controller or interrupt-map (that's in the parent node). Drop 'model' as it is not used by software nor documented. Drop 'arm,v2m-memory-map' as it is not used by software. The purpose was to describe which memory map, but that's all described by the DT already. Link: https://lore.kernel.org/r/[email protected] Cc: Andre Przywara <[email protected]> Cc: Sudeep Holla <[email protected]> Cc: Linus Walleij <[email protected]> Reviewed-by: Linus Walleij <[email protected]> Signed-off-by: Rob Herring <[email protected]> Signed-off-by: Sudeep Holla <[email protected]>
2021-09-14arm64: dts: arm: drop unused interrupt-names in MHUKrzysztof Kozlowski1-2/+0
The arm,mhu bindings and driver do not define interrupt-names, so drop the property to fix warnings: arch/arm64/boot/dts/arm/juno-r2.dt.yaml: mhu@2b1f0000: 'interrupt-names' does not match any of the regexes: 'pinctrl-[0-9]+' Link: https://lore.kernel.org/r/[email protected] Acked-by: Liviu Dudau <[email protected]> Signed-off-by: Krzysztof Kozlowski <[email protected]> Signed-off-by: Sudeep Holla <[email protected]>
2021-09-14arm64: dts: arm: align watchdog and mmc node names with dtschemaKrzysztof Kozlowski2-4/+4
Align the watchdog and mmc device node names with the schema to fix warnings like: mmci@50000: $nodename:0: 'mmci@50000' does not match '^mmc(@.*)?$' wdt@f0000: $nodename:0: 'wdt@f0000' does not match '^watchdog(@.*|-[0-9a-f])?$' Link: https://lore.kernel.org/r/[email protected] Acked-by: Liviu Dudau <[email protected]> Signed-off-by: Krzysztof Kozlowski <[email protected]> Signed-off-by: Sudeep Holla <[email protected]>
2021-09-13arm64: dts: fvp: Remove panel timingsRobin Murphy1-12/+0
The simple-panel driver already has hard-coded timings for "arm,rtsm-display", and as such screams at us for trying to override a fixed mode from DT. Since the exact values probably don't matter all that much anyway, just remove the DT node to keep boot quiet. Link: https://lore.kernel.org/r/2701c187cf8e0762df38f68cc069ec2c29a3b5a9.1626283322.git.robin.murphy@arm.com Reviewed-by: Linus Walleij <[email protected]> Signed-off-by: Robin Murphy <[email protected]> Signed-off-by: Sudeep Holla <[email protected]>
2021-06-09arm64: dts: juno: Update SCPI nodes as per the YAML schemaSudeep Holla1-3/+3
The SCPI YAML schema expects standard node names for clocks and power domain controllers. Fix those as per the schema for Juno platforms. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Sudeep Holla <[email protected]>
2021-03-15arm64: dts: juno: Enable more SMMUsRobin Murphy3-1/+8
Now that PCI inbound window restrictions are handled generically between the of_pci resource parsing and the IOMMU layer, and described in the Juno DT, we can finally enable the PCIe SMMU without the risk of DMA mappings inadvertently allocating unusable addresses. Similarly, the relevant support for IOMMU mappings for peripheral transfers has been hooked up in the pl330 driver for ages, so we can happily enable the DMA SMMU without that breaking anything either. Link: https://lore.kernel.org/r/a730070d718cb119f77c8ca1782a0d4189bfb3e7.1614965598.git.robin.murphy@arm.com Signed-off-by: Robin Murphy <[email protected]> Signed-off-by: Sudeep Holla <[email protected]>
2021-03-15arm64: dts: juno: Describe PCI dma-rangesRobin Murphy1-0/+4
The PLDA root complex on Juno relies on an address-based lookup table to generate AXI attributes for inbound PCI transactions, and as such will not pass any transaction not matching any programmed address range. The standard firmware configuration programs 3 entries covering the GICv2m MSI doorbell and the 2 DRAM regions, so add a "dma-ranges" property to describe those usable inbound windows. Link: https://lore.kernel.org/r/720d0a9a42e33148fcac45cd39a727093a32bf32.1614965598.git.robin.murphy@arm.com Signed-off-by: Robin Murphy <[email protected]> Signed-off-by: Sudeep Holla <[email protected]>
2020-09-07arm64: dts: arm: Fix SP805 clock-namesAndre Przywara2-2/+2
The SP805 binding sets the name for the actual watchdog clock to "wdog_clk" (with an underscore). Change the name in the DTs for ARM Ltd. platforms to match that. The Linux and U-Boot driver use the *first* clock for this purpose anyway, so it does not break anything. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Andre Przywara <[email protected]> Signed-off-by: Sudeep Holla <[email protected]>
2020-05-18arm64: dts: juno: Fix SCPI shared mem node nameAndre Przywara1-2/+2
The SRAM DT binding requires child nodes to use a certain node name scheme. Change the naming from scp-shmem to scp-sram to comply with that. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Andre Przywara <[email protected]> Signed-off-by: Sudeep Holla <[email protected]>
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