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Several includes are not needed, so drop them.
Signed-off-by: Rob Herring <[email protected]>
Reviewed-by: Jisheng Zhang <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Arnd Bergmann <[email protected]>
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Making virt_to_pfn() a static inline taking a strongly typed
(const void *) makes the contract of a passing a pointer of that
type to the function explicit and exposes any misuse of the
macro virt_to_pfn() acting polymorphic and accepting many types
such as (void *), (unitptr_t) or (unsigned long) as arguments
without warnings.
Doing this is a bit intrusive: virt_to_pfn() requires
PHYS_PFN_OFFSET and PAGE_SHIFT to be defined, and this is defined in
<asm/page.h>, so this must be included *before* <asm/memory.h>.
The use of macros were obscuring the unclear inclusion order here,
as the macros would eventually be resolved, but a static inline
like this cannot be compiled with unresolved macros.
The naive solution to include <asm/page.h> at the top of
<asm/memory.h> does not work, because <asm/memory.h> sometimes
includes <asm/page.h> at the end of itself, which would create a
confusing inclusion loop. So instead, take the approach to always
unconditionally include <asm/page.h> at the end of <asm/memory.h>
arch/arm uses <asm/memory.h> explicitly in a lot of places,
however it turns out that if we just unconditionally include
<asm/memory.h> into <asm/page.h> and switch all inclusions of
<asm/memory.h> to <asm/page.h> instead, we enforce the right
order and <asm/memory.h> will always have access to the
definitions.
Put an inclusion guard in place making it impossible to include
<asm/memory.h> explicitly.
Link: https://lore.kernel.org/linux-mm/[email protected]/
Signed-off-by: Linus Walleij <[email protected]>
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Support for Marvell Berlin SoCs depends on ARCH_MULTI_V7.
As the latter selects HAVE_SMP, there is no need for MACH_BERLIN_BG2 to
select HAVE_SMP.
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Geert Uytterhoeven <[email protected]>
Cc: Jisheng Zhang <[email protected]>
Cc: Sebastian Hesselbarth <[email protected]>
Acked-by: Arnd Bergmann <[email protected]>
Signed-off-by: Arnd Bergmann <[email protected]>
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Add SPDX license identifiers to all Make/Kconfig files which:
- Have no license information of any form
These files fall under the project license, GPL v2 only. The resulting SPDX
license identifier is:
GPL-2.0-only
Signed-off-by: Thomas Gleixner <[email protected]>
Signed-off-by: Greg Kroah-Hartman <[email protected]>
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Use the appropriate SPDX license identifier and drop the previous
boilerplate license text.
Signed-off-by: Jisheng Zhang <[email protected]>
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I believe the flush_cache_all() after scu_enable() is to "Ensure that
the data accessed by CPU0 before the SCU was initialised is visible
to the other CPUs." as commented in scu_enable(). So here
flush_cache_all() is a duplication, remove it.
Signed-off-by: Jisheng Zhang <[email protected]>
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BG2CD SoC uses r3p0 Cortex-A9 MPCore single-CPU cluster. Autoselect
pertinent errata, the SCU and the global timer, and allow use of the
local timer on uniprocessor kernels.
PL310 L2 cache controller has revision r3p2; no errata to select.
Signed-off-by: Alexander Monakov <[email protected]>
Signed-off-by: Jisheng Zhang <[email protected]>
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For MMU configurations, VECTORS_BASE is always 0xffff0000, a macro
definition will suffice.
For no-MMU, exception base address is dynamically determined in
subsequent patches. To preserve bisectability, now make the
macro applicable for no-MMU scenario too.
Thanks to 0-DAY kernel test infrastructure that found the
bisectability issue. This macro will be restricted to MMU case upon
dynamically determining exception base address for no-MMU.
Once exception address is handled dynamically for no-MMU,
VECTORS_BASE can be removed from Kconfig.
Signed-off-by: afzal mohammed <[email protected]>
Tested-by: Vladimir Murzin <[email protected]>
Signed-off-by: Russell King <[email protected]>
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All low-level PM/SMP code using virt_to_phys() should actually use
__pa_symbol() against kernel symbols. Update code where relevant to move
away from virt_to_phys().
Acked-by: Russell King <[email protected]>
Reviewed-by: Laura Abbott <[email protected]>
Signed-off-by: Florian Fainelli <[email protected]>
Signed-off-by: Russell King <[email protected]>
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This replaces:
- "select ARCH_REQUIRE_GPIOLIB" with "select GPIOLIB" as this can
now be selected directly.
- "select ARCH_WANT_OPTIONAL_GPIOLIB" with no dependency: GPIOLIB
is now selectable by everyone, so we need not declare our
intent to select it.
When ordering the symbols the following rationale was used:
if the selects were in alphabetical order, I moved select GPIOLIB
to be in alphabetical order, but if the selects were not
maintained in alphabetical order, I just replaced
"select ARCH_REQUIRE_GPIOLIB" with "select GPIOLIB".
Cc: Michael Büsch <[email protected]>
Cc: [email protected]
Cc: [email protected]
Signed-off-by: Linus Walleij <[email protected]>
Signed-off-by: Olof Johansson <[email protected]>
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The cpufreq-dt-platdev driver supports creation of cpufreq-dt platform
device now, reuse that and remove similar code from platform code.
Signed-off-by: Viresh Kumar <[email protected]>
Acked-by: Antoine Tenart <[email protected]>
Acked-by: Arnd Bergmann <[email protected]>
Signed-off-by: Rafael J. Wysocki <[email protected]>
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Many ARM sub-architectures use prompts followed by "if" conditional,
but it is wrong.
Please notice the difference between
config ARCH_FOO
bool "Foo SoCs" if ARCH_MULTI_V7
and
config ARCH_FOO
bool "Foo SoCs"
depends on ARCH_MULTI_V7
These two are *not* equivalent!
In the former statement, it is not ARCH_FOO, but its prompt that
depends on ARCH_MULTI_V7. So, it is completely valid that ARCH_FOO
is selected by another, but ARCH_MULTI_V7 is still disabled. As it is
not unmet dependency, Kconfig never warns. This is probably not what
you want.
The former should be used only when you need to do so, and you really
understand what you are doing. (In most cases, it should be wrong!)
For enabling/disabling sub-architectures, the latter is always correct.
As a good side effect, this commit fixes some entries over 80 columns
(mach-imx, mach-integrator, mach-mbevu).
[Arnd: I note that there is not really a bug here, according to
the discussion that followed, but I can see value in being consistent
and in making the lines shorter]
Signed-off-by: Masahiro Yamada <[email protected]>
Acked-by: Maxime Ripard <[email protected]>
Acked-by: Nicolas Ferre <[email protected]>
Acked-by: Heiko Stuebner <[email protected]>
Acked-by: Patrice Chotard <[email protected]>
Acked-by: Liviu Dudau <[email protected]>
Acked-by: Krzysztof Kozlowski <[email protected]>
Acked-by: Jun Nie <[email protected]>
Acked-by: Matthias Brugger <[email protected]>
Acked-by: Simon Horman <[email protected]>
Acked-by: Gregory CLEMENT <[email protected]>
Acked-by: Shawn Guo <[email protected]>
Acked-by: Sebastian Hesselbarth <[email protected]>
Acked-by: Thierry Reding <[email protected]>
Acked-by: Krzysztof Halasa <[email protected]>
Acked-by: Maxime Coquelin <[email protected]>
Signed-off-by: Arnd Bergmann <[email protected]>
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These smp_operations structures are not over-written, so add "const"
qualifier and replace __initdata with __initconst.
Also, add "static" where it is possible.
Signed-off-by: Masahiro Yamada <[email protected]>
Acked-by: Krzysztof Kozlowski <[email protected]>
Acked-by: Maxime Ripard <[email protected]>
Acked-by: Moritz Fischer <[email protected]>
Acked-by: Stephen Boyd <[email protected]> # qcom part
Acked-by: Viresh Kumar <[email protected]>
Acked-by: Patrice Chotard <[email protected]>
Acked-by: Heiko Stuebner <[email protected]>
Acked-by: Wei Xu <[email protected]>
Acked-by: Florian Fainelli <[email protected]>
Acked-by: Sebastian Hesselbarth <[email protected]>
Acked-by: Gregory CLEMENT <[email protected]>
Acked-by: Shawn Guo <[email protected]>
Acked-by: Matthias Brugger <[email protected]>
Acked-by: Thierry Reding <[email protected]>
Acked-by: Nicolas Pitre <[email protected]>
Acked-by: Liviu Dudau <[email protected]>
Acked-by: Linus Walleij <[email protected]>
Signed-off-by: Arnd Bergmann <[email protected]>
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Add cpu hotplug support for berlin SoCs such as BG2 and BG2Q. These SoC
don't support power off cpu independently, but we also want cpu hotplug
support in these SoCs. We achieve this goal by putting the dying CPU in
WFI state after the coherency is disabled, then asserting the dying CPU
reset bit to put the CPU in reset state.
Signed-off-by: Jisheng Zhang <[email protected]>
Signed-off-by: Sebastian Hesselbarth <[email protected]>
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In Berlin SoCs, there are two kinds of cpu reset control registers: the
first one's corresponding bits will be self-cleared after some cycles,
while the second one's bits won't. Previously the first kind of reset
control register is used, this patch uses the second kind one to prepare
for the next hotplug commit.
Signed-off-by: Jisheng Zhang <[email protected]>
Signed-off-by: Sebastian Hesselbarth <[email protected]>
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The Berlin SoCs use cpufreq-dt for cpufreq. Register a platform device.
Signed-off-by: Antoine Tenart <[email protected]>
Signed-off-by: Sebastian Hesselbarth <[email protected]>
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git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC driver updates from Kevin Hilman:
"Some of these are for drivers/soc, where we're now putting
SoC-specific drivers these days. Some are for other driver subsystems
where we have received acks from the appropriate maintainers.
Some highlights:
- simple-mfd: document DT bindings and misc updates
- migrate mach-berlin to simple-mfd for clock, pinctrl and reset
- memory: support for Tegra132 SoC
- memory: introduce tegra EMC driver for scaling memory frequency
- misc. updates for ARM CCI and CCN busses"
* tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (48 commits)
drivers: soc: sunxi: Introduce SoC driver to map SRAMs
arm-cci: Add aliases for PMU events
arm-cci: Add CCI-500 PMU support
arm-cci: Sanitise CCI400 PMU driver specific code
arm-cci: Abstract handling for CCI events
arm-cci: Abstract out the PMU counter details
arm-cci: Cleanup PMU driver code
arm-cci: Do not enable CCI-400 PMU by default
firmware: qcom: scm: Add HDCP Support
ARM: berlin: add an ADC node for the BG2Q
ARM: berlin: remove useless chip and system ctrl compatibles
clk: berlin: drop direct of_iomap of nodes reg property
ARM: berlin: move BG2Q clock node
ARM: berlin: move BG2CD clock node
ARM: berlin: move BG2 clock node
clk: berlin: prepare simple-mfd conversion
pinctrl: berlin: drop SoC stub provided regmap
ARM: berlin: move pinctrl to simple-mfd nodes
pinctrl: berlin: prepare to use regmap provided by syscon
reset: berlin: drop arch_initcall initialization
...
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All ARMv5 and older CPUs invalidate their caches in the early assembly
setup function, prior to enabling the MMU. This is because the L1
cache should not contain any data relevant to the execution of the
kernel at this point; all data should have been flushed out to memory.
This requirement should also be true for ARMv6 and ARMv7 CPUs - indeed,
these typically do not search their caches when caching is disabled (as
it needs to be when the MMU is disabled) so this change should be safe.
ARMv7 allows there to be CPUs which search their caches while caching is
disabled, and it's permitted that the cache is uninitialised at boot;
for these, the architecture reference manual requires that an
implementation specific code sequence is used immediately after reset
to ensure that the cache is placed into a sane state. Such
functionality is definitely outside the remit of the Linux kernel, and
must be done by the SoC's firmware before _any_ CPU gets to the Linux
kernel.
Changing the data cache clean+invalidate to a mere invalidate allows us
to get rid of a lot of platform specific hacks around this issue for
their secondary CPU bringup paths - some of which were buggy.
Reviewed-by: Florian Fainelli <[email protected]>
Tested-by: Florian Fainelli <[email protected]>
Tested-by: Heiko Stuebner <[email protected]>
Tested-by: Dinh Nguyen <[email protected]>
Acked-by: Sebastian Hesselbarth <[email protected]>
Tested-by: Sebastian Hesselbarth <[email protected]>
Acked-by: Shawn Guo <[email protected]>
Tested-by: Thierry Reding <[email protected]>
Acked-by: Thierry Reding <[email protected]>
Tested-by: Geert Uytterhoeven <[email protected]>
Tested-by: Michal Simek <[email protected]>
Tested-by: Wei Xu <[email protected]>
Signed-off-by: Russell King <[email protected]>
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The chip and system controller nodes handle sub-devices, such as the
clock, pinctrl or reset controllers. The drivers handling them need a
regmap provided by syscon. Select it by default when using a Berlin SoC.
Signed-off-by: Antoine Tenart <[email protected]>
Signed-off-by: Sebastian Hesselbarth <[email protected]>
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RESET_CONTROLLER is meant to be user-selectable. To respect that,
do not select it automatically when using ARCH_BERLIN.
Signed-off-by: Antoine Tenart <[email protected]>
Signed-off-by: Sebastian Hesselbarth <[email protected]>
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The Marvell Berlin SoCs now has a reset controller. Add the needed
configuration. While at it reorder Kconfigs alphabetically.
Signed-off-by: Antoine Ténart <[email protected]>
Signed-off-by: Sebastian Hesselbarth <[email protected]>
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git://git.infradead.org/users/hesselba/linux-berlin into next/soc
Merge "Berlin SoC changes for v3.17" from Sebastian Hesselbarth:
- SMP support for BG2 and BG2Q
* tag 'berlin-soc-3.17-1' of git://git.infradead.org/users/hesselba/linux-berlin:
ARM: berlin: add SMP support
Signed-off-by: Olof Johansson <[email protected]>
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The System Type menu is getting quite long with platforms and is
inconsistent in handling of sub-arch specific options. Tidy up the menu
by making platform options a menuconfig entry containing any platform
specific config items.
[arnd: change OMAP part according to suggestion from
Tony Lindgren <[email protected]>]
Signed-off-by: Rob Herring <[email protected]>
Signed-off-by: Arnd Bergmann <[email protected]>
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Adds SMP support for Berlin SoCs. Secondary CPUs are reset, then
execute the instruction we put in the reset exception register, setting
the pc at the address contained in the software reset address register,
which is the physical address of the Berlin secondary startup.
This implementation avoid using the pen lock mechanism.
Signed-off-by: Antoine Ténart <[email protected]>
Reviewed-by: Andrew Lunn <[email protected]>
Signed-off-by: Sebastian Hesselbarth <[email protected]>
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Pull ARM updates from Russell King:
- Major clean-up of the L2 cache support code. The existing mess was
becoming rather unmaintainable through all the additions that others
have done over time. This turns it into a much nicer structure, and
implements a few performance improvements as well.
- Clean up some of the CP15 control register tweaks for alignment
support, moving some code and data into alignment.c
- DMA properties for ARM, from Santosh and reviewed by DT people. This
adds DT properties to specify bus translations we can't discover
automatically, and to indicate whether devices are coherent.
- Hibernation support for ARM
- Make ftrace work with read-only text in modules
- add suspend support for PJ4B CPUs
- rework interrupt masking for undefined instruction handling, which
allows us to enable interrupts earlier in the handling of these
exceptions.
- support for big endian page tables
- fix stacktrace support to exclude stacktrace functions from the
trace, and add save_stack_trace_regs() implementation so that kprobes
can record stack traces.
- Add support for the Cortex-A17 CPU.
- Remove last vestiges of ARM710 support.
- Removal of ARM "meminfo" structure, finally converting us solely to
memblock to handle the early memory initialisation.
* 'for-linus' of git://ftp.arm.linux.org.uk/~rmk/linux-arm: (142 commits)
ARM: ensure C page table setup code follows assembly code (part II)
ARM: ensure C page table setup code follows assembly code
ARM: consolidate last remaining open-coded alignment trap enable
ARM: remove global cr_no_alignment
ARM: remove CPU_CP15 conditional from alignment.c
ARM: remove unused adjust_cr() function
ARM: move "noalign" command line option to alignment.c
ARM: provide common method to clear bits in CPU control register
ARM: 8025/1: Get rid of meminfo
ARM: 8060/1: mm: allow sub-architectures to override PCI I/O memory type
ARM: 8066/1: correction for ARM patch 8031/2
ARM: 8049/1: ftrace/add save_stack_trace_regs() implementation
ARM: 8065/1: remove last use of CONFIG_CPU_ARM710
ARM: 8062/1: Modify ldrt fixup handler to re-execute the userspace instruction
ARM: 8047/1: rwsem: use asm-generic rwsem implementation
ARM: l2c: trial at enabling some Cortex-A9 optimisations
ARM: l2c: add warnings for stuff modifying aux_ctrl register values
ARM: l2c: print a warning with L2C-310 caches if the cache size is modified
ARM: l2c: remove old .set_debug method
ARM: l2c: kill L2X0_AUX_CTRL_MASK before anyone else makes use of this
...
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Remove the explicit call to l2x0_of_init(), converting to the generic
infrastructure instead. We can remove the explicit machine init too
as this becomes identical to the generic version.
Acked-by: Sebastian Hesselbarth <[email protected]>
Signed-off-by: Russell King <[email protected]>
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Since we now automatically enable early BRESP in core L2C-310 code when
we detect a Cortex-A9, we don't need platforms/SoCs to set this bit
explicitly. Instead, they should seek to preserve the value of bit 30
in the auxiliary control register.
Acked-by: Tony Lindgren <[email protected]>
Acked-by: Stephen Warren <[email protected]>
Signed-off-by: Russell King <[email protected]>
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Signed-off-by: Antoine Tenart <[email protected]>
Acked-by: Sebastian Hesselbarth <[email protected]>
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The BG2Q has GPIOs driven by the dwapb GPIO driver. Add the LIBGPIO as a
dependency to be able to support them.
Signed-off-by: Antoine Tenart <[email protected]>
Reviewed-by: Jisheng Zhang <[email protected]>
Signed-off-by: Sebastian Hesselbarth <[email protected]>
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Now that we start supporting the Marvell Berlin BG2Q, add a symbol allowing to
differentiate that SoC from the other SoCs of the Berlin family.
Signed-off-by: Alexandre Belloni <[email protected]>
Signed-off-by: Sebastian Hesselbarth <[email protected]>
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All V7 platforms can run SMP kernels, so make CONFIG_SMP visible for V7
multi-platform builds.
Signed-off-by: Rob Herring <[email protected]>
Acked-by: Stephen Warren <[email protected]>
Acked-by: Arnd Bergmann <[email protected]>
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Multi-platform requires various kconfig options to be selected, so
platforms don't need to select them individually.
Signed-off-by: Rob Herring <[email protected]>
Acked-by: Linus Walleij <[email protected]>
Cc: Russell King <[email protected]>
Acked-by: Stephen Warren <[email protected]>
Tested-by: Stephen Warren <[email protected]>
Acked-by: Arnd Bergmann <[email protected]>
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This adds initial support for the Marvell Berlin SoC family with
Armada 1500 (88DE3100) and Armada 1500-mini (88DE3005) SoCs.
Signed-off-by: Sebastian Hesselbarth <[email protected]>
Reviewed-by: Jason Cooper <[email protected]>
Reviewed-by: Thomas Petazzoni <[email protected]>
Reviewed-by: Arnd Bergmann <[email protected]>
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