aboutsummaryrefslogtreecommitdiff
path: root/arch/arm/include/asm/hardware/cache-tauros2.h
AgeCommit message (Collapse)AuthorFilesLines
2022-06-10treewide: Replace GPLv2 boilerplate/reference with SPDX - gpl-2.0_56.RULE ↵Thomas Gleixner1-4/+1
(part 1) Based on the normalized pattern: this file is licensed under the terms of the gnu general public license version 2 this program is licensed as is without any warranty of any kind whether express or implied extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference. Reviewed-by: Allison Randal <[email protected]> Signed-off-by: Thomas Gleixner <[email protected]> Signed-off-by: Greg Kroah-Hartman <[email protected]>
2012-08-16ARM: cache: add extra feature enable for tauros2Chao Xie1-1/+4
The extra feature may be used by SOCs are prefetch, burst8, write buffer coalesce Signed-off-by: Chao Xie <[email protected]> Signed-off-by: Haojian Zhuang <[email protected]>
2009-11-27ARM: Add Tauros2 L2 cache controller supportLennert Buytenhek1-0/+11
Support for the Tauros2 L2 cache controller as used with the PJ1 and PJ4 CPUs. Signed-off-by: Lennert Buytenhek <[email protected]> Signed-off-by: Saeed Bishara <[email protected]> Signed-off-by: Nicolas Pitre <[email protected]>