| Age | Commit message (Collapse) | Author | Files | Lines | |
|---|---|---|---|---|---|
| 2012-08-16 | ARM: cache: add extra feature enable for tauros2 | Chao Xie | 1 | -1/+4 | |
| The extra feature may be used by SOCs are prefetch, burst8, write buffer coalesce Signed-off-by: Chao Xie <[email protected]> Signed-off-by: Haojian Zhuang <[email protected]> | |||||
| 2009-11-27 | ARM: Add Tauros2 L2 cache controller support | Lennert Buytenhek | 1 | -0/+11 | |
| Support for the Tauros2 L2 cache controller as used with the PJ1 and PJ4 CPUs. Signed-off-by: Lennert Buytenhek <[email protected]> Signed-off-by: Saeed Bishara <[email protected]> Signed-off-by: Nicolas Pitre <[email protected]> | |||||