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git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull SoC update from Arnd Bergmann:
"Convert ep93xx to devicetree
This concludes a long journey towards replacing the old board files
with devictree description on the Cirrus Logic EP93xx platform.
Nikita Shubin has been working on this for a long time, for details
see the last post on
https://lore.kernel.org/lkml/[email protected]/"
* tag 'soc-ep93xx-dt-6.12' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (47 commits)
dt-bindings: gpio: ep9301: Add missing "#interrupt-cells" to examples
MAINTAINERS: Update EP93XX ARM ARCHITECTURE maintainer
soc: ep93xx: drop reference to removed EP93XX_SOC_COMMON config
net: cirrus: use u8 for addr to calm down sparse
dmaengine: cirrus: use snprintf() to calm down gcc 13.3.0
dmaengine: ep93xx: Fix a NULL vs IS_ERR() check in probe()
pinctrl: ep93xx: Fix raster pins typo
spi: ep93xx: update kerneldoc comments for ep93xx_spi
clk: ep93xx: Fix off by one in ep93xx_div_recalc_rate()
clk: ep93xx: add module license
dmaengine: cirrus: remove platform code
ASoC: cirrus: edb93xx: Delete driver
ARM: ep93xx: soc: drop defines
ARM: ep93xx: delete all boardfiles
ata: pata_ep93xx: remove legacy pinctrl use
pwm: ep93xx: drop legacy pinctrl
ARM: ep93xx: DT for the Cirrus ep93xx SoC platforms
ARM: dts: ep93xx: Add EDB9302 DT
ARM: dts: ep93xx: add ts7250 board
ARM: dts: add Cirrus EP93XX SoC .dtsi
...
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Add YAML bindings for ep93xx SoC SPI.
Signed-off-by: Nikita Shubin <[email protected]>
Tested-by: Alexander Sverdlin <[email protected]>
Reviewed-by: Krzysztof Kozlowski <[email protected]>
Reviewed-by: Mark Brown <[email protected]>
Reviewed-by: Andy Shevchenko <[email protected]>
Reviewed-by: Guenter Roeck <[email protected]>
Acked-by: Miquel Raynal <[email protected]>
Acked-by: Vinod Koul <[email protected]>
Signed-off-by: Arnd Bergmann <[email protected]>
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The flexspi on imx8ulp only has 16 number of LUTs, it is different
with flexspi on other imx SoC which has 32 number of LUTs.
Fixes: ef89fd56bdfc ("arm64: dts: imx8ulp: add flexspi node")
Cc: [email protected]
Acked-by: Krzysztof Kozlowski <[email protected]>
Signed-off-by: Haibo Chen <[email protected]>
Reviewed-by: Frank Li <[email protected]>
Link: https://patch.msgid.link/[email protected]
Signed-off-by: Mark Brown <[email protected]>
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It is compatible with the rockchip,rk3066-spi SPI core.
Signed-off-by: Detlev Casanova <[email protected]>
Acked-by: Krzysztof Kozlowski <[email protected]>
Link: https://patch.msgid.link/[email protected]
Signed-off-by: Mark Brown <[email protected]>
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PIC64GX SPI/QSPI are compatible with MPFS SPI/QSPI driver, we just use
fallback mechanism
Signed-off-by: Pierre-Henry Moussay <[email protected]>
Link: https://patch.msgid.link/[email protected]
Signed-off-by: Mark Brown <[email protected]>
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Convert binding doc spi-sc18is602.txt (I2C to SPI bridge) to yaml.
Additional change:
- ref spi-controller.yaml
Fix below warning:
arch/arm64/boot/dts/freescale/fsl-lx2160a-bluebox3.dtb:
/soc/i2c@2000000/i2c-mux@77/i2c@7/i2c-mux@75/i2c@0/spi@28: failed to match any schema with compatible: ['nxp,sc18is602b']
Reviewed-by: Rob Herring (Arm) <[email protected]>
Signed-off-by: Frank Li <[email protected]>
Link: https://patch.msgid.link/[email protected]
Signed-off-by: Mark Brown <[email protected]>
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Merge series from Witold Sadowski <[email protected]>:
This patch series adds support for the second version of the Marvell
hardware overlay for the Cadence xSPI IP block. The overlay is a hardware
change made around the original xSPI block. It extends xSPI features with
clock configuration, interrupt masking, and full-duplex, variable-length SPI
operations.
These functionalities allow the xSPI block to operate not only with memory
devices but also with simple SPI devices and TPM devices.
Example ACPI entry:
Device (SPI0) {
Name (_HID, "PRP0001") // ACPI_DT_NAMESPACE_HID
Name (_UID, 0)
Name (_DDN, "SPI controller 0")
Name (_CCA, ONE)
Method (_STA) {Return (0xF)}
Name (_CRS, ResourceTemplate() {
QWordMemory ( ResourceConsumer,// ResourceUsage
PosDecode, // Decode
MinFixed, // MinType
MaxFixed, // MaxType
NonCacheable, // MemType
ReadWrite, // ReadWriteType
0, // AddressGranularity
0x804000000000, // MinAddress
0x804000001037, // MaxAddress
0, // AddressTranslation
0x1038) // AddressLength
QWordMemory ( ResourceConsumer,// ResourceUsage
PosDecode, // Decode
MinFixed, // MinType
MaxFixed, // MaxType
NonCacheable, // MemType
ReadWrite, // ReadWriteType
0, // AddressGranularity
0x804010000000, // MinAddress
0x804010000007, // MaxAddress
0, // AddressTranslation
0x8) // AddressLength
QWordMemory ( ResourceConsumer,// ResourceUsage
PosDecode, // Decode
MinFixed, // MinType
MaxFixed, // MaxType
NonCacheable, // MemType
ReadWrite, // ReadWriteType
0, // AddressGranularity
0x804000002000, // MinAddress
0x804000004027, // MaxAddress
0, // AddressTranslation
0x2028) // AddressLength
QWordMemory ( ResourceConsumer,// ResourceUsage
PosDecode, // Decode
MinFixed, // MinType
MaxFixed, // MaxType
NonCacheable, // MemType
ReadWrite, // ReadWriteType
0, // AddressGranularity
0x804000008000, // MinAddress
0x804000008237, // MaxAddress
0, // AddressTranslation
0x238) // AddressLength
Interrupt(ResourceConsumer, Edge, ActiveHigh, Exclusive) { 0x7A }
})
Name (_DSD, Package() {
ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
Package () {
Package () { "compatible", "marvell,cn10-xspi-nor"},
Package () { "reg", 0x8040},
}
})
} // SPI0
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MT7981 has SPI controllers based on IPM design
Signed-off-by: Rafał Miłecki <[email protected]>
Acked-by: Krzysztof Kozlowski <[email protected]>
Link: https://patch.msgid.link/[email protected]
Signed-off-by: Mark Brown <[email protected]>
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Cadence XSPI
Add new bindings for the v2 Marvell xSPI overlay: marvell,cn10-xspi-nor
compatible string. This new compatible string distinguishes between the
original and modified xSPI block.
Also add an optional base for the xfer register set with an additional
reg field to allocate the xSPI Marvell overlay XFER block.
Signed-off-by: Witold Sadowski <[email protected]>
Reviewed-by: Krzysztof Kozlowski <[email protected]>
Link: https://patch.msgid.link/[email protected]
Signed-off-by: Mark Brown <[email protected]>
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git://git.kernel.org/pub/scm/linux/kernel/git/vkoul/dmaengine
Pull dmaengine updates from Vinod Koul:
"New support:
- New dmaengine_prep_peripheral_dma_vec() to support transfers using
dma vectors and documentation and user in AXI dma
- STMicro STM32 DMA3 support and new capabilities of cyclic dma
Updates:
- Yaml conversion for Freescale imx dma and qdma bindings,
sprd sc9860 dma binding
- Altera msgdma updates for descriptor management"
* tag 'dmaengine-6.11-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vkoul/dmaengine: (35 commits)
dt-bindings: fsl-qdma: fix interrupts 'if' check logic
dt-bindings: dma: sprd,sc9860-dma: convert to YAML
dmaengine: fsl-dpaa2-qdma: add missing MODULE_DESCRIPTION() macro
dmaengine: ti: add missing MODULE_DESCRIPTION() macros
dmaengine: ti: cppi41: add missing MODULE_DESCRIPTION() macro
dmaengine: virt-dma: add missing MODULE_DESCRIPTION() macro
dmaengine: ti: k3-udma: Fix BCHAN count with UHC and HC channels
dmaengine: sh: rz-dmac: Fix lockdep assert warning
dmaengine: qcom: gpi: clean up the IRQ disable/enable in gpi_reset_chan()
dmaengine: fsl-edma: change the memory access from local into remote mode in i.MX 8QM
dmaengine: qcom: gpi: remove unused struct 'reg_info'
dmaengine: moxart-dma: remove unused struct 'moxart_filter_data'
dt-bindings: fsl-qdma: Convert to yaml format
dmaengine: fsl-edma: remove redundant "idle" field from fsl_chan
dmaengine: fsl-edma: request per-channel IRQ only when channel is allocated
dmaengine: stm32-dma3: defer channel registration to specify channel name
dmaengine: add channel device name to channel registration
dmaengine: stm32-dma3: improve residue granularity
dmaengine: stm32-dma3: add device_pause and device_resume ops
dmaengine: stm32-dma3: add DMA_MEMCPY capability
...
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git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux
Pull devicetree updates from Rob Herring:
"DT Bindings:
- Convert and add a bunch of IBM FSI related bindings
- Add a new schema listing legacy compatibles which will (probably)
never be documented. This will silence various checks warning about
them.
- Add bindings for Sierra Wireless mangOH Green SPI IoT interface,
new Arm 2024 Cortex and Neoverse CPUs, QCom sc8180x PDC, QCom SDX75
GPI DMA, imx8mp/imx8qxp fsl,irqsteer, and Renesas RZ/G2UL CRU and
CSI-2 blocks
- Convert Spreadtrum sprd-timer, FSL cpm_qe, FSL fsl,ls-scfg-msi, FSL
q(b)man-*, FSL qoriq-mc, and img,pdc-wdt bindings to DT schema
- Drop obsolete stericsson,abx500.txt
DT core:
- Update dtc to upstream version v1.7.0-93-g1df7b047fe43
- Add support to run DT validation on DTs with applied overlays
- Add helper for creating boolean properties in dynamic nodes and use
that for dynamic PCI nodes
- Clean-up early parsing of '#{address,size}-cells'"
* tag 'devicetree-for-6.11' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux: (39 commits)
dt-bindings: timer: sprd-timer: convert to YAML
dt-bindings: incomplete-devices: document devices without bindings
dt-bindings: trivial-devices: document the Sierra Wireless mangOH Green SPI IoT interface
scripts/dtc: Update to upstream version v1.7.0-93-g1df7b047fe43
dt-bindings: soc: fsl: Add fsl,ls1028a-reset for reset syscon node
dt-bindings: soc: fsl: cpm_qe: convert to yaml format
dt-bindings: i2c: i2c-fsi: Convert to json-schema
dt-bindings: fsi: Document the FSI Hub Controller
dt-bindings: fsi: Document the AST2700 FSI controller
dt-bindings: fsi: ast2600-fsi-master: Convert to json-schema
dt-bindings: fsi: ibm,i2cr-fsi-master: Reference common FSI controller
dt-bindings: fsi: Document the FSI controller common properties
dt-bindings: fsi: Document the IBM SBEFIFO engine
dt-bindings: fsi: p9-occ: Convert to json-schema
dt-bindings: fsi: Document the IBM SCOM engine
dt-bindings: fsi: fsi2spi: Document SPI controller child nodes
dt-bindings: interrupt-controller: convert fsl,ls-scfg-msi to yaml
dt-bindings: soc: fsl: Convert q(b)man-* to yaml format
dt-bindings: misc: fsl,qoriq-mc: convert to yaml format
dt-bindings: drop stale Anson Huang from maintainers
...
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Add compatible string for sama7d65. Like sam9x60 and sam9x7, it requires
to bind to "atmel,at91rm9200-spi".
Group these three under the same enum, sorted alphanumerically, and
remove previously added item.
Signed-off-by: Nicolas Ferre <[email protected]>
Acked-by: Rob Herring (Arm) <[email protected]>
Link: https://patch.msgid.link/[email protected]
Signed-off-by: Mark Brown <[email protected]>
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Emails to Anson Huang bounce:
Diagnostic-Code: smtp; 550 5.4.1 Recipient address rejected: Access denied.
Add IMX platform maintainers for bindings which would become orphaned.
Acked-by: Uwe Kleine-König <[email protected]>
Reviewed-by: Fabio Estevam <[email protected]>
Acked-by: Peng Fan <[email protected]>
Acked-by: Wolfram Sang <[email protected]> # for I2C
Signed-off-by: Krzysztof Kozlowski <[email protected]>
Acked-by: Mark Brown <[email protected]>
Acked-by: Jonathan Cameron <[email protected]> # for IIO
Acked-by: Andi Shyti <[email protected]>
Acked-by: Abel Vesa <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Rob Herring (Arm) <[email protected]>
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Add compatible string 'fsl,lx2160a-dspi' and allow fall back to
'fsl,ls2085a-dspi'.
Fix below CHECK_DTBS warning.
arch/arm64/boot/dts/freescale/fsl-lx2160a-bluebox3.dtb: spi@2100000: compatible: 'oneOf' conditional failed, one must be fixed:
['fsl,lx2160a-dspi', 'fsl,ls2085a-dspi'] is too long
Signed-off-by: Frank Li <[email protected]>
Link: https://patch.msgid.link/[email protected]
Signed-off-by: Mark Brown <[email protected]>
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Add dmas and dma-names properties because dspi support dma transfer.
Fix below warnings:
arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var1.dtb: spi@2120000: Unevaluated properties are not allowed ('dma-names', 'dmas', 'little-endian' were unexpected)
from schema $id: http://devicetree.org/schemas/spi/fsl,dspi.yaml#
Reviewed-by: Krzysztof Kozlowski <[email protected]>
Signed-off-by: Frank Li <[email protected]>
Reviewed-by: Vladimir Oltean <[email protected]>
Link: https://patch.msgid.link/[email protected]
Signed-off-by: Mark Brown <[email protected]>
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updated compatible property to include "thead,th1520-spi" for the
TH1520 SoC SPI Controller.
Signed-off-by: Kanak Shilledar <[email protected]>
Acked-by: Conor Dooley <[email protected]>
Link: https://patch.msgid.link/[email protected]
Signed-off-by: Mark Brown <[email protected]>
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Convert dt-binding spi-fsl-dspi.txt to yaml format.
Use part Vladimir Oltean's work at of
https://lore.kernel.org/linux-spi/[email protected]/
Additional changes during convert:
- compatible string "fsl,ls1028a-dspi" can be followed by
fsl,ls1021a-v1.0-dspi.
- Change "dspi0@4002c000" to "spi@4002c000" in example.
- Reorder properties in example.
- Use GIC include in example.
- Deprecated fsl,spi-cs-sck-delay and fsl,spi-sck-cs-delay by use common SPI
property.
- Use compatible string 'jedec,spi-nor' in example.
- Split peripheral part to fsl,dspi-peripheral-props.yaml.
- Remove 'interrupts' and 'pinctrl' from required list.
- Update 'bus-num' description.
- Update 'spi-num-chipselects' description by add "cs-gpios don't count
against this number".
- Remove 'big-endian' description.
Co-developed-by: Kuldeep Singh <[email protected]>
Signed-off-by: Kuldeep Singh <[email protected]>
Co-developed-by: Vladimir Oltean <[email protected]>
Signed-off-by: Vladimir Oltean <[email protected]>
Signed-off-by: Frank Li <[email protected]>
Reviewed-by: Vladimir Oltean <[email protected]>
Reviewed-by: Rob Herring (Arm) <[email protected]>
Link: https://patch.msgid.link/[email protected]
Signed-off-by: Mark Brown <[email protected]>
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Gather the STM32 DMA controllers bindings under ./dma/stm32/.
Then fix reference to old path in spi/st,stm32-spi.yaml: update the dmas
property description by referring to all STM32 DMA controllers bindings.
Acked-by: Rob Herring (Arm) <[email protected]>
Signed-off-by: Amelie Delaunay <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Vinod Koul <[email protected]>
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On the Amlogic A1, the SPI FC controller can require a power-domain to
operate, add it as optional.
Signed-off-by: Neil Armstrong <[email protected]>
Acked-by: Conor Dooley <[email protected]>
Link: https://msgid.link/r/20240605-topic-amlogic-upstream-bindings-fixes-power-domains-spifc-v1-1-380f29ba4a16@linaro.org
Signed-off-by: Mark Brown <[email protected]>
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Merge series from Prajna Rajendra Kumar <[email protected]>:
The Microchip PolarFire SoC SPI "hard" controller supports eight
chip selects. However, only one chip select is physically wired.
Therefore, use GPIO descriptors to configure additional chip select
lines.
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Merge series from Ji Sheng Teoh <[email protected]>:
The first patch adds optional reset control to support assertion and
deassertion of reset signal to properly bring the SPI device into an
operating condition.
The second patch documents the optional reset control into dt-bindings.
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IBM Power processors have a SPI controller that can be accessed
over FSI from a service processor. Document it.
Signed-off-by: Eddie James <[email protected]>
Reviewed-by: Krzysztof Kozlowski <[email protected]>
Link: https://msgid.link/r/[email protected]
Signed-off-by: Mark Brown <[email protected]>
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Convert the Broadcom BCM2835 SPI0 controller to newer DT
schema. Created DT schema based on the .txt file which had
`comaptible`, `reg`, `interrupts`, `clocks` as required
properties.
Added GPL-2.0 OR BSD-2-Clause License
Signed-off-by: Kanak Shilledar <[email protected]>
Reviewed-by: Conor Dooley <[email protected]>
Link: https://msgid.link/r/[email protected]
Signed-off-by: Mark Brown <[email protected]>
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The Marvell PXA SSP block is the same or similiar to the MMP2 variant.
The only difference in the binding is the PXA version supports DMA (and
that's probably a binding difference rather than an actual h/w
difference).
The old binding didn't belong under 'serial' as it is not a UART. The
SSP block also supports audio devices, so 'spi' is not a perfect fit
either. As the existing schema for MMP2 is there, just leave things
as-is.
The examples in the old text binding were pretty out of sync with
reality. 'clock-names' and 'ssp-id' aren't documented nor used.
Cc: Andy Shevchenko <[email protected]>
Signed-off-by: Rob Herring (Arm) <[email protected]>
Link: https://msgid.link/r/[email protected]
Signed-off-by: Mark Brown <[email protected]>
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The PolarFire SoC SPI "hard" controller supports eight CS lines, out of
which only one CS line is physically wired. The default value of
'num-cs' was never set and it did not didn't impose a maximum value.
To reflect this hardware limitation in the device tree, the binding
enforces that the 'num-cs' property cannot exceed 1 unless additional
CS lines are explicitly defined using GPIO descriptors.
Fixes: 2da187304e55 ("spi: add bindings for microchip mpfs spi")
Signed-off-by: Prajna Rajendra Kumar <[email protected]>
Link: https://msgid.link/r/[email protected]
Reviewed-by: Conor Dooley <[email protected]>
Signed-off-by: Mark Brown <[email protected]>
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Document the optional reset control to SPI.
Co-developed-by: Eng Lee Teh <[email protected]>
Signed-off-by: Eng Lee Teh <[email protected]>
Co-developed-by: Ley Foon Tan <[email protected]>
Signed-off-by: Ley Foon Tan <[email protected]>
Signed-off-by: Ji Sheng Teoh <[email protected]>
Reviewed-by: Krzysztof Kozlowski <[email protected]>
Link: https://msgid.link/r/[email protected]
Signed-off-by: Mark Brown <[email protected]>
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git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi
Pull spi updates from Mark Brown:
"The diffstat for this release is dominated by the new Airoha driver,
mainly as a result of this being a generally quite quiet release.
There were a couple of cleanups in the core but nothing substantial,
the updates here are almost all driver specific ones.
- Support for multi-word mode in the OMAP2 McSPI driver
- Overhaul of the PXA2xx driver, mostly API updates
- A number of DT binding conversions
- Support for Airoha NAND controllers, Cirrus Logic CS35L56, Mobileye
EYEQ5 and Renesas R8A779H0"
* tag 'spi-v6.10' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi: (87 commits)
spi: dw: Bail out early on unsupported target mode
spi: Remove unneded check for orig_nents
MAINTAINERS: repair file entry in AIROHA SPI SNFI DRIVER
spi: pxa2xx: Drop the stale entry in documentation TOC
spi: pxa2xx: Don't provide struct chip_data for others
spi: pxa2xx: Remove timeout field from struct chip_data
spi: pxa2xx: Remove DMA parameters from struct chip_data
spi: pxa2xx: Drop struct pxa2xx_spi_chip
spi: pxa2xx: Don't use "proxy" headers
spi: pxa2xx: Remove outdated documentation
spi: pxa2xx: Move contents of linux/spi/pxa2xx_spi.h to a local one
spi: pxa2xx: Provide num-cs for Sharp PDAs via device properties
spi: pxa2xx: Allow number of chip select pins to be read from property
spi: dt-bindings: ti,qspi: convert to dtschema
spi: bitbang: Add missing MODULE_DESCRIPTION()
spi: bitbang: Use NSEC_PER_*SEC rather than hard coding
spi: dw: Drop default number of CS setting
spi: dw: Convert dw_spi::num_cs to u32
spi: dw: Add a number of native CS auto-detection
spi: dw: Convert to using BITS_TO_BYTES() macro
...
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Convert txt binding of TI's qspi controller (found on their omap SoCs) to
dtschema to allow for validation.
The changes, w.r.t. the original txt binding, are:
- Introduce "clocks" and "clock-names" which was never mentioned.
- Reflect that "ti,hwmods" is deprecated and is not a "required"
property anymore.
- Introduce "num-cs" which allows for setting the number of chip
selects.
- Drop "qspi_ctrlmod".
Signed-off-by: Kousik Sanagavarapu <[email protected]>
Reviewed-by: Krzysztof Kozlowski <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Mark Brown <[email protected]>
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Introduce Airoha EN7581 SPI NAND controller binding
Reviewed-by: AngeloGioacchino Del Regno <[email protected]>
Reviewed-by: Conor Dooley <[email protected]>
Tested-by: Rajeev Kumar <[email protected]>
Signed-off-by: Lorenzo Bianconi <[email protected]>
Link: https://lore.kernel.org/r/f3377b323f00589e6b7ed7950c4840d18129238b.1714377864.git.lorenzo@kernel.org
Signed-off-by: Mark Brown <[email protected]>
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Convert txt binding of marvell armada 3700 SoC spi controller to dtschema
to allow for validation.
Signed-off-by: Kousik Sanagavarapu <[email protected]>
Reviewed-by: Conor Dooley <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Mark Brown <[email protected]>
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Document support for the Clock-Synchronized Serial Interface with FIFO
(MSIOF) in the Renesas R-Car V4M (R8A779H0) SoC.
Signed-off-by: Geert Uytterhoeven <[email protected]>
Acked-by: Conor Dooley <[email protected]>
Link: https://lore.kernel.org/r/68a4d8ad8638c1133e21d0eef87e8982ddea3dd8.1713279687.git.geert+renesas@glider.be
Signed-off-by: Mark Brown <[email protected]>
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Make cdns,fifo-depth devicetree property optional.
Value can be detected at runtime.
Upper SRAMPARTITION register bits are read-only. Procedure to find FIFO
depth is therefore to write 0xFFFFFFFF and read back to get amount of
writeable bits.
Signed-off-by: Théo Lebrun <[email protected]>
Link: https://msgid.link/r/[email protected]
Signed-off-by: Mark Brown <[email protected]>
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Add Mobileye EyeQ5 compatible.
Reviewed-by: Krzysztof Kozlowski <[email protected]>
Signed-off-by: Théo Lebrun <[email protected]>
Link: https://msgid.link/r/[email protected]
Signed-off-by: Mark Brown <[email protected]>
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Compatibles are ordered by date of addition.
Switch to (deterministic) alphabetical ordering.
Reviewed-by: Krzysztof Kozlowski <[email protected]>
Signed-off-by: Théo Lebrun <[email protected]>
Link: https://msgid.link/r/[email protected]
Signed-off-by: Mark Brown <[email protected]>
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access-controllers is an optional property that allows a peripheral to
refer to one or more domain access controller(s).
Description of this property is added to all peripheral binding files of
the peripheral under the STM32 firewall controller. It allows an accurate
representation of the hardware, where various peripherals are connected
to a firewall bus. The firewall can then check the peripheral accesses
before allowing its device to probe.
Signed-off-by: Gatien Chevallier <[email protected]>
Reviewed-by: Rob Herring <[email protected]>
Signed-off-by: Alexandre Torgue <[email protected]>
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There are SPI IPs that can be configured by the integrator with a
specific FIFO depth depending on the system's capabilities. For example,
the samsung USI SPI IP can be configured by the integrator with a TX/RX
FIFO from 8 byte to 256 bytes.
Introduce the ``fifo-depth`` property for such instances of IPs where the
same FIFO depth is used for both RX and TX. Introduce ``rx-fifo-depth``
and ``tx-fifo-depth`` properties for cases where the RX FIFO depth is
different from the TX FIFO depth.
Make the dedicated RX/TX properties dependent on each other and mutual
exclusive with the other.
Reviewed-by: Rob Herring <[email protected]>
Signed-off-by: Tudor Ambarus <[email protected]>
Reviewed-by: Conor Dooley <[email protected]>
Link: https://msgid.link/r/[email protected]
Signed-off-by: Mark Brown <[email protected]>
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Since the addition of the driver in 2009, the driver selects between DMA
and polling mode depending on the transfer length - DMA mode for
transfers bigger than the FIFO depth, polling mode otherwise. All
versions of the IP support polling mode, make the dma properties not
required.
Signed-off-by: Tudor Ambarus <[email protected]>
Link: https://msgid.link/r/[email protected]
Signed-off-by: Mark Brown <[email protected]>
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Remove microchip,sam9x60-spi compatible from the list as the driver used
has the compatible atmel,at91rm9200-spi and sam9x60 devices also use the
same compatible as fallback. So removing the microchip,sam9x60-spi
compatible from the list since it is not needed.
Signed-off-by: Varshini Rajendran <[email protected]>
Reviewed-by: Tudor Ambarus <[email protected]>
Link: https://msgid.link/r/[email protected]
Signed-off-by: Mark Brown <[email protected]>
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Add "google,gs101-spi" dedicated compatible for representing SPI of
Google GS101 SoC.
Reviewed-by: Sam Protsenko <[email protected]>
Reviewed-by: Krzysztof Kozlowski <[email protected]>
Reviewed-by: Peter Griffin <[email protected]>
Acked-by: Andi Shyti <[email protected]>
Signed-off-by: Tudor Ambarus <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Mark Brown <[email protected]>
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Document samsung,exynos850-spi compatible which will be used on
Exynos850 SoC. Exynos850 doesn't have ioclk, so only two clocks are
needed (bus clock and functional SPI clock).
Signed-off-by: Sam Protsenko <[email protected]>
Reviewed-by: Tudor Ambarus <[email protected]>
Reviewed-by: Krzysztof Kozlowski <[email protected]>
Link: https://msgid.link/r/[email protected]
Signed-off-by: Mark Brown <[email protected]>
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Add i.MX93/95 flexspi compatible strings, which are compatible with
i.MX8MM
Signed-off-by: Peng Fan <[email protected]>
Acked-by: Han Xu <[email protected]>
Acked-by: Conor Dooley <[email protected]>
Link: https://msgid.link/r/[email protected]
Signed-off-by: Mark Brown <[email protected]>
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Add i.MX95 LPSPI compatible string, same as i.MX93 compatible with
i.MX7ULP
Signed-off-by: Peng Fan <[email protected]>
Acked-by: Conor Dooley <[email protected]>
Link: https://msgid.link/r/[email protected]
Signed-off-by: Mark Brown <[email protected]>
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Add st,stm32mp25-spi compatible in dt-bindings. STM32MP25 spi is similar
to the STM32H7 except for the following two points:
- Burst should not be enabled with the new DMA used on STM32MP25.
- STM32MP25 SPI8 has a limited feature set, it can only send words of
8 or 16 bits and with a maximum words number of 1024.
Signed-off-by: Valentin Caron <[email protected]>
Signed-off-by: Alain Volmat <[email protected]>
Reviewed-by: Fabrice Gasnier <[email protected]>
Acked-by: Conor Dooley <[email protected]>
Link: https://msgid.link/r/[email protected]
Signed-off-by: Mark Brown <[email protected]>
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Remove Intel Thunder Bay specific code as the product got cancelled and
there are no end customers or users.
Signed-off-by: Nandhini Srikandan <[email protected]>
Acked-by: Krzysztof Kozlowski <[email protected]>
Link: https://msgid.link/r/[email protected]
Signed-off-by: Mark Brown <[email protected]>
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Merge series from David Lechner <[email protected]>:
We are working towards adding support for the offload feature[1] of the
AXI SPI Engine IP core. Before we can do that, we want to make some
general fixes and improvements to the driver. In order to avoid a giant
series with 35+ patches, we are splitting this up into a few smaller
series.
This first series mostly doing some housekeeping:
* Convert device tree bindings to yaml.
* Add a MAINTAINERS entry.
* Clean up probe and remove using devm.
* Separate message state from driver state.
* Add support for cs_off and variable word size.
Once this series is applied, we will follow up with a second series of
general improvements, and then finally a 3rd series that implements the
offload support. The offload support will also involve the IIO
subsystem (a new IIO driver will depend on the new SPI offload feature),
so I'm mentioning this now in case we want to do anything ahead of time
to prepare for that (e.g. putting all of these changes on a separate
branch).
[1]: https://wiki.analog.com/resources/fpga/peripherals/spi_engine/offload
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This converts the axi-spi-engine binding to yaml.
There are a few minor fixes in the conversion:
* Added maintainers.
* Added descriptions for the clocks.
* Fixed the double "@" in the example.
* Added a comma between the clocks in the example.
Signed-off-by: David Lechner <[email protected]>
Reviewed-by: Rob Herring <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Mark Brown <[email protected]>
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The RSPI block on the RZ/Five SoC is identical to one found on the RZ/G2UL
SoC. "renesas,r9a07g043-rspi" compatible string will be used on the
RZ/Five SoC so to make this clear and to keep this file consistent, update
the comment to include RZ/Five SoC.
No driver changes are required as generic compatible string
"renesas,rspi-rz" will be used as a fallback on RZ/Five SoC.
Signed-off-by: Lad Prabhakar <[email protected]>
Reviewed-by: Geert Uytterhoeven <[email protected]>
Acked-by: Conor Dooley <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Mark Brown <[email protected]>
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The STM32F7 SPI peripheral is nearly identical to the STM32F4, with the
only significant differences being support for a wider range of word
sizes and the addition of 32-bit transmit and receive FIFOs.
Signed-off-by: Ben Wolsieffer <[email protected]>
Acked-by: Conor Dooley <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Mark Brown <[email protected]>
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One small fix that didn't seem worth sending before the merge window.
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The CSI IP found inside the Renesas RZ/V2M SoC can also work
in SPI target mode.
When working in target mode, the IP will make use of the SS
(Slave Selection) pin, with "low" as default active level.
The active level of SS can be changed to "high" upon setting
property "spi-cs-high" to true.
By default, the SS will be used in target mode, unless property
"renesas,csi-no-ss" is set to true, in which case data will be
shifted in and out purely based on clock activity, and the
logic level of the SS pin will be completely ignored.
Signed-off-by: Fabrizio Castro <[email protected]>
Reviewed-by: Rob Herring <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Mark Brown <[email protected]>
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