aboutsummaryrefslogtreecommitdiff
path: root/Documentation/devicetree/bindings/pci
AgeCommit message (Collapse)AuthorFilesLines
2024-09-19Merge branch 'pci/controller/xilinx'Bjorn Helgaas2-2/+41
- Fix off-by-one error in INTx IRQ handler that caused INTx interrupts to be lost or delivered as the wrong interrupt (Sean Anderson) - Rate-limit misc interrupt messages (Sean Anderson) - Turn off the clock on probe failure and device removal (Sean Anderson) - Add DT binding and driver support for enabling/disabling PHYs (Sean Anderson) - Add PCIe phy bindings for the ZCU102 (Sean Anderson) - Add support for Xilinx QDMA Soft IP PCIe Root Port Bridge to DT binding and xilinx-dma-pl driver (Thippeswamy Havalige) * pci/controller/xilinx: PCI: xilinx-xdma: Add Xilinx QDMA Root Port driver dt-bindings: PCI: xilinx-xdma: Add schemas for Xilinx QDMA PCIe Root Port Bridge arm64: zynqmp: Add PCIe phys property for ZCU102 PCI: xilinx-nwl: Add PHY support dt-bindings: pci: xilinx-nwl: Add phys property PCI: xilinx-nwl: Clean up clock on probe failure/removal PCI: xilinx-nwl: Rate-limit misc interrupt messages PCI: xilinx-nwl: Fix register misspelling PCI: xilinx-nwl: Fix off-by-one in INTx IRQ handler
2024-09-19Merge branch 'pci/controller/rcar-gen4'Bjorn Helgaas2-0/+2
- Make the read-only const array 'check_addr' static (Colin Ian King) - Add R-Car V4M (R8A779H0) PCIe host and endpoint to DT binding (Yoshihiro Shimoda) * pci/controller/rcar-gen4: dt-bindings: PCI: rcar-gen4-pci-ep: Add R-Car V4M compatible dt-bindings: PCI: rcar-gen4-pci-host: Add R-Car V4M compatible PCI: rcar-gen4: Make read-only const array check_addr static
2024-09-19Merge branch 'pci/controller/qcom'Bjorn Helgaas4-7/+22
- Drop endpoint redundant masking of global IRQ events (Manivannan Sadhasivam) - Clarify unknown global IRQ message and only log it once to avoid a flood (Manivannan Sadhasivam) - Add Manivannan Sadhasivam as maintainer of qcom endpoint driver (Manivannan Sadhasivam) - Add 'linux,pci-domain' property to endpoint DT binding (Manivannan Sadhasivam) - Assign PCI domain number for endpoint controllers (Manivannan Sadhasivam) - Add 'qcom_pcie_ep' and the PCI domain number to IRQ names for endpoint controller (Manivannan Sadhasivam) - Add global SPI interrupt for PCIe link events to DT binding (Manivannan Sadhasivam) - Add global RC interrupt handler to handle 'Link up' events and automatically enumerate hot-added devices (Manivannan Sadhasivam) - Avoid mirroring of DBI and iATU register space so it doesn't overlap BAR MMIO space (Prudhvi Yarlagadda) - Enable controller resources like PHY only after PERST# is deasserted to partially avoid the problem that the endpoint SoC crashes when accessing things when Refclk is absent (Manivannan Sadhasivam) - Rename dw_pcie.link_gen to max_link_speed to avoid ambiguity (Manivannan Sadhasivam) - Cache maximum link speed value in dw_pcie.max_link_speed for use by vendor drivers (Manivannan Sadhasivam) - Add 16.0 GT/s equalization and RX lane margining settings (Shashank Babu Chinta Venkata) - Pass domain number to pci_bus_release_domain_nr() explicitly to avoid a NULL pointer dereference (Manivannan Sadhasivam) * pci/controller/qcom: PCI: Pass domain number to pci_bus_release_domain_nr() explicitly PCI: qcom: Add RX lane margining settings for 16.0 GT/s PCI: qcom: Add equalization settings for 16.0 GT/s PCI: dwc: Always cache the maximum link speed value in dw_pcie::max_link_speed PCI: dwc: Rename 'dw_pcie::link_gen' to 'dw_pcie::max_link_speed' PCI: qcom-ep: Enable controller resources like PHY only after refclk is available PCI: qcom: Disable mirroring of DBI and iATU register space in BAR region PCI: qcom: Enumerate endpoints based on Link up event in 'global_irq' interrupt dt-bindings: PCI: qcom,pcie-sm8450: Add 'global' interrupt PCI: qcom-ep: Modify 'global_irq' and 'perst_irq' IRQ device names PCI: endpoint: Assign PCI domain number for endpoint controllers dt-bindings: PCI: pci-ep: Document 'linux,pci-domain' property dt-bindings: PCI: pci-ep: Update Maintainers PCI: qcom-ep: Reword the error message for receiving unknown global IRQ event PCI: qcom-ep: Drop the redundant masking of global IRQ events
2024-09-19Merge branch 'pci/controller/mediatek-gen3'Bjorn Helgaas1-5/+63
- Add per-SoC struct mtk_gen3_pcie_pdata to support multiple SoC types (Lorenzo Bianconi) - Use reset_bulk APIs to manage PHY reset lines (Lorenzo Bianconi) - Add DT and driver support for Airoha EN7581 PCIe controller (Lorenzo Bianconi) * pci/controller/mediatek-gen3: PCI: mediatek-gen3: Add Airoha EN7581 support PCI: mediatek-gen3: Rely on reset_bulk APIs for PHY reset lines PCI: mediatek-gen3: Add mtk_gen3_pcie_pdata data structure dt-bindings: PCI: mediatek-gen3: Add support for Airoha EN7581
2024-09-19Merge branch 'pci/controller/j721e'Bjorn Helgaas1-0/+10
- Add DT "ti,syscon-acspcie-proxy-ctrl" and driver support to enable the ACSPCIE module to drive Refclk for the Endpoint (Siddharth Vadapalli) - Extract the cadence link setup from cdns_pcie_host_setup() so link setup can be done separately during resume (Thomas Richard) - Use dev_err_probe() to simplify j721e probe (Thomas Richard) - Add T_PERST_CLK_US definition for the mandatory delay between Refclk becoming stable and PERST# being deasserted (Thomas Richard) - Add j721e suspend and resume support (Théo Lebrun) * pci/controller/j721e: PCI: j721e: Add suspend and resume support PCI: j721e: Use T_PERST_CLK_US macro PCI: Add T_PERST_CLK_US macro PCI: j721e: Add reset GPIO to struct j721e_pcie PCI: j721e: Use dev_err_probe() in the probe() function PCI: cadence: Set cdns_pcie_host_init() global PCI: cadence: Extract link setup sequence from cdns_pcie_host_setup() PCI: j721e: Enable ACSPCIE Refclk if "ti,syscon-acspcie-proxy-ctrl" exists dt-bindings: PCI: ti,j721e-pci-host: Add ACSPCIE proxy control property
2024-09-19Merge branch 'pci/controller/imx6'Bjorn Helgaas1-0/+16
- Fix a code restructuring error that caused i.MX8MM and i.MX8MP Endpoints to fail to establish link (Richard Zhu) - Fix i.MX8MP Endpoint occasional failure to trigger MSI by enforcing outbound alignment requirement (Richard Zhu) - Call phy_power_off() in the .probe() error path (Frank Li) - Rename internal names from imx6_* to imx_* since i.MX7/8/9 are also supported (Frank Li) - Manage Refclk by using SoC-specific callbacks instead of switch statements (Frank Li) - Manage core reset by using SoC-specific callbacks instead of switch statements (Frank Li) - Expand comments for erratum ERR010728 workaround (Frank Li) - Use generic PHY APIs to configure mode, speed, and submode, which is harmless for devices that implement their own internal PHY management and don't set the generic imx_pcie->phy (Frank Li) - Add i.MX8Q (i.MX8QM, i.MX8QXP, and i.MX8DXL) DT binding and driver Root Complex support (Richard Zhu) * pci/controller/imx6: PCI: imx6: Add i.MX8Q PCIe Root Complex (RC) support PCI: imx6: Call common PHY API to set mode, speed, and submode dt-bindings: PCI: imx6q-pcie: Add i.MX8Q PCIe compatible string PCI: imx6: Consolidate redundant if-checks PCI: imx6: Improve comment for workaround ERR010728 PCI: imx6: Simplify switch-case logic by involve core_reset callback PCI: imx6: Introduce SoC specific callbacks for controlling REFCLK PCI: imx6: Rename imx6_* with imx_* PCI: imx6: Fix missing call to phy_power_off() in error handling PCI: imx6: Fix i.MX8MP PCIe EP's occasional failure to trigger MSI PCI: imx6: Fix establish link failure in EP mode for i.MX8MM and i.MX8MP
2024-09-19Merge branch 'pci/controller/brcmstb'Bjorn Helgaas1-6/+34
- Change DT binding maintainer to Jim Quinlan (Jim Quinlan) - Add DT binding maxItems for reset controllers (Jim Quinlan) - Refactor .probe() error handling (Jim Quinlan) - Use the 'bridge' reset method if described in the DT (Jim Quinlan) - Use the 'swinit' reset method if described in the DT (Jim Quinlan) - Add SoC-specific HARD_DEBUG, INTR2_CPU_BASE register offsets (Jim Quinlan) - Drop unused RGR1_SW_INIT_1_INIT_MASK, RGR1_SW_INIT_1_INIT_SHIFT offsets (Jim Quinlan) - Add 'has_phy' so the existence of a 'rescal' reset controller doesn't imply software control of it (Jim Quinlan) - Add support for many inbound DMA windows (Jim Quinlan) - Check return values of all reset_control_*() calls (Jim Quinlan) - Rename SoC 'type' to 'soc_base' express the fact that SoCs come in families of multiple similar devices (Jim Quinlan) - Add Broadcom 7712 DT description and driver support (Jim Quinlan) - Sort enums, pcie_offsets[], pcie_cfg_data, .compatible strings for maintainability (Bjorn Helgaas) * pci/controller/brcmstb: PCI: brcmstb: Sort enums, pcie_offsets[], pcie_cfg_data, .compatible strings PCI: brcmstb: Enable 7712 SoCs PCI: brcmstb: Change field name from 'type' to 'soc_base' PCI: brcmstb: Check return value of all reset_control_* calls PCI: brcmstb: Refactor for chips with many regular inbound windows PCI: brcmstb: Don't conflate the reset rescal with PHY ctrl PCI: brcmstb: Remove two unused constants from driver PCI: brcmstb: PCI: brcmstb: Make HARD_DEBUG, INTR2_CPU_BASE offsets SoC-specific PCI: brcmstb: Use swinit reset if available PCI: brcmstb: Use bridge reset if available PCI: brcmstb: Use common error handling code in brcm_pcie_probe() dt-bindings: PCI: brcm,stb-pcie: Add 7712 SoC description dt-bindings: PCI: brcm,stb-pcie: Use maxItems for reset controllers dt-bindings: PCI: brcm,stb-pcie: Change brcmstb maintainer and cleanup
2024-09-13dt-bindings: PCI: qcom: Allow 'vddpe-3v3-supply' againJohan Hovold4-6/+6
Commit 756485bfbb85 ("dt-bindings: PCI: qcom,pcie-sc7280: Move SC7280 to dedicated schema") incorrectly removed 'vddpe-3v3-supply' from the bindings, which results in DT checker warnings like: arch/arm64/boot/dts/qcom/msm8996-sony-xperia-tone-dora.dtb: pcie@600000: Unevaluated properties are not allowed ('vddpe-3v3-supply' was unexpected) from schema $id: http://devicetree.org/schemas/pci/qcom,pcie.yaml# Note that this property has been part of the Qualcomm PCIe bindings since 2018 and would need to be deprecated rather than simply removed if there is a desire to replace it with 'vpcie3v3' which is used for some non-Qualcomm controllers. Link: https://lore.kernel.org/lkml/[email protected]/ Fixes: 756485bfbb85 ("dt-bindings: PCI: qcom,pcie-sc7280: Move SC7280 to dedicated schema") Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Johan Hovold <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Krzysztof Kozlowski <[email protected]> Reviewed-by: Manivannan Sadhasivam <[email protected]>
2024-09-13dt-bindings: PCI: imx6q-pcie: Add reg-name "dbi2" and "atu" for i.MX8M PCIe ↵Richard Zhu1-4/+9
Endpoint Add reg-name: "dbi2", "atu" for i.MX8M PCIe Endpoint. For i.MX8M PCIe EP, the dbi2 and atu addresses are pre-defined in the driver. This method is not good. In commit b7d67c6130ee ("PCI: imx6: Add iMX95 Endpoint (EP) support"), Frank suggests to fetch the dbi2 and atu from DT directly. This commit is preparation to do that for i.MX8M PCIe EP. These changes wouldn't break driver function. When "dbi2" and "atu" properties are present, i.MX PCIe driver would fetch the according base addresses from DT directly. If only two reg properties are provided, i.MX PCIe driver would fall back to the old method. Link: https://lore.kernel.org/linux-pci/[email protected] Signed-off-by: Richard Zhu <[email protected]> Signed-off-by: Krzysztof Wilczyński <[email protected]> Reviewed-by: Frank Li <[email protected]> Reviewed-by: Rob Herring (Arm) <[email protected]>
2024-09-13dt-bindings: PCI: altera: msi: Convert to YAMLMatthew Gerlach2-27/+65
Convert the devicetree bindings for the Altera PCIe MSI controller from text to YAML. Link: https://lore.kernel.org/linux-pci/[email protected] Signed-off-by: Matthew Gerlach <[email protected]> [kwilczynski: remove unused msi0 label] Signed-off-by: Krzysztof Wilczyński <[email protected]> Reviewed-by: Conor Dooley <[email protected]>
2024-09-09dt-bindings: PCI: imx6q-pcie: Add i.MX8Q PCIe compatible stringRichard Zhu1-0/+16
Add i.MX8Q PCIe "fsl,imx8q-pcie" compatible strings. clock-names align DesignWare Cores (DWC) common naming convension. Link: https://lore.kernel.org/linux-pci/[email protected] Signed-off-by: Richard Zhu <[email protected]> Signed-off-by: Frank Li <[email protected]> [kwilczynski: commit log] Signed-off-by: Krzysztof Wilczyński <[email protected]> Reviewed-by: Manivannan Sadhasivam <[email protected]> Reviewed-by: Rob Herring (Arm) <[email protected]> Acked-by: Conor Dooley <[email protected]> Acked-by: Manivannan Sadhasivam <[email protected]>
2024-09-04dt-bindings: PCI: altera: Convert to YAMLMatthew Gerlach2-50/+114
Convert the devicetree bindings for the Altera Root Port PCIe controller from text to YAML. While at it, update the entries in the interrupt-map field to have the correct number of address cells for the interrupt parent. Link: https://lore.kernel.org/linux-pci/[email protected] Signed-off-by: Matthew Gerlach <[email protected]> [kwilczynski: commit log] Signed-off-by: Krzysztof Wilczyński <[email protected]> Reviewed-by: Conor Dooley <[email protected]>
2024-09-04dt-bindings: PCI: qcom,pcie-sc7280: Update bindings adding eight interruptsRayyan Ansari1-4/+20
Previous commit to this bindings, commit 756485bfbb85 ("dt-bindings: PCI: qcom,pcie-sc7280: Move SC7280 to dedicated schema"), updated the bindings to specify one interrupt only, as the devicetree at that time did not describe the hardware fully. The devicetree for SC7280 now specifies eight interrupts, following the commit b8ba66b40da3 ("arm64: dts: qcom: sc7280: Add additional MSI interrupts"). Thus, update the bindings to reflect this. Link: https://lore.kernel.org/linux-pci/[email protected] Signed-off-by: Rayyan Ansari <[email protected]> [kwilczynski: commit log] Signed-off-by: Krzysztof Wilczyński <[email protected]> Reviewed-by: Krzysztof Kozlowski <[email protected]> Reviewed-by: Manivannan Sadhasivam <[email protected]>
2024-09-04dt-bindings: PCI: layerscape-pci: Change property 'fsl,pcie-scfg' typeFrank Li1-1/+6
The fsl,pcie-scfg requires an argument when there are more than one PCIe instances. Thus, change it to the phandle-array type and use items to describe what each field means. This also fixes the following warning: arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dtb: pcie@3400000: fsl,pcie-scfg:0: [22, 0] is too long from schema $id: http://devicetree.org/schemas/pci/fsl,layerscape-pcie.yaml# Link: https://lore.kernel.org/linux-pci/[email protected] Signed-off-by: Frank Li <[email protected]> [kwilczynski: commit log] Signed-off-by: Krzysztof Wilczyński <[email protected]> Reviewed-by: Rob Herring <[email protected]>
2024-09-04dt-bindings: PCI: layerscape-pci: Add deprecated property 'num-viewport'Frank Li1-0/+8
Copy the 'num-viewport' property from snps,dw-pcie-common.yaml to fsl,layerscape-pcie.yaml to address the following warning: /arch/arm64/boot/dts/freescale/fsl-ls1012a-frwy.dtb: pcie@3400000: Unevaluated properties are not allowed ('num-viewport' was unexpected) This is necessary due to historical reasons where fsl,layerscape-pcie.yaml does not directly reference snps,dw-pcie-common.yaml. Link: https://lore.kernel.org/linux-pci/[email protected] Signed-off-by: Frank Li <[email protected]> [kwilczynski: commit log] Signed-off-by: Krzysztof Wilczyński <[email protected]> Acked-by: Rob Herring (Arm) <[email protected]>
2024-09-04dt-bindings: PCI: layerscape-pci: Replace fsl,lx2160a-pcie with ↵Frank Li1-12/+14
fsl,lx2160ar2-pcie The fsl,lx2160a-pcie compatible is used for mobivel according to the Documentation/devicetree/bindings/pci/layerscape-pcie-gen4.txt file. Whereas the fsl,layerscape-pcie is used for DesignWare PCIe controller binding. So change it to fsl,lx2160ar2-pcie and allow a fall back to fsl,ls2088a-pcie. While at it, sort compatible string. Fixes: 24cd7ecb3886 ("dt-bindings: PCI: layerscape-pci: Convert to YAML format") Link: https://lore.kernel.org/linux-pci/[email protected] Signed-off-by: Frank Li <[email protected]> [kwilczynski: commit log] Signed-off-by: Krzysztof Wilczyński <[email protected]> Reviewed-by: Rob Herring (Arm) <[email protected]>
2024-09-04dt-bindings: PCI: socionext,uniphier-pcie-ep: Add top-level constraintsKrzysztof Kozlowski1-2/+6
Properties with variable number of items per each device are expected to have widest constraints in top-level "properties:" block and further customized (narrowed) in "if:then:". Add missing top-level constraints for clock-names and reset-names. Link: https://lore.kernel.org/linux-pci/[email protected] Signed-off-by: Krzysztof Kozlowski <[email protected]> Signed-off-by: Krzysztof Wilczyński <[email protected]> Reviewed-by: Kunihiko Hayashi <[email protected]> Reviewed-by: Rob Herring (Arm) <[email protected]>
2024-09-04dt-bindings: PCI: renesas,pci-rcar-gen2: Add top-level constraintsKrzysztof Kozlowski1-2/+6
Properties with variable number of items per each device are expected to have widest constraints in top-level "properties:" block and further customized (narrowed) in "if:then:". Add missing top-level constraints for clocks and clock-names. Link: https://lore.kernel.org/linux-pci/[email protected] Signed-off-by: Krzysztof Kozlowski <[email protected]> Signed-off-by: Krzysztof Wilczyński <[email protected]> Reviewed-by: Rob Herring (Arm) <[email protected]>
2024-09-04dt-bindings: PCI: hisilicon,kirin-pcie: Add top-level constraintsKrzysztof Kozlowski1-1/+2
Properties with variable number of items per each device are expected to have widest constraints in top-level "properties:" block and further customized (narrowed) in "if:then:". Add missing top-level constraints for clock-names and reset-names. Link: https://lore.kernel.org/linux-pci/[email protected] Signed-off-by: Krzysztof Kozlowski <[email protected]> Signed-off-by: Krzysztof Wilczyński <[email protected]> Reviewed-by: Rob Herring (Arm) <[email protected]>
2024-09-04dt-bindings: PCI: brcm,stb-pcie: Add 7712 SoC descriptionJim Quinlan1-2/+26
Add description for the 7712 SoC, a Broadcom STB sibling chip of the Raspberry Pi 5. The 7712 uses three reset controllers: rescal, for PHY reset calibration; bridge, for the bridge between the PCIe bus and the memory bus; and swinit, which is a "soft" initialization of the PCIe HW. Link: https://lore.kernel.org/linux-pci/[email protected] Signed-off-by: Jim Quinlan <[email protected]> [kwilczynski: commit log] Signed-off-by: Krzysztof Wilczyński <[email protected]> Reviewed-by: Florian Fainelli <[email protected]> Reviewed-by: Krzysztof Kozlowski <[email protected]> Reviewed-by: Manivannan Sadhasivam <[email protected]>
2024-09-04dt-bindings: PCI: brcm,stb-pcie: Use maxItems for reset controllersJim Quinlan1-4/+8
Provide the maxItem property for the reset controllers and drop their superfluous descriptions. Link: https://lore.kernel.org/linux-pci/[email protected] Signed-off-by: Jim Quinlan <[email protected]> [kwilczynski: commit log] Signed-off-by: Krzysztof Wilczyński <[email protected]> Reviewed-by: Florian Fainelli <[email protected]> Reviewed-by: Krzysztof Kozlowski <[email protected]>
2024-09-04dt-bindings: PCI: brcm,stb-pcie: Change brcmstb maintainer and cleanupJim Quinlan1-3/+3
Change maintainer: Nicolas has not been active for a while. It also makes sense for a Broadcom employee to be the maintainer as many of the details are privy to Broadcom. Also, alphabetize the compatible strings. Link: https://lore.kernel.org/linux-pci/[email protected] Signed-off-by: Jim Quinlan <[email protected]> [kwilczynski: commit log] Signed-off-by: Krzysztof Wilczyński <[email protected]> Reviewed-by: Florian Fainelli <[email protected]> Reviewed-by: Krzysztof Kozlowski <[email protected]>
2024-09-03dt-bindings: PCI: rcar-gen4-pci-ep: Add R-Car V4M compatibleYoshihiro Shimoda1-0/+1
Document bindings for R-Car V4M (R8A779H0) PCIe endpoint module. Link: https://lore.kernel.org/linux-pci/[email protected] Signed-off-by: Yoshihiro Shimoda <[email protected]> Signed-off-by: Krzysztof Wilczyński <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Geert Uytterhoeven <[email protected]> Acked-by: Krzysztof Kozlowski <[email protected]>
2024-09-03dt-bindings: PCI: rcar-gen4-pci-host: Add R-Car V4M compatibleYoshihiro Shimoda1-0/+1
Document bindings for R-Car V4M (R8A779H0) PCIe host module. Link: https://lore.kernel.org/linux-pci/[email protected] Signed-off-by: Yoshihiro Shimoda <[email protected]> Signed-off-by: Krzysztof Wilczyński <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Geert Uytterhoeven <[email protected]> Acked-by: Krzysztof Kozlowski <[email protected]>
2024-09-03dt-bindings: PCI: mediatek-gen3: Add support for Airoha EN7581Lorenzo Bianconi1-5/+63
Introduce Airoha EN7581 entry in mediatek-gen3 PCIe controller binding. Link: https://lore.kernel.org/linux-pci/138d65a140c3dcf2a6aefecc33ba6ba3ca300a23.1720022580.git.lorenzo@kernel.org Signed-off-by: Lorenzo Bianconi <[email protected]> Signed-off-by: Krzysztof Wilczyński <[email protected]> Reviewed-by: AngeloGioacchino Del Regno <[email protected]> Reviewed-by: Conor Dooley <[email protected]> Acked-by: Jianjun Wang <[email protected]>
2024-09-01dt-bindings: PCI: qcom,pcie-sm8450: Add 'global' interruptManivannan Sadhasivam2-6/+8
Qcom PCIe RC controllers are capable of generating 'global' SPI interrupt to the host CPU. This interrupt can be used by the device driver to identify events such as PCIe link specific events, safety events, etc... Hence, document it in the binding along with the existing MSI interrupts. Though adding a new interrupt will break the ABI, it is required to accurately describe the hardware. Link: https://lore.kernel.org/linux-pci/[email protected] Signed-off-by: Manivannan Sadhasivam <[email protected]> Signed-off-by: Krzysztof Wilczyński <[email protected]> Reviewed-by: Rob Herring (Arm) <[email protected]>
2024-09-01dt-bindings: PCI: pci-ep: Document 'linux,pci-domain' propertyManivannan Sadhasivam2-0/+12
'linux,pci-domain' property provides the PCI domain number for the PCI endpoint controllers in a SoC. If this property is not present, then an unstable (across boots) unique number will be assigned. Devicetrees can specify the domain number based on the actual hardware instance of the PCI endpoint controllers in the SoC. Link: https://lore.kernel.org/linux-pci/[email protected] Signed-off-by: Manivannan Sadhasivam <[email protected]> Signed-off-by: Krzysztof Wilczyński <[email protected]> Reviewed-by: Rob Herring (Arm) <[email protected]>
2024-09-01dt-bindings: PCI: pci-ep: Update MaintainersManivannan Sadhasivam1-1/+2
Kishon's TI email ID is not active anymore, so use his kernel.org ID. Also, since I've been maintaining the PCI endpoint framework, I'm willing to maintain the DT binding as well. So add myself as the co-maintainer. Link: https://lore.kernel.org/linux-pci/[email protected] Signed-off-by: Manivannan Sadhasivam <[email protected]> [kwilczynski: commit log] Signed-off-by: Krzysztof Wilczyński <[email protected]> Reviewed-by: Frank Li <[email protected]> Acked-by: Rob Herring (Arm) <[email protected]>
2024-08-31dt-bindings: PCI: ti,j721e-pci-host: Add ACSPCIE proxy control propertySiddharth Vadapalli1-0/+10
Add the "ti,syscon-acspcie-proxy-ctrl" device-tree property which is used to obtain a reference to the ACSPCIE Proxy Control register along with the details of the PAD IO Buffer output enable bits. The ACSPCIE Proxy Control register is used to drive the reference clock for the PCIe Endpoint device via the PAD IO Buffers of the ACSPCIE module. The ACSPCIE module can be used as an alternative to either an on-board clock generator or an external clock generator for providing the reference clock to the PCIe Endpoint device. Link: https://lore.kernel.org/linux-pci/[email protected] Signed-off-by: Siddharth Vadapalli <[email protected]> Signed-off-by: Krzysztof Wilczyński <[email protected]> Reviewed-by: Manivannan Sadhasivam <[email protected]> Acked-by: Krzysztof Kozlowski <[email protected]>
2024-08-31dt-bindings: PCI: xilinx-xdma: Add schemas for Xilinx QDMA PCIe Root Port BridgeThippeswamy Havalige1-2/+34
Add YAML devicetree schemas for Xilinx QDMA Soft IP PCIe Root Port Bridge version 3.0. Link: https://lore.kernel.org/linux-pci/[email protected] Signed-off-by: Thippeswamy Havalige <[email protected]> Signed-off-by: Krzysztof Wilczyński <[email protected]> Acked-by: Conor Dooley <[email protected]>
2024-08-22dt-bindings: pci: xilinx-nwl: Add phys propertySean Anderson1-0/+7
Add phys properties so Linux can power-on/configure the GTR transceivers (xlnx,zynqmp-psgtr-v1.1). Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Sean Anderson <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Rob Herring (Arm) <[email protected]>
2024-08-09dt-bindings: PCI: host-generic-pci: Drop minItems and maxItems of rangesFrank Li1-2/+0
The ranges description states that "at least one non-prefetchable memory and one or both of prefetchable memory and IO space may also be provided." However, it should not limit the maximum number of ranges to 3. Freescale LS1028 and iMX95 use more than 3 ranges because the space splits some discontinuous prefetchable and non-prefetchable segments. Drop minItems and maxItems. The number of entries will be limited to 32 in pci-bus-common.yaml in dtschema, which should be sufficient. Fixes this CHECK_DTBS warning: arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dtb: pcie@1f0000000: ranges: [[2181038080, 1, 4160749568, 1, 4160749568, 0, 1441792], [3254779904, 1, 4162191360, 1, 4162191360, 0, 458752], [2181038080, 1, 4162650112, 1, 4162650112, 0, 131072], [3254779904, 1, 4162781184, 1, 4162781184, 0, 131072], [2181038080, 1, 4162912256, 1, 4162912256, 0, 131072], [3254779904, 1, 4163043328, 1, 4163043328, 0, 131072], [2181038080, 1, 4227858432, 1, 4227858432, 0, 4194304]] is too long Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Frank Li <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Rob Herring (Arm) <[email protected]>
2024-07-19Merge branch 'pci/controller/qcom'Bjorn Helgaas1-2/+62
- Use devm_clk_bulk_get_all() to get all the clocks from DT to avoid writing out all the clock names (Manivannan Sadhasivam) - Add DT binding and driver support for the SA8775P SoC (Mrinmay Sarkar) - Refactor dw_pcie_edma_find_chip() to enable adding support for Hyper DMA (HDMA) (Manivannan Sadhasivam) - Enable drivers to supply the eDMA channel count since some can't auto detect this (Manivannan Sadhasivam) - Add HDMA support for the SA8775P SoC (Mrinmay Sarkar) - Override the SA8775P NO_SNOOP default to avoid possible memory corruption (Mrinmay Sarkar) - Make sure resources are disabled during PERST# assertion, even if the link is already disabled (Manivannan Sadhasivam) - Vote for the CPU-PCIe ICC (interconnect) path to ensure it stays active even if other drivers don't vote for it (Krishna chaitanya chundru) - Add Operating Performance Points (OPP) to scale performance state based on aggregate link bandwidth to improve SoC power efficiency (Krishna chaitanya chundru) - Return failure instead of success if dev_pm_opp_find_freq_floor() fails (Dan Carpenter) - Avoid an error pointer dereference if dev_pm_opp_find_freq_exact() fails (Dan Carpenter) - Prevent use of uninitialized data in qcom_pcie_suspend_noirq() (Dan Carpenter) * pci/controller/qcom: PCI: qcom: Prevent use of uninitialized data in qcom_pcie_suspend_noirq() PCI: qcom: Prevent potential error pointer dereference PCI: qcom: Fix missing error code in qcom_pcie_probe() PCI: qcom: Add OPP support to scale performance PCI: Bring the PCIe speed to MBps logic to new pcie_dev_speed_mbps() PCI: qcom: Add ICC bandwidth vote for CPU to PCIe path PCI: qcom-ep: Disable resources unconditionally during PERST# assert PCI: qcom-ep: Override NO_SNOOP attribute for SA8775P EP PCI: qcom: Override NO_SNOOP attribute for SA8775P RC PCI: epf-mhi: Enable HDMA for SA8775P SoC PCI: qcom-ep: Add HDMA support for SA8775P SoC PCI: dwc: Pass the eDMA mapping format flag directly from glue drivers PCI: dwc: Skip finding eDMA channels count for HDMA platforms PCI: dwc: Refactor dw_pcie_edma_find_chip() API PCI: qcom-ep: Add support for SA8775P SOC dt-bindings: PCI: qcom-ep: Add support for SA8775P SoC PCI: qcom: Use devm_clk_bulk_get_all() API
2024-07-19Merge branch 'pci/controller/microchip'Bjorn Helgaas3-54/+196
- Move PLDA XpressRICH generic DT binding properties to plda,xpressrich3-axi-common.yaml where they can be shared across PLDA-based drivers (Minda Chen) - Create a drivers/pci/controller/plda/ directory for PLDA-based drivers and move pcie-microchip-host.c there (Minda Chen) - Move PLDA generic macros to pcie-plda.h where they can be shared across drivers (Minda Chen) - Extract PLDA generic structures from pcie-microchip-host.c, rename them to be generic, and move them to pcie-plda-host.c where they can be shared across drivers (Minda Chen) - Add a .request_event_irq() callback for requesting device-specific interrupts in addition to PLDA-generic interrupts (Minda Chen) - Add DT binding and driver for the StarFive JH7110 SoC, based on PLDA IP (Minda Chen) * pci/controller/microchip: PCI: starfive: Add JH7110 PCIe controller dt-bindings: PCI: Add StarFive JH7110 PCIe controller PCI: Add PCIE_RESET_CONFIG_DEVICE_WAIT_MS waiting time value PCI: plda: Pass pci_host_bridge to plda_pcie_setup_iomems() PCI: plda: Add host init/deinit and map bus functions PCI: plda: Add event bitmap field to struct plda_pcie_rp PCI: microchip: Move IRQ functions to pcie-plda-host.c PCI: microchip: Add event irqchip field to host port and add PLDA irqchip PCI: microchip: Add get_events() callback and PLDA get_event() PCI: microchip: Add INTx and MSI event num to struct plda_event PCI: microchip: Add request_event_irq() callback function PCI: microchip: Add num_events field to struct plda_pcie_rp PCI: microchip: Rename interrupt related functions PCI: microchip: Move PLDA functions to pcie-plda-host.c PCI: microchip: Rename PLDA functions to be generic PCI: microchip: Move PLDA structures to plda-pcie.h PCI: microchip: Rename PLDA structures to be generic PCI: microchip: Add bridge_addr field to struct mc_pcie PCI: microchip: Move PLDA IP register macros to pcie-plda.h PCI: microchip: Move pcie-microchip-host.c to PLDA directory dt-bindings: PCI: Add PLDA XpressRICH PCIe host common properties # Conflicts: # drivers/pci/pci.h
2024-07-04dt-bindings: PCI: qcom: x1e80100: Make the MHI reg region mandatoryAbel Vesa1-2/+1
All PCIe controllers found on X1E80100 have MHI register region. So change the schema to reflect that. Fixes: 692eadd51698 ("dt-bindings: PCI: qcom: Document the X1E80100 PCIe Controller") Link: https://lore.kernel.org/linux-pci/[email protected] Signed-off-by: Abel Vesa <[email protected]> Signed-off-by: Krzysztof Wilczyński <[email protected]> Reviewed-by: Rob Herring (Arm) <[email protected]> Reviewed-by: Manivannan Sadhasivam <[email protected]> Reviewed-by: Krzysztof Kozlowski <[email protected]>
2024-07-04dt-bindings: PCI: generic: Add ats-supported propertyJean-Philippe Brucker1-0/+6
Add a way for firmware to tell the OS that ATS is supported by the PCI root complex. An endpoint with ATS enabled may send Translation Requests and Translated Memory Requests, which look just like Normal Memory Requests with a non-zero AT field. So a root controller that ignores the AT field may simply forward the request to the IOMMU as a Normal Memory Request, which could end badly. In any case, the endpoint will be unusable. The ats-supported property allows the OS to only enable ATS in endpoints if the root controller can handle ATS requests. Only add the property to pcie-host-ecam-generic for the moment. For non-generic root controllers, availability of ATS can be inferred from the compatible string. Link: https://lore.kernel.org/linux-pci/[email protected] Signed-off-by: Jean-Philippe Brucker <[email protected]> Signed-off-by: Krzysztof Wilczyński <[email protected]> Reviewed-by: Jason Gunthorpe <[email protected]> Reviewed-by: Liviu Dudau <[email protected]> Reviewed-by: Nicolin Chen <[email protected]> Reviewed-by: Rob Herring <[email protected]> Reviewed-by: Robin Murphy <[email protected]>
2024-07-04dt-bindings: PCI: mediatek,mt7621-pcie: Add PCIe host topology ASCII graphSergio Paracuellos1-0/+29
MediaTek MT7621 PCIe sub-system supports a single Root Complex (RC) with 3 Root Ports. Add PCIe host topology ASCII graph to the binding for completeness. Suggested-by: Krzysztof Kozlowski <[email protected]> Link: https://lore.kernel.org/linux-pci/[email protected] Signed-off-by: Sergio Paracuellos <[email protected]> Signed-off-by: Krzysztof Wilczyński <[email protected]> Reviewed-by: AngeloGioacchino Del Regno <[email protected]> Acked-by: Krzysztof Kozlowski <[email protected]>
2024-07-04dt-bindings: PCI: qcom: Add OPP tableKrishna chaitanya chundru1-0/+4
PCIe needs to choose the appropriate performance state of RPMh power domain based on the PCIe gen speed. Adding the Operating Performance Points table allows to adjust power domain performance state and ICC peak bw, depending on the PCIe data rate and link width. Link: https://lore.kernel.org/linux-pci/[email protected] Signed-off-by: Krishna chaitanya chundru <[email protected]> Signed-off-by: Krzysztof Wilczyński <[email protected]> Reviewed-by: Krzysztof Kozlowski <[email protected]> Reviewed-by: Manivannan Sadhasivam <[email protected]>
2024-07-04dt-bindings: PCI: xilinx-cpm: Fix overlapping of bridge register and 32-bit ↵Thippeswamy Havalige1-1/+1
BAR addresses The current configuration had non-prefetchable memory overlapping with bridge registers by 64KB from base address. This patch fixes the 'ranges' property in the device tree by adjusting the non-prefetchable memory addresses beyond the 64KB mark to prevent conflicts. [kwilczynski: commit log] Link: https://lore.kernel.org/linux-pci/[email protected] Signed-off-by: Thippeswamy Havalige <[email protected]> Signed-off-by: Krzysztof Wilczyński <[email protected]> Acked-by: Krzysztof Kozlowski <[email protected]>
2024-07-04dt-bindings: PCI: rockchip: Add DesignWare based PCIe Endpoint controllerNiklas Cassel2-0/+109
Document DT bindings for PCIe Endpoint controller found in Rockchip SoCs. Link: https://lore.kernel.org/linux-pci/[email protected] Signed-off-by: Niklas Cassel <[email protected]> Signed-off-by: Krzysztof Wilczyński <[email protected]> Reviewed-by: Manivannan Sadhasivam <[email protected]> Reviewed-by: Rob Herring (Arm) <[email protected]>
2024-06-21dt-bindings: PCI: rockchip-dw-pcie: Fix description of legacy IRQNiklas Cassel1-1/+2
The descriptions of the combined interrupt signals (level1) mention all the lower interrupt signals (level2) for each combined interrupt, regardless if the lower (level2) signal is RC or EP specific. E.g. the description of "Combined system interrupt" includes rbar_update, which is EP specific, and the description of "Combined message interrupt" includes obff_idle, obff_obff, obff_cpu_active, which are all EP specific. The only exception is the "Combined legacy interrupt", which for some reason does not provide an exhaustive list of the lower (level2) signals. Add the missing lower interrupt signals: tx_inta, tx_intb, tx_intc, and tx_intd for the "Combined legacy interrupt", as per the rk3568 and rk3588 Technical Reference Manuals, such that the descriptions of the combined interrupt signals are consistent. Link: https://lore.kernel.org/linux-pci/[email protected] Signed-off-by: Niklas Cassel <[email protected]> Signed-off-by: Krzysztof Wilczyński <[email protected]> Reviewed-by: Manivannan Sadhasivam <[email protected]> Reviewed-by: Rob Herring (Arm) <[email protected]>
2024-06-21dt-bindings: PCI: rockchip-dw-pcie: Prepare for Endpoint mode supportNiklas Cassel2-90/+114
Refactor the rockchip-dw-pcie binding to move generic properties to a new rockchip-dw-pcie-common binding that can be shared by both RC and EP mode. No functional change intended. Link: https://lore.kernel.org/linux-pci/[email protected] Signed-off-by: Niklas Cassel <[email protected]> Signed-off-by: Krzysztof Wilczyński <[email protected]> Reviewed-by: Manivannan Sadhasivam <[email protected]> Reviewed-by: Rob Herring (Arm) <[email protected]>
2024-06-21dt-bindings: PCI: snps,dw-pcie-ep: Add tx_int{a,b,c,d} legacy IRQsNiklas Cassel1-0/+9
The DWC core has four interrupt signals: tx_inta, tx_intb, tx_intc, tx_intd that are triggered when the PCIe controller (when running in Endpoint mode) has sent an Assert_INTA Message to the upstream device. Some DWC controllers have these interrupt in a combined interrupt signal. Add the description of these interrupts to the device tree binding. Link: https://lore.kernel.org/linux-pci/[email protected] Signed-off-by: Niklas Cassel <[email protected]> Signed-off-by: Krzysztof Wilczyński <[email protected]> Reviewed-by: Manivannan Sadhasivam <[email protected]> Reviewed-by: Rob Herring (Arm) <[email protected]>
2024-06-21dt-bindings: PCI: snps,dw-pcie-ep: Add vendor specific interrupt-namesNiklas Cassel1-1/+1
Considering that some drivers (e.g. pcie-dw-rockchip.c) already use the interrupt-names "sys", "pmc", "msg", "err" for the device tree binding in Root Complex mode (snps,dw-pcie.yaml), it doesn't make sense that those drivers should use different interrupt-names when running in Endpoint mode (snps,dw-pcie-ep.yaml). Therefore, since "sys", "pmc", "msg", "err" are already defined in snps,dw-pcie.yaml, add them also for snps,dw-pcie-ep.yaml. Link: https://lore.kernel.org/linux-pci/[email protected] Signed-off-by: Niklas Cassel <[email protected]> Signed-off-by: Krzysztof Wilczyński <[email protected]> Reviewed-by: Manivannan Sadhasivam <[email protected]> Reviewed-by: Rob Herring (Arm) <[email protected]>
2024-06-21dt-bindings: PCI: snps,dw-pcie-ep: Add vendor specific reg-nameNiklas Cassel1-1/+1
Considering that some drivers (e.g. pcie-dw-rockchip.c) already use the reg-name "apb" for the device tree binding in Root Complex mode (snps,dw-pcie.yaml), it doesn't make sense that those drivers should use a different reg-name when running in Endpoint mode (snps,dw-pcie-ep.yaml). Therefore, since "apb" is already defined in snps,dw-pcie.yaml, add it also for snps,dw-pcie-ep.yaml. Link: https://lore.kernel.org/linux-pci/[email protected] Signed-off-by: Niklas Cassel <[email protected]> Signed-off-by: Krzysztof Wilczyński <[email protected]> Reviewed-by: Manivannan Sadhasivam <[email protected]> Reviewed-by: Rob Herring (Arm) <[email protected]>
2024-05-28dt-bindings: PCI: Add StarFive JH7110 PCIe controllerMinda Chen1-0/+120
Add StarFive JH7110 SoC PCIe controller dt-bindings. JH7110 uses PLDA XpressRICH PCIe host controller IP. Link: https://lore.kernel.org/linux-pci/[email protected] Signed-off-by: Minda Chen <[email protected]> Signed-off-by: Krzysztof Wilczyński <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Conor Dooley <[email protected]> Reviewed-by: Hal Feng <[email protected]> Reviewed-by: Rob Herring <[email protected]> Acked-by: Kevin Xie <[email protected]>
2024-05-28dt-bindings: PCI: Add PLDA XpressRICH PCIe host common propertiesMinda Chen2-54/+76
Add PLDA XpressRICH PCIe host common properties dt-binding doc. The PolarFire PCIe host uses PLDA IP. Move common properties from Microchip PolarFire PCIe host to PLDA files. Link: https://lore.kernel.org/linux-pci/[email protected] Signed-off-by: Minda Chen <[email protected]> Signed-off-by: Krzysztof Wilczyński <[email protected]> [bhelgaas: adapt for 5db62b7d3c37 ("dt-bindings: PCI: host-bridges: Switch from deprecated pci-bus.yaml")] Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Hal Feng <[email protected]> Reviewed-by: Conor Dooley <[email protected]> Reviewed-by: Rob Herring <[email protected]> Tested-by: John Clark <[email protected]>
2024-05-28dt-bindings: PCI: qcom-ep: Add support for SA8775P SoCMrinmay Sarkar1-2/+62
Add devicetree bindings support for SA8775P SoC. It has DMA register space and dma interrupt to support HDMA. Link: https://lore.kernel.org/linux-pci/[email protected] Signed-off-by: Mrinmay Sarkar <[email protected]> Signed-off-by: Krzysztof Wilczyński <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Krzysztof Kozlowski <[email protected]> Acked-by: Manivannan Sadhasivam <[email protected]>
2024-05-21Merge tag 'pci-v6.10-changes' of ↵Linus Torvalds32-110/+333
git://git.kernel.org/pub/scm/linux/kernel/git/pci/pci Pull pci updates from Bjorn Helgaas: "Enumeration: - Skip E820 checks for MCFG ECAM regions for new (2016+) machines, since there's no requirement to describe them in E820 and some platforms require ECAM to work (Bjorn Helgaas) - Rename PCI_IRQ_LEGACY to PCI_IRQ_INTX to be more specific (Damien Le Moal) - Remove last user and pci_enable_device_io() (Heiner Kallweit) - Wait for Link Training==0 to avoid possible race (Ilpo Järvinen) - Skip waiting for devices that have been disconnected while suspended (Ilpo Järvinen) - Clear Secondary Status errors after enumeration since Master Aborts and Unsupported Request errors are an expected part of enumeration (Vidya Sagar) MSI: - Remove unused IMS (Interrupt Message Store) support (Bjorn Helgaas) Error handling: - Mask Genesys GL975x SD host controller Replay Timer Timeout correctable errors caused by a hardware defect; the errors cause interrupts that prevent system suspend (Kai-Heng Feng) - Fix EDR-related _DSM support, which previously evaluated revision 5 but assumed revision 6 behavior (Kuppuswamy Sathyanarayanan) ASPM: - Simplify link state definitions and mask calculation (Ilpo Järvinen) Power management: - Avoid D3cold for HP Pavilion 17 PC/1972 PCIe Ports, where BIOS apparently doesn't know how to put them back in D0 (Mario Limonciello) CXL: - Support resetting CXL devices; special handling required because CXL Ports mask Secondary Bus Reset by default (Dave Jiang) DOE: - Support DOE Discovery Version 2 (Alexey Kardashevskiy) Endpoint framework: - Set endpoint BAR to be 64-bit if the driver says that's all the device supports, in addition to doing so if the size is >2GB (Niklas Cassel) - Simplify endpoint BAR allocation and setting interfaces (Niklas Cassel) Cadence PCIe controller driver: - Drop DT binding redundant msi-parent and pci-bus.yaml (Krzysztof Kozlowski) Cadence PCIe endpoint driver: - Configure endpoint BARs to be 64-bit based on the BAR type, not the BAR value (Niklas Cassel) Freescale Layerscape PCIe controller driver: - Convert DT binding to YAML (Frank Li) MediaTek MT7621 PCIe controller driver: - Add DT binding missing 'reg' property for child Root Ports (Krzysztof Kozlowski) - Fix theoretical string truncation in PHY name (Sergio Paracuellos) NVIDIA Tegra194 PCIe controller driver: - Return success for endpoint probe instead of falling through to the failure path (Vidya Sagar) Renesas R-Car PCIe controller driver: - Add DT binding missing IOMMU properties (Geert Uytterhoeven) - Add DT binding R-Car V4H compatible for host and endpoint mode (Yoshihiro Shimoda) Rockchip PCIe controller driver: - Configure endpoint BARs to be 64-bit based on the BAR type, not the BAR value (Niklas Cassel) - Add DT binding missing maxItems to ep-gpios (Krzysztof Kozlowski) - Set the Subsystem Vendor ID, which was previously zero because it was masked incorrectly (Rick Wertenbroek) Synopsys DesignWare PCIe controller driver: - Restructure DBI register access to accommodate devices where this requires Refclk to be active (Manivannan Sadhasivam) - Remove the deinit() callback, which was only need by the pcie-rcar-gen4, and do it directly in that driver (Manivannan Sadhasivam) - Add dw_pcie_ep_cleanup() so drivers that support PERST# can clean up things like eDMA (Manivannan Sadhasivam) - Rename dw_pcie_ep_exit() to dw_pcie_ep_deinit() to make it parallel to dw_pcie_ep_init() (Manivannan Sadhasivam) - Rename dw_pcie_ep_init_complete() to dw_pcie_ep_init_registers() to reflect the actual functionality (Manivannan Sadhasivam) - Call dw_pcie_ep_init_registers() directly from all the glue drivers, not just those that require active Refclk from the host (Manivannan Sadhasivam) - Remove the "core_init_notifier" flag, which was an obscure way for glue drivers to indicate that they depend on Refclk from the host (Manivannan Sadhasivam) TI J721E PCIe driver: - Add DT binding J784S4 SoC Device ID (Siddharth Vadapalli) - Add DT binding J722S SoC support (Siddharth Vadapalli) TI Keystone PCIe controller driver: - Add DT binding missing num-viewport, phys and phy-name properties (Jan Kiszka) Miscellaneous: - Constify and annotate with __ro_after_init (Heiner Kallweit) - Convert DT bindings to YAML (Krzysztof Kozlowski) - Check for kcalloc() failure in of_pci_prop_intr_map() (Duoming Zhou)" * tag 'pci-v6.10-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/pci/pci: (97 commits) PCI: Do not wait for disconnected devices when resuming x86/pci: Skip early E820 check for ECAM region PCI: Remove unused pci_enable_device_io() ata: pata_cs5520: Remove unnecessary call to pci_enable_device_io() PCI: Update pci_find_capability() stub return types PCI: Remove PCI_IRQ_LEGACY scsi: vmw_pvscsi: Do not use PCI_IRQ_LEGACY instead of PCI_IRQ_LEGACY scsi: pmcraid: Use PCI_IRQ_INTX instead of PCI_IRQ_LEGACY scsi: mpt3sas: Use PCI_IRQ_INTX instead of PCI_IRQ_LEGACY scsi: megaraid_sas: Use PCI_IRQ_INTX instead of PCI_IRQ_LEGACY scsi: ipr: Use PCI_IRQ_INTX instead of PCI_IRQ_LEGACY scsi: hpsa: Use PCI_IRQ_INTX instead of PCI_IRQ_LEGACY scsi: arcmsr: Use PCI_IRQ_INTX instead of PCI_IRQ_LEGACY wifi: rtw89: Use PCI_IRQ_INTX instead of PCI_IRQ_LEGACY dt-bindings: PCI: rockchip,rk3399-pcie: Add missing maxItems to ep-gpios Revert "genirq/msi: Provide constants for PCI/IMS support" Revert "x86/apic/msi: Enable PCI/IMS" Revert "iommu/vt-d: Enable PCI/IMS" Revert "iommu/amd: Enable PCI/IMS" Revert "PCI/MSI: Provide IMS (Interrupt Message Store) support" ...
2024-05-16dt-bindings: PCI: rockchip,rk3399-pcie: Add missing maxItems to ep-gpiosKrzysztof Kozlowski1-0/+1
Properties with GPIOs should define number of actual GPIOs, so add missing maxItems to ep-gpios. Otherwise multiple GPIOs could be provided which is not a true hardware description. Fixes: aa222f9311e1 ("dt-bindings: PCI: Convert Rockchip RK3399 PCIe to DT schema") Link: https://lore.kernel.org/linux-pci/[email protected] Signed-off-by: Krzysztof Kozlowski <[email protected]> Signed-off-by: Krzysztof Wilczyński <[email protected]> Acked-by: Conor Dooley <[email protected]>
Powered by cgit, Gruvboxed by Blaster4385.