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2024-02-06dt-bindings: firmware: xilinx: Describe soc-nvmem subnodeMichal Simek1-0/+18
Describe soc-nvmem subnode as the part of firmware node. The name can't be pure nvmem because dt-schema already defines it as array property that's why different name should be used. Acked-by: Conor Dooley <[email protected]> Link: https://lore.kernel.org/r/24fe6adbf2424360618e8f5ca541ebfd8bb0723e.1706692641.git.michal.simek@amd.com Signed-off-by: Michal Simek <[email protected]>
2024-01-22dt-bindings: firmware: xilinx: Sort node names (clock-controller)Michal Simek1-9/+9
Nodes should be sorted that's why move clock-controller to the top of list. Acked-by: Krzysztof Kozlowski <[email protected]> Link: https://lore.kernel.org/r/ccb6bd5f4d1d28983c73497ada596e893fece499.1703161663.git.michal.simek@amd.com Signed-off-by: Michal Simek <[email protected]>
2024-01-22dt-bindings: firmware: xilinx: Describe missing child nodesMichal Simek1-0/+50
Firmware node has more than fpga, aes and clock child nodes but also power, reset, gpio, pinctrl and pcap which are not described yet. All of them have binding in separate files but there is missing connection to firmware node that's why describe it. Reviewed-by: Krzysztof Kozlowski <[email protected]> Link: https://lore.kernel.org/r/1d7988cfadf3554d11f0779f96a670b4fd86ce5a.1703161663.git.michal.simek@amd.com Signed-off-by: Michal Simek <[email protected]>
2024-01-22dt-bindings: firmware: xilinx: Fix versal-fpga node nameMichal Simek1-2/+2
Based on commit 83a368a3fc8a ("docs: dt-bindings: add DTS Coding Style document") using underscore ('_') in node name is not recommended that's why switch to dash ('-'). Acked-by: Xu Yilun <[email protected]> Acked-by: Krzysztof Kozlowski <[email protected]> Link: https://lore.kernel.org/r/6779af2f9cc21c912f10cf310388d99b980800b2.1702996281.git.michal.simek@amd.com Signed-off-by: Michal Simek <[email protected]>
2024-01-22dt-bindings: firmware: versal: add versal-net compatible stringJay Buddhabhatti1-0/+6
Add dt-binding documentation for Versal NET platforms. Versal Net is a new AMD/Xilinx SoC. The SoC and its architecture is based on the Versal ACAP device. The Versal Net device includes more security features in the platform management controller (PMC) and increases the number of CPUs in the application processing unit (APU) and the real-time processing unit (RPU). Signed-off-by: Jay Buddhabhatti <[email protected]> Signed-off-by: Radhey Shyam Pandey <[email protected]> Acked-by: Krzysztof Kozlowski <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Michal Simek <[email protected]>
2023-12-17dt-bindings: Remove alt_ref from versalShubhrajyoti Datta1-2/+2
The alt_ref is present only in Versal-net devices. Other versal devices do not have it. So remove alt_ref for versal. Fixes: 352546805a44 ("dt-bindings: clock: Add bindings for versal clock driver") Signed-off-by: Shubhrajyoti Datta <[email protected]> Link: https://lore.kernel.org/r/[email protected] Acked-by: Conor Dooley <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2023-08-18dt-bindings: power: xilinx: merge zynqmp-genpd.txt with firmware bindingNaman Trivedi Manojbhai1-0/+14
Remove the zynqmp-genpd.txt binding. Add the power-domain-cells property from the zynqmp-genpd.txt binding to firmware binding. Signed-off-by: Naman Trivedi Manojbhai <[email protected]> Acked-by: Conor Dooley <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Rob Herring <[email protected]>
2023-06-05dt-bindings: xilinx: Switch xilinx.com emails to amd.comMichal Simek1-1/+1
@xilinx.com is still working but better to switch to new amd.com after AMD/Xilinx acquisition. Acked-by: Sebastian Reichel <[email protected]> Acked-by: Wolfram Sang <[email protected]> # for I2C Acked-by: Mark Brown <[email protected]> Acked-by: Jassi Brar <[email protected]> Acked-by: Damien Le Moal <[email protected]> Acked-by: Krzysztof Kozlowski <[email protected]> Acked-by: Guenter Roeck <[email protected]> Signed-off-by: Michal Simek <[email protected]> Link: https://lore.kernel.org/r/f5b2bd1e78407e4128fc8f0b5874ba723e710a88.1684245058.git.michal.simek@amd.com
2021-07-21dt-bindings: firmware: Remove xlnx,zynqmp-firmware.txt fileNava kishore Manne1-44/+0
The funtionality of xlnx,zynqmp-firmware.txt is replaced with xlnx,zynqmp-firmware.yaml bindings so this patch removes the zynqmp-firmware.txt file Reviewed-by: Rob Herring <[email protected]> Signed-off-by: Nava kishore Manne <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Greg Kroah-Hartman <[email protected]>
2021-07-21dt-bindings: firmware: Add bindings for xilinx firmwareNava kishore Manne1-0/+89
Add documentation to describe Xilinx firmware driver bindings. Firmware driver provides an interface to firmware APIs. Interface APIs can be used by any driver to communicate to Platform Management Unit. Reviewed-by: Rob Herring <[email protected]> Signed-off-by: Nava kishore Manne <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Greg Kroah-Hartman <[email protected]>
2019-10-16dt-bindings: firmware: Add bindings for Versal firmwareJolly Shah1-1/+15
ZynqMP firmware driver can be used for versal also. Add versal compatible string to zynqmp firmware driver doc. Signed-off-by: Jolly Shah <[email protected]> Reviewed-by: Rob Herring <[email protected]> Signed-off-by: Michal Simek <[email protected]>
2019-03-18dt-bindings: xilinx: Separate clock binding from firmware docRajan Vaja1-53/+1
Clock description is part of firmware doc. Move clock description in separate doc. Signed-off-by: Rajan Vaja <[email protected]> Signed-off-by: Jolly Shah <[email protected]> Signed-off-by: Michal Simek <[email protected]>
2019-03-18include: dt-binding: clock: Rename zynqmp header fileJolly Shah1-1/+1
Rename file name of ZynqMP clk dt-bindings to align with file name of reset and power dt-bindings. Signed-off-by: Rajan Vaja <[email protected]> Signed-off-by: Jolly Shah <[email protected]> Signed-off-by: Michal Simek <[email protected]>
2018-10-09dt-bindings: clock: Add bindings for ZynqMP clock driverRajan Vaja1-0/+53
Add documentation to describe Xilinx ZynqMP clock driver bindings. Signed-off-by: Rajan Vaja <[email protected]> Signed-off-by: Jolly Shah <[email protected]> Reviewed-by: Rob Herring <[email protected]> Reviewed-by: Stephen Boyd <[email protected]> Signed-off-by: Michal Simek <[email protected]>
2018-09-26dt-bindings: firmware: Add bindings for ZynqMP firmwareRajan Vaja1-0/+29
Add documentation to describe Xilinx ZynqMP firmware driver bindings. Firmware driver provides an interface to firmware APIs. Interface APIs can be used by any driver to communicate to PMUFW (Platform Management Unit). Signed-off-by: Rajan Vaja <[email protected]> Signed-off-by: Jolly Shah <[email protected]> Reviewed-by: Rob Herring <[email protected]> Signed-off-by: Michal Simek <[email protected]>
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