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2022-07-21dt-bindings: Fix typo in commentSlark Xiao1-1/+1
Fix typo in the comment Signed-off-by: Slark Xiao <[email protected]> Reviewed-by: Krzysztof Kozlowski <[email protected]> Signed-off-by: Rob Herring <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2019-11-14dt-bindings: power: Convert Generic Power Domain bindings to json-schemaKrzysztof Kozlowski1-1/+1
Convert Generic Power Domain bindings to DT schema format using json-schema. Signed-off-by: Krzysztof Kozlowski <[email protected]> Reviewed-by: Ulf Hansson <[email protected]> Acked-by: Stephen Boyd <[email protected]> Reviewed-by: Rob Herring <[email protected]> Signed-off-by: Rob Herring <[email protected]>
2018-03-20dt-bindings: clock: Add bindings for DA8XX CFGCHIP clocksDavid Lechner1-0/+93
This adds a new binding for the clocks present in the CFGCHIP syscon registers in TI DA8XX SoCs. Signed-off-by: David Lechner <[email protected]> Reviewed-by: Rob Herring <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2018-03-20dt-bindings: clock: New bindings for TI Davinci PSCDavid Lechner1-0/+71
This adds a new binding for the Power Sleep Controller (PSC) for the mach-davinci family of processors. Note: Although TI Keystone has a very similar PSC, we are not using the existing bindings. Keystone is using a legacy one-node-per-clock binding (actually two nodes if you count the separate reset binding for the same IP block). Also, some davinci LPSCs have quirks that aren't handled by the keystone bindings, so we would be adding one compatible string per clock with quirks instead of just a new compatible string for each controller. Signed-off-by: David Lechner <[email protected]> Reviewed-by: Rob Herring <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2018-03-20dt-bindings: clock: Add new bindings for TI Davinci PLL clocksDavid Lechner1-0/+96
This adds a new binding for the PLL IP blocks in the mach-davinci family of processors. Currently, only da850 has device tree support but these bindings can also work for other SoCs in this family just by adding new compatible strings. Note: Although these PLL controllers are very similar to the TI Keystone SoCs, we are not re-using those bindings. The Keystone bindings use a legacy one-node-per-clock binding. Furthermore, the mach-davinici SoCs have a slightly different PLL register layout and a number of quirks that can't be handled by the existing bindings, so the keystone bindings could not be used as-is anyway. Signed-off-by: David Lechner <[email protected]> Reviewed-by: Rob Herring <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>