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The Qualcomm SPM / SAW2 device is described in two bindigns files:
arm/msm/qcom,saw2.txt and soc/qcom/qcom,spm.yaml. Merge the former into
the latter, adding detailed device node description. While we are at it,
also rename qcom,spm.yaml to qcom,saw2.yaml to follow the actual
compatible used for these devices.
The regulator property is retained as is. It will be changed in the
later patches.
Reviewed-by: Rob Herring <[email protected]>
Signed-off-by: Dmitry Baryshkov <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Bjorn Andersson <[email protected]>
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Merge Qualcomm-specific idle-state binding with generic one.
Signed-off-by: David Heidelberg <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Rob Herring <[email protected]>
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Convert arm/msm/ssbi.txt yo YAML, moving it to the directory with bus
bindings.
Signed-off-by: Dmitry Baryshkov <[email protected]>
Reviewed-by: Krzysztof Kozlowski <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Rob Herring <[email protected]>
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git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
Pull clk updates from Stephen Boyd:
"Nothing looks out of the ordinary in this batch of clk driver updates.
There are a couple patches to the core clk framework, but they're all
basically cleanups or debugging aids. The driver updates and new
additions are dominated in the diffstat by Qualcomm and MediaTek
drivers. Qualcomm gained a handful of new drivers for various SoCs,
and MediaTek gained a bunch of drivers for MT8188. The MediaTek
drivers are being modernized as well, so there are updates all over
that vendor's clk drivers. There's also a couple other new clk drivers
in here, for example the Starfive JH7110 SoC support is added.
Outside of the two major SoC vendors though, we have the usual
collection of non-critical fixes and cleanups to various clk drivers.
It's good to see that we're getting more cleanups and modernization
patches. Maybe one day we'll be able to properly split clk providers
from clk consumers.
Core:
- Print an informational message before disabling unused clks
New Drivers:
- BCM63268 timer clock and reset controller
- Frequency Hopping (FHCTL) on MediaTek MT6795, MT8173, MT8192 and
MT8195 SoCs
- Mediatek MT8188 SoC clk drivers
- Clock driver for Sunplus SP7021 SoC
- Clk driver support for Loongson-2 SoCs
- Clock driver for Skyworks Si521xx I2C PCIe clock generators
- Initial Starfive JH7110 clk/reset support
- Global clock controller drivers for Qualcomm SM7150, IPQ9574,
MSM8917 and IPQ5332 SoCs
- GPU clock controller drivers for SM6115, SM6125, SM6375 and SA8775P
SoCs
Updates:
- Shrink size of clk_fractional_divider a little
- Convert various clk drivers to devm_of_clk_add_hw_provider()
- Convert platform clk drivers to remove_new()
- Converted most Mediatek clock drivers to struct platform_driver
- MediaTek clock drivers can be built as modules
- Reimplement Loongson-1 clk driver with DT support
- Migrate socfpga clk driver to of_clk_add_hw_provider()
- Support for i3c clks on Aspeed ast2600 SoCs
- Add clock generic devm_clk_hw_register_gate_parent_data
- Add audiomix block control for i.MX8MP
- Add support for determine_rate to i.MX composite-8m
- Let the LCDIF Pixel clock of i.MX8MM and i.MX8MN set parent rate
- Provide clock name in error message for clk-gpr-mux on get parent
failure
- Drop duplicate imx_clk_mux_flags macro
- Register the i.MX8MP Media Disp2 Pix clock as bus clock
- Add Media LDB root clock to i.MX8MP
- Make i.MX8MP nand_usdhc_bus clock as non-critical
- Fix the rate table for i.MX fracn-gppll
- Disable HW control for the fracn-gppll in order to be controlled by
register write
- Add support for interger PLL in fracn-gppll
- Add mcore_booted module parameter to i.MX93 provider
- Add NIC, A55 and ARM PLL clocks to i.MX93
- Fix i.MX8ULP XBAR_DIVBUS and AD_SLOW clock parents
- Use "divider closest" clock type for PLL4_PFD dividers on i.MX8ULP
to get more accurate clock rates
- Mark the MU0_Bi and TPM5 clocks on i.MX8ULP as critical
- Update some of the i.MX critical clocks flags to allow glitchless
on-the-fly rate change.
- Add I2C5 clock on Renesas R-Car V3H
- Exynos850: Add CMU_G3D clock controller for the Mali GPU
- Extract Exynos5433 (ARM64) clock controller power management code
to common driver parts
- Exynos850: make PMU_ALIVE_PCLK clock critical
- Add Audio, thermal, camera (CSI-2), Image Signal Processor/Channel
Selector (ISPCS), and video capture (VIN) clocks on Renesas R-Car
V4H
- Add video capture (VIN) clocks on Renesas R-Car V3H
- Add Cortex-A53 System CPU (Z2) clocks on Renesas R-Car V3M and V3H
- Support for Stromer Plus PLL on Qualcomm IPQ5332
- Add a missing reset to Qualcomm QCM2290
- Migrate Qualcomm IPQ4019 to clk_parent_data
- Make USB GDSCs enter retention state when disabled on Qualcomm
SM6375, MSM8996 and MSM8998 SoCs
- Set floor rounding clk_ops for Qualcomm QCM2290 SDCC2 clk
- Add two EMAC GDSCs on Qualcomm SC8280XP
- Use shared rcg clk ops in Qualcomm SM6115 GCC
- Park Qualcomm SM8350 PCIe PIPE clks when disabled
- Add GDSCs to Qualcomm SC7280 LPASS audio clock controller
- Add missing XO clocks to Qualcomm MSM8226 and MSM8974
- Convert some Qualcomm clk DT bindings to YAML
- Reparenting fix for the clock supplying camera modules on Rockchip
rk3399
- Mark more critical (bus-)clocks on Rockchip rk3588"
* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (290 commits)
clk: qcom: gcc-sc8280xp: Add EMAC GDSCs
clk: starfive: Delete the redundant dev_set_drvdata() in JH7110 clock drivers
clk: rockchip: rk3588: make gate linked clocks critical
clk: qcom: dispcc-qcm2290: Remove inexistent DSI1PHY clk
clk: qcom: add the GPUCC driver for sa8775p
dt-bindings: clock: qcom: describe the GPUCC clock for SA8775P
clk: qcom: gcc-sm8350: fix PCIe PIPE clocks handling
clk: qcom: lpassaudiocc-sc7280: Add required gdsc power domain clks in lpass_cc_sc7280_desc
clk: qcom: lpasscc-sc7280: Skip qdsp6ss clock registration
dt-bindings: clock: qcom,sc7280-lpasscc: Add qcom,adsp-pil-mode property
clk: starfive: Avoid casting iomem pointers
clk: microchip: fix potential UAF in auxdev release callback
clk: qcom: rpm: Use managed `of_clk_add_hw_provider()`
clk: mediatek: fhctl: Mark local variables static
clk: sifive: make SiFive clk drivers depend on ARCH_ symbols
clk: uniphier: Use managed `of_clk_add_hw_provider()`
clk: si5351: Use managed `of_clk_add_hw_provider()`
clk: si570: Use managed `of_clk_add_hw_provider()`
clk: si514: Use managed `of_clk_add_hw_provider()`
clk: lmk04832: Use managed `of_clk_add_hw_provider()`
...
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There's a bunch of bindings for (mostly l2) cache controllers
scattered to the four winds, move them to a common directory.
I renamed the freescale l2cache.txt file, as while that might make sense
when the parent dir is fsl, it's confusing after the move.
The two Marvell bindings have had a "marvell," prefix added to match
their compatibles.
Signed-off-by: Conor Dooley <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Rob Herring <[email protected]>
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Rework kpss-gcc driver Documentation to yaml Documentation and move it
to clock as it's a clock-controller.
The current kpss-gcc Documentation have major problems and can't be
converted directly. Introduce various changes to the original
Documentation.
Add #clock-cells additional binding as this clock outputs a static clk
named acpu_l2_aux with supported compatible.
Only some compatible require and outputs a clock, for the others, set
only the reg as a required binding to correctly export the kpss-gcc
registers. As the reg is shared also add the required syscon compatible.
Signed-off-by: Christian Marangi <[email protected]>
Reviewed-by: Rob Herring <[email protected]>
Signed-off-by: Bjorn Andersson <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
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Convert kpss-acc driver Documentation to yaml.
The original Documentation was wrong all along. Fix it while we are
converting it.
The example was wrong as kpss-acc-v2 should only expose the regs but we
don't have any driver that expose additional clocks. The kpss-acc driver
is only specific to v1. For this exact reason, split the Documentation
to 2 different schema, v1 as clock-controller and v2 for
power-manager as per msm-3.10 specification, the exposed regs handle
power manager.
Signed-off-by: Christian Marangi <[email protected]>
Reviewed-by: Rob Herring <[email protected]>
Signed-off-by: Bjorn Andersson <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
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Add LLCC compatible for SM8550 SoC.
Signed-off-by: Abel Vesa <[email protected]>
Reviewed-by: Krzysztof Kozlowski <[email protected]>
Signed-off-by: Bjorn Andersson <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
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Fix typo in the comment
Signed-off-by: Slark Xiao <[email protected]>
Reviewed-by: Krzysztof Kozlowski <[email protected]>
Signed-off-by: Rob Herring <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
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Add compatibles for the SC8180X and SC8280XP platforms to the existing
LLCC binding.
Acked-by: Krzysztof Kozlowski <[email protected]>
Signed-off-by: Bjorn Andersson <[email protected]>
Acked-by: Rob Herring <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
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This series adds RISC-V CPU Idle support using SBI HSM suspend function.
The RISC-V SBI CPU idle driver added by this series is highly inspired
from the ARM PSCI CPU idle driver.
Special thanks Sandeep Tripathy for providing early feeback on SBI HSM
support in all above projects (RISC-V SBI specification, OpenSBI, and
Linux RISC-V).
* palmer/riscv-idle:
RISC-V: Enable RISC-V SBI CPU Idle driver for QEMU virt machine
dt-bindings: Add common bindings for ARM and RISC-V idle states
cpuidle: Add RISC-V SBI CPU idle driver
cpuidle: Factor-out power domain related code from PSCI domain driver
RISC-V: Add SBI HSM suspend related defines
RISC-V: Add arch functions for non-retentive suspend entry/exit
RISC-V: Rename relocate() and make it global
RISC-V: Enable CPU_IDLE drivers
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The RISC-V CPU idle states will be described in under the
/cpus/idle-states DT node in the same way as ARM CPU idle
states.
This patch adds common bindings documentation for both ARM
and RISC-V idle states.
Signed-off-by: Anup Patel <[email protected]>
Signed-off-by: Anup Patel <[email protected]>
Reviewed-by: Rob Herring <[email protected]>
Reviewed-by: Guo Ren <[email protected]>
Signed-off-by: Palmer Dabbelt <[email protected]>
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Add LLCC compatible for SM8450 SoC.
Cc: Rob Herring <[email protected]>
Signed-off-by: Sai Prakash Ranjan <[email protected]>
Reviewed-by: Krzysztof Kozlowski <[email protected]>
Tested-by: Vinod Koul <[email protected]>
Signed-off-by: Bjorn Andersson <[email protected]>
Link: https://lore.kernel.org/r/f5235371f07ac0ce367c6ea84ed49937fb751a07.1643355594.git.quic_saipraka@quicinc.com
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Add LLCC compatible for SM8350 SoC.
Cc: Rob Herring <[email protected]>
Signed-off-by: Sai Prakash Ranjan <[email protected]>
Reviewed-by: Krzysztof Kozlowski <[email protected]>
Tested-by: Vinod Koul <[email protected]>
Signed-off-by: Bjorn Andersson <[email protected]>
Link: https://lore.kernel.org/r/e3d200eb06949f7e216b7f82f5811b7addb7fdc8.1643355594.git.quic_saipraka@quicinc.com
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Newer SoCs like SM6350 or SM8250 don't provide an interrupt for LLCC.
Signed-off-by: Luca Weiss <[email protected]>
Acked-by: Konrad Dybcio <[email protected]>
Signed-off-by: Bjorn Andersson <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
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Add LLCC compatible for SM6350 SoC.
Reviewed-by: AngeloGioacchino Del Regno <[email protected]>
Signed-off-by: Konrad Dybcio <[email protected]>
Acked-by: Rob Herring <[email protected]>
Signed-off-by: Luca Weiss <[email protected]>
Signed-off-by: Bjorn Andersson <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
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Add the dt-binding compatible in the SPM AVS Wrapper 2 (SAW2) for the
MSM8226 SoC platform.
Acked-by: Rob Herring <[email protected]>
Signed-off-by: Bartosz Dudziak <[email protected]>
Signed-off-by: Daniel Lezcano <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
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Add LLCC compatible for SC7280 SoC.
Acked-by: Rob Herring <[email protected]>
Reviewed-by: Stephen Boyd <[email protected]>
Signed-off-by: Sai Prakash Ranjan <[email protected]>
Link: https://lore.kernel.org/r/f3b32d437d7c1165a74ceec2cd52ff56b496e5a3.1614244789.git.saiprakash.ranjan@codeaurora.org
Signed-off-by: Bjorn Andersson <[email protected]>
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Add LLCC compatible for SM8250 SoC.
Signed-off-by: Manivannan Sadhasivam <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Bjorn Andersson <[email protected]>
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Add LLCC compatible for SM8150 SoC.
Acked-by: Rob Herring <[email protected]>
Signed-off-by: Souradeep Chowdhury <[email protected]>
Link: https://lore.kernel.org/r/141e7cf03932859243edec83451c04c655ba640b.1601452132.git.schowdhu@codeaurora.org
Signed-off-by: Bjorn Andersson <[email protected]>
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Setting 'additionalProperties: false' is frequently omitted, but is
important in order to check that there aren't extra undocumented
properties in a binding.
Ideally, we'd just add this automatically and make this the default, but
there's some cases where it doesn't work. For example, if a common
schema is referenced, then properties in the common schema aren't part
of what's considered for 'additionalProperties'. Also, sometimes there
are bus specific properties such as 'spi-max-frequency' that go into
bus child nodes, but aren't defined in the child node's schema.
So let's stick with the json-schema defined default and add
'additionalProperties: false' where needed. This will be a continual
review comment and game of wack-a-mole.
Signed-off-by: Rob Herring <[email protected]>
Reviewed-by: Neil Armstrong <[email protected]>
Acked-by: Mark Brown <[email protected]>
Acked-by: Jonathan Cameron <[email protected]>
Acked-by: Alexandru Ardelean <[email protected]>
Reviewed-by: Benjamin Gaignard <[email protected]>
Acked-by: Stephen Boyd <[email protected]> # clock
Acked-by: Lee Jones <[email protected]>
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Several DT references got broken due to txt->yaml conversion.
Those are auto-fixed by running:
scripts/documentation-file-ref-check --fix
Signed-off-by: Mauro Carvalho Chehab <[email protected]>
Acked-by: Andrew Jeffery <[email protected]>
Reviewed-by: Dan Murphy <[email protected]>
Reviewed-by: Amit Kucheria <[email protected]>
Signed-off-by: Rob Herring <[email protected]>
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DT schema checks for the node name 'cache-controller' and enforces
that there has to be a cache-level associated with it. But LLCC is
a system cache and does not have a cache-level property and hence
the dt binding check fails. So let us rename the LLCC cache-controller
to system-cache-controller which is the proper description and also
makes the schema happy.
Acked-by: Rob Herring <[email protected]>
Reviewed-by: Stephen Boyd <[email protected]>
Suggested-by: Stephen Boyd <[email protected]>
Signed-off-by: Sai Prakash Ranjan <[email protected]>
Link: https://lore.kernel.org/r/83394ae827ce7c123228b749bcae2a2c470e88a4.1573814758.git.saiprakash.ranjan@codeaurora.org
Signed-off-by: Bjorn Andersson <[email protected]>
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Add LLCC compatible for SC7180 SoC.
Reviewed-by: Stephen Boyd <[email protected]>
Signed-off-by: Sai Prakash Ranjan <[email protected]>
Signed-off-by: Bjorn Andersson <[email protected]>
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Convert LLCC bindings to DT schema format using json-schema.
Reviewed-by: Stephen Boyd <[email protected]>
Signed-off-by: Sai Prakash Ranjan <[email protected]>
Signed-off-by: Bjorn Andersson <[email protected]>
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git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
Pull clk updates from Stephen Boyd:
"This time it looks like a quieter release cycle in the clk tree. I
guess that's because of summer time holidays/vacations. The biggest
change in the diffstat is in the Qualcomm clk driver, where they got
support for CPUs and handful of SoCs. After that, the at91 driver got
a major rewrite for newer DT bindings that should make things easier
going forward and the TI code moved to a clockdomain based design.
The long tail is mostly small driver updates for newer clks and some
simpler SoC clock drivers such as the Hisilicon and imx support.
In the core framework, we only have two small changes this time.
One is a new clk API to get all clks for a device with the bulk clk
APIs. This allows drivers that don't care about doing anything besides
turning on all the clks to just clk_get() them all and turn them on.
The other change is the beginning of a way to support save and restore
of clk settings in the clk framework. TI is the only user right now,
but we will want to expand upon this design in the future to support
more save and restore of clk registers. At least this gets us started
and works well enough for one SoC, but there's more work in the
future.
Core:
- clk_bulk_get_all() API and friends to get all the clks for a device
- Basic clk state save/restore hooks
New Drivers:
- Renesas RZ/A2 (R7S9210) SoC, including early clocks
- Rensas RZ/G1N (R8A7744) and RZ/G2E (R8A774C0) SoCs
- Rensas RZ/G2M (r8a774a1) SoC
- Qualcomm Krait CPU clk support
- Qualcomm QCS404 GCC support
- Qualcomm SDM660 GCC support
- Qualcomm SDM845 camera clock controller
- Ingenic jz4725b CGU
- Hisilicon 3670 SoC support
- TI SCI clks on K3 SoCs
- iMX6 MMDC clks
- Reset Controller (RMU) support for Actions Semi Owl S900 and S700 SoCs
Updates:
- Rework at91 PMC clock driver for new DT bindings
- Nvidia Tegra clk driver MBIST workaround fix
- S2RAM support for Marvell mvebu periph clks
- Use updated printk format for OF node names
- Fix TI code to only search DT subnodes
- Various static analysis finds
- Tag various drivers with SPDX license tags
- Support dynamic frequency switching (DFS) on qcom SDM845 GCC
- Only use s2mps11 dt-binding defines instead of redefining them in the driver
- Add some more missing clks to qcom MSM8996 GCC
- Quad SPI clks on qcom SDM845
- Add support for CMT timer clocks on R-Car V3H
- Add support for SHDI and various timer clocks on R-Car V3M
- Improve OSC and RCLK (watchdog) handling on R-Car Gen3 SoCs
- Amlogic clk-pll driver improvements and updates
- Amlogic axg audio controller system clocks
- Register Amlogic meson8b clock controller early
- Add support for SATA and Fine Display Processor (FDP) clocks on R-Car M3-N
- Consolidation of system suspend related code in Exynos, S5P, S3C SoC clk drivers
- Fixes for system suspend support on Exynos542x (Odroid boards) and Exynos5433 SoC
- Remove obsoleted Exynos4212 ISP clock definitions
- Migrated TI am3/4/5 and dra7 SoCs to clockdomain based design
- TI RTC+DDR sleep mode support for clock save/restore
- Allwinner A64 display engine support and fixes
- Allwinner A83t display engine support and fixes"
* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (186 commits)
clk: qcom: Remove unused arrays in SDM845 GCC
clk: fixed-rate: fix of_node_get-put imbalance
clk: s2mps11: Add used attribute to s2mps11_dt_match
clk: qcom: gcc-sdm660: Add MODULE_LICENSE
clk: qcom: Add safe switch hook for krait mux clocks
dt-bindings: clock: Document qcom,krait-cc
clk: qcom: Add Krait clock controller driver
dt-bindings: arm: Document qcom,kpss-gcc
clk: qcom: Add KPSS ACC/GCC driver
clk: qcom: Add support for Krait clocks
clk: qcom: Add IPQ806X's HFPLLs
clk: qcom: Add MSM8960/APQ8064's HFPLLs
dt-bindings: clock: Document qcom,hfpll
clk: qcom: Add HFPLL driver
clk: qcom: Add support for High-Frequency PLLs (HFPLLs)
ARM: Add Krait L2 register accessor functions
clk: imx6q: add mmdc0 ipg clock
clk: imx6sl: add mmdc ipg clocks
clk: imx6sll: add mmdc1 ipg clock
clk: imx6sx: add mmdc1 ipg clock
...
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The ACC and GCC regions present in KPSSv1 contain registers to
control clocks and power to each Krait CPU and L2. Documenting
the bindings here.
Reviewed-by: Rob Herring <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
Signed-off-by: Sricharan R <[email protected]>
Tested-by: Craig Tatlor <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
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Add reg-names and interrupts for LLCC documentation and the usage
examples. llcc broadcast base is added in addition to llcc base,
which is used for llcc broadcast writes.
Signed-off-by: Venkata Narendra Kumar Gutta <[email protected]>
Reviewed-by: Rob Herring <[email protected]>
Signed-off-by: Andy Gross <[email protected]>
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Documentation for last level cache controller device tree bindings,
client bindings usage examples.
Signed-off-by: Channagoud Kadabi <[email protected]>
Signed-off-by: Rishabh Bhatnagar <[email protected]>
Reviewed-by: Evan Green <[email protected]>
Reviewed-by: Rob Herring <[email protected]>
Reviewed-by: Bjorn Andersson <[email protected]>
Signed-off-by: Andy Gross <[email protected]>
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Bindings are supposed to be organized by device class/function. Move
bindings for various timers to timer/ binding directory.
Cc: Linus Walleij <[email protected]>
Acked-by: Thierry Reding <[email protected]>
Signed-off-by: Rob Herring <[email protected]>
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Pull watchdog updates from Wim Van Sebroeck:
"This contains following changes:
- Octeon: convert to watchdog-API and apply some fixes
- Cadence wdt: remove dependency on ARCH
- add DT bindings for qcom + msm
- bcm281xx: Remove use of seq_printf return value
- stmp3xxx_rtc_wdt + pnx4008_wdt: fix broken email addresses"
* git://www.linux-watchdog.org/linux-watchdog:
watchdog: stmp3xxx_rtc_wdt: fix broken email address
watchdog: pnx4008_wdt: fix broken email address
watchdog: octeon: use fixed length string for register names
watchdog: octeon: fix some trivial coding style issues
watchdog: octeon: convert to WATCHDOG_CORE API
watchdog: cadence: Remove Kconfig dependency on ARCH
ARM: msm: add watchdog entries to DT timer binding doc
ARM: qcom: add description of KPSS WDT for IPQ8064
watchdog: qcom: use timer devicetree binding
watchdog: bcm281xx: Remove use of seq_printf return value
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The watchdog has been reworked to use the same DT node as the timer.
This change is updating the device tree doc accordingly.
Signed-off-by: Mathieu Olivari <[email protected]>
Acked-by: Guenter Roeck <[email protected]>
Signed-off-by: Wim Van Sebroeck <[email protected]>
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Document cpuidle states of QCOM cpus. In addition to arm-idle-state
compatible string, the ARM idle state definition must define one of the
following compatible strings -
"qcom,idle-state-ret",
"qcom,idle-state-spc",
"qcom,idle-state-pc",
The compatibles helps the SPM platform driver to use the correct idle
function when the index to the idle state is passed to the platform
driver.
Signed-off-by: Lina Iyer <[email protected]>
Signed-off-by: Kumar Gala <[email protected]>
Signed-off-by: Olof Johansson <[email protected]>
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Update qcom,saw2 node bindings with compatible strings to identify nodes
that provides cpuidle functionality for a particular SoC. Remove
unused compatible strings.
Update examples for different SAW nodes.
Signed-off-by: Lina Iyer <[email protected]>
Signed-off-by: Kumar Gala <[email protected]>
Signed-off-by: Olof Johansson <[email protected]>
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This patch fix multiple words such as "the the" and "which which"
in Documentation/devicetree.
Signed-off-by: Masanari Iida <[email protected]>
Signed-off-by: Jonathan Corbet <[email protected]>
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The saw2 binding describes the SPM/AVS wrapper hardware used to
control the regulator supplying voltage to the Krait CPUs.
Cc: <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
Signed-off-by: Kumar Gala <[email protected]>
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The kpss acc binding describes the clock, reset, and power domain
controller for a Krait CPU.
Cc: <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
Signed-off-by: Kumar Gala <[email protected]>
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git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC platform updates from Olof Johansson:
"This branch contains part 1 of the platform updates for 3.10. Among
the highlights:
- Support for the new Atmel Cortex-A5 based platforms (SAMA5D3)
- New support for CSR SiRFatlas6 SoCs
- A handful of updates for NVidia T114 (a.k.a. Tegra 4)
- A bunch of updates for the shmobile platforms
- A handful of updates for davinci
- A few updates for Qualcomm MSM
- Plus a handful of other patches, defconfig updates, etc."
* tag 'soc-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (135 commits)
ARM: tegra: pm: fix build error w/o PM_SLEEP
ARM: davinci: ensure global variables are declared
ARM: davinci: sram.c: fix incorrect type in assignment
ARM: davinci: da8xx dt: make file local symbols static
ARM: davinci: da8xx: add remoteproc support
ARM: socfpga: Upgrade clk driver for socfpga to make use of dts clock entries
ARM: socfpga: Add clock entries into device tree
ARM: socfpga: Enable soft reset
ARM: EXYNOS: replace cpumask by the corresponding macro
ARM: EXYNOS: handle properly the return values
ARM: EXYNOS: factor out the idle states
ARM: OMAP4: Enable fix for Cortex-A9 erratas
ARM: OMAP2+: Export SoC information to userspace
ARM: OMAP2+: SoC name and revision unification
ARM: OMAP2+: Move common part of late init into common function
ARM: tegra: pm: remove duplicated include from pm.c
ARM: davinci: da850: override mmc DT node device name
ARM: davinci: da850: add mmc DT entries
mmc: davinci_mmc: add DT support
ARM: SAMSUNG: check processor type before cache restoration in resume
...
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The SSBI bus is exclusive to the Qualcomm MSM targets, and all SoCs
using it will be using device tree. Convert this driver to indentify
with device tree.
This makes the bus probing a good bit simpler, since the attaching of
child nodes can be represented directly in the devicetree, rather than
having to be inferred by name.
Signed-off-by: David Brown <[email protected]>
Signed-off-by: Greg Kroah-Hartman <[email protected]>
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The msm timer binding I wrote is bad. First off, the clock
frequency in the binding for the dgt is wrong. Software divides
down the input rate by 4 to achieve the rate listed in the
binding. We also treat each individual timer as a separate
hardware component, when in reality there is one timer block
(that may be duplicated per cpu) with multiple timers within it.
Depending on the version of the hardware there can be one or two
general purpose timers, status and divider control registers, and
an entirely different register layout.
In the next patch we'll need to know about the different register
layouts so that we can properly check the status register after
clearing the count. The current binding makes this complicated
because the general purpose timer's reg property doesn't indicate
where that status register is, and in fact it is beyond the size
of the reg property.
Clean all this up by just having one node for the timer hardware,
and describe all the interrupts and clock frequencies supported
while having one reg property that covers the entire timer
register region. We'll use the compatible field in the future to
determine different register layouts and if we should read the
status registers, etc.
Signed-off-by: Stephen Boyd <[email protected]>
Signed-off-by: David Brown <[email protected]>
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Add support to setup the MSM timer via information obtained from
the devicetree.
Signed-off-by: Stephen Boyd <[email protected]>
[[email protected]: Remove leading zeros]
Signed-off-by: David Brown <[email protected]>
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