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2023-11-28dt-bindings: arm/calxeda: drop unneeded quotesRob Herring1-1/+1
Drop unneeded quotes over simple string values to fix a soon to be enabled yamllint warning: [error] string value is redundantly quoted with any quotes (quoted-strings) Reviewed-by: Krzysztof Kozlowski <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Rob Herring <[email protected]>
2020-05-03dt-bindings: arm: Add Calxeda system registers json-schema bindingAndre Przywara1-0/+49
The Calxeda system registers are a collection of MMIO register controlling several more general aspects of the SoC. Beside for some power management tasks this node is also somewhat abused as the container for the clock nodes. Add a binding in DT schema format using json-schema. Signed-off-by: Andre Przywara <[email protected]> Signed-off-by: Rob Herring <[email protected]>
2020-05-03dt-bindings: arm: Convert Calxeda L2 cache controller to json-schemaAndre Przywara2-15/+42
Convert the L2-ECC controller binding to DT schema format using json-schema. This is indented to be just used for error reporting. Signed-off-by: Andre Przywara <[email protected]> Signed-off-by: Rob Herring <[email protected]>
2015-10-22dt-bindings: move Calxeda bindings to appropriate subsystemsRob Herring2-33/+0
Move the Calxeda memory controller and PHY bindings to appropriate subsystem directories. Signed-off-by: Rob Herring <[email protected]> Cc: Pawel Moll <[email protected]> Cc: Mark Rutland <[email protected]> Cc: Ian Campbell <[email protected]> Cc: Kumar Gala <[email protected]>
2013-11-04ARM: dts: calxeda: move memory-controller node out of ecx-common.dtsiRob Herring1-1/+3
The DDR controller is slightly different in ECX-2000 and ECX-1000, so we need to have different nodes for each platform. Signed-off-by: Rob Herring <[email protected]> [Device Tree documentation updated.] Signed-off-by: Robert Richter <[email protected]>
2012-09-13ata: add platform driver for Calxeda AHCI controllerMark Langsdorf1-0/+17
Calxeda highbank SATA phy has intermittent problems bringing up a link with Gen3 drives. Retrying the phy hard reset can work-around this issue, but each reset also disables spread spectrum support. The reset function also needs to reprogram the phy to enable spread spectrum support. Create a new driver based on ahci_platform to support the Calxeda Highbank SATA controller. Signed-off-by: Mark Langsdorf <[email protected]> Signed-off-by: Rob Herring <[email protected]> Signed-off-by: Jeff Garzik <[email protected]>
2012-06-27edac: add support for Calxeda highbank L2 cache eccRob Herring1-0/+15
Add support for L2 ECC on Calxeda highbank platform. Signed-off-by: Rob Herring <[email protected]> Signed-off-by: Mauro Carvalho Chehab <[email protected]>
2012-06-27edac: add support for Calxeda highbank memory controllerRob Herring1-0/+14
Add support for memory controller on Calxeda Highbank platforms. Highbank platforms support a single 4GB mini-DIMM with 1-bit correction and 2-bit detection. Signed-off-by: Rob Herring <[email protected]> Signed-off-by: Mauro Carvalho Chehab <[email protected]>
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