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2024-05-10dt-bindings: mfd: syscon: Add missing simple syscon compatiblesRob Herring1-12/+0
Add various "simple" syscon compatibles which were undocumented or still documented with old text bindings. apm,xgene-csw, apm,xgene-efuse, apm,xgene-mcb, apm,xgene-rb, fsl,ls1088a-reset, marvell,armada-3700-cpu-misc, mediatek,mt2712-pctl-a-syscfg, mediatek,mt6397-pctl-pmic-syscfg, and mediatek,mt8173-pctl-a-syscfg were all undocumented, but are in use already. Remove the old text binding docs for the others. Signed-off-by: Rob Herring <[email protected]> Reviewed-by: Krzysztof Kozlowski <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Lee Jones <[email protected]>
2020-03-31dt-bindings: Add missing 'additionalProperties: false'Rob Herring1-0/+2
Setting 'additionalProperties: false' is frequently omitted, but is important in order to check that there aren't extra undocumented properties in a binding. Ideally, we'd just add this automatically and make this the default, but there's some cases where it doesn't work. For example, if a common schema is referenced, then properties in the common schema aren't part of what's considered for 'additionalProperties'. Also, sometimes there are bus specific properties such as 'spi-max-frequency' that go into bus child nodes, but aren't defined in the child node's schema. So let's stick with the json-schema defined default and add 'additionalProperties: false' where needed. This will be a continual review comment and game of wack-a-mole. Signed-off-by: Rob Herring <[email protected]> Reviewed-by: Neil Armstrong <[email protected]> Acked-by: Mark Brown <[email protected]> Acked-by: Jonathan Cameron <[email protected]> Acked-by: Alexandru Ardelean <[email protected]> Reviewed-by: Benjamin Gaignard <[email protected]> Acked-by: Stephen Boyd <[email protected]> # clock Acked-by: Lee Jones <[email protected]>
2019-04-02dt-bindings: arm: socfpga: Add S10 System Manager bindingThor Thayer1-0/+12
Add the device tree bindings for the Stratix10 System Manager. Signed-off-by: Thor Thayer <[email protected]> Reviewed-by: Rob Herring <[email protected]> Reviewed-by: Arnd Bergmann <[email protected]> Signed-off-by: Lee Jones <[email protected]>
2018-12-13dt-bindings: altera: Convert clkmgr binding to json-schemaRob Herring2-11/+31
Convert Altera clkmgr to DT schema format using json-schema. Cc: Mark Rutland <[email protected]> Acked-by: Dinh Nguyen <[email protected]> Cc: [email protected] Signed-off-by: Rob Herring <[email protected]>
2018-05-12Documentation: dt: edac: Move Altera SOCFPGA EDAC fileThor Thayer1-268/+0
Move the Altera SOCFPGA EDAC file from bindings/arm/altera to bindings/edac. Signed-off-by: Thor Thayer <[email protected]> Requested-by: Rob Herring <[email protected]> Acked-by: Rob Herring <[email protected]> Cc: Mark Rutland <[email protected]> Cc: [email protected] Cc: linux-edac <[email protected]> Link: http://lkml.kernel.org/r/[email protected] Signed-off-by: Borislav Petkov <[email protected]>
2018-05-12Documentation: dt: socfpga: Add Stratix10 ECC Manager bindingThor Thayer1-0/+35
Add the device tree bindings needed to support the Stratix10 ECC Manager and SDRAM ECC. Signed-off-by: Thor Thayer <[email protected]> Reviewed-by: Rob Herring <[email protected]> Cc: Mark Rutland <[email protected]> Cc: [email protected] Cc: [email protected] Cc: [email protected] Cc: [email protected] Cc: linux-edac <[email protected]> Cc: [email protected] Cc: [email protected] Link: http://lkml.kernel.org/r/[email protected] Signed-off-by: Borislav Petkov <[email protected]>
2016-08-08Documentation: dt: socfpga: Add Arria10 SD-MMC EDAC bindingThor Thayer1-0/+19
Add the device tree bindings needed to support the Altera SD-MMC FIFO buffers EDAC on the Arria10 chip. Signed-off-by: Thor Thayer <[email protected]> Acked-by: Rob Herring <[email protected]> Cc: [email protected] Cc: [email protected] Cc: [email protected] Cc: linux-edac <[email protected]> Link: http://lkml.kernel.org/r/[email protected] Signed-off-by: Borislav Petkov <[email protected]>
2016-08-08Documentation: dt: socfpga: Add Arria10 QSPI EDAC bindingThor Thayer1-0/+16
Add the device tree bindings needed to support the Altera QSPI FIFO buffer on the Arria10 chip. Signed-off-by: Thor Thayer <[email protected]> Acked-by: Rob Herring <[email protected]> Cc: [email protected] Cc: [email protected] Cc: [email protected] Cc: linux-edac <[email protected]> Link: http://lkml.kernel.org/r/[email protected] Signed-off-by: Borislav Petkov <[email protected]>
2016-08-08Documentation: dt: socfpga: Add Arria10 USB EDAC bindingThor Thayer1-0/+15
Add the device tree bindings needed to support the Altera USB FIFO buffer on the Arria10 chip. Signed-off-by: Thor Thayer <[email protected]> Acked-by: Rob Herring <[email protected]> Cc: [email protected] Cc: [email protected] Cc: [email protected] Cc: linux-edac <[email protected]> Link: http://lkml.kernel.org/r/[email protected] Signed-off-by: Borislav Petkov <[email protected]>
2016-08-08Documentation: dt: socfpga: Add Arria10 DMA EDAC bindingThor Thayer1-0/+16
Add the device tree bindings needed to support the Altera DMA FIFO buffer on the Arria10 chip. Signed-off-by: Thor Thayer <[email protected]> Acked-by: Rob Herring <[email protected]> Cc: [email protected] Cc: [email protected] Cc: [email protected] Cc: linux-edac <[email protected]> Link: http://lkml.kernel.org/r/[email protected] Signed-off-by: Borislav Petkov <[email protected]>
2016-08-08Documentation: dt: socfpga: Add Arria10 NAND EDAC bindingThor Thayer1-0/+32
Add the device tree bindings needed to support the Altera NAND FIFO buffers on the Arria10 chip. Signed-off-by: Thor Thayer <[email protected]> Acked-by: Rob Herring <[email protected]> Cc: [email protected] Cc: [email protected] Cc: [email protected] Cc: linux-edac <[email protected]> Link: http://lkml.kernel.org/r/[email protected] Signed-off-by: Borislav Petkov <[email protected]>
2016-06-24Documentation: dt: socfpga: Add Arria10 Ethernet bindingThor Thayer1-0/+24
Add the device tree bindings needed to support the Altera Ethernet FIFO buffers on the Arria10 chip. Signed-off-by: Thor Thayer <[email protected]> Acked-by: Rob Herring <[email protected]> Cc: [email protected] Cc: [email protected] Cc: linux-edac <[email protected]> Link: http://lkml.kernel.org/r/[email protected] Signed-off-by: Borislav Petkov <[email protected]>
2016-06-07Documentation: dt: socfpga: Add interrupt-controller to ecc-managerThor Thayer1-1/+13
Designate the ECC Manager as an interrupt controller and add child interrupts. Signed-off-by: Thor Thayer <[email protected]> Acked-by: Rob Herring <[email protected]> Cc: [email protected] Cc: [email protected] Cc: [email protected] Cc: [email protected] Cc: [email protected] Cc: [email protected] Cc: linux-edac <[email protected]> Link: http://lkml.kernel.org/r/[email protected] Signed-off-by: Borislav Petkov <[email protected]>
2016-04-02Documentation: dt: socfpga: Add Altera Arria10 OCRAM bindingThor Thayer1-0/+10
Add the device tree bindings needed to support the Altera On-Chip RAM ECC on the Arria10 chip. Signed-off-by: Thor Thayer <[email protected]> Acked-by: Rob Herring <[email protected]> Cc: [email protected] Cc: [email protected] Cc: [email protected] Cc: [email protected] Cc: linux-edac <[email protected]> Link: http://lkml.kernel.org/r/[email protected] Signed-off-by: Borislav Petkov <[email protected]>
2016-03-29Documentation, dt, socfpga: Add Altera Arria10 L2 cache bindingThor Thayer1-0/+40
Add the device tree bindings needed to support the Altera L2 cache on the Arria10 chip. Since all the peripherals share IRQs, the IRQ fields are now in the ecc_manager. Signed-off-by: Thor Thayer <[email protected]> Acked-by: Rob Herring <[email protected]> Cc: [email protected] Cc: [email protected] Cc: [email protected] Cc: [email protected] Cc: linux-edac <[email protected]> Link: http://lkml.kernel.org/r/[email protected] Signed-off-by: Borislav Petkov <[email protected]>
2016-02-11ARM: dts: Add Altera L2 Cache and OCRAM EDAC entriesThor Thayer1-0/+49
Add the device tree entries and bindings needed to support the Altera L2 cache and On-Chip RAM EDAC. This patch relies upon an earlier patch to declare and setup On-chip RAM properly: 8b907c8b62ac ("arm: dts: socfpga: Add OCRAM node") Signed-off-by: Thor Thayer <[email protected]> Acked-by: Rob Herring <[email protected]> Cc: [email protected] Cc: Dinh Nguyen <[email protected]> Cc: [email protected] Cc: [email protected] Cc: Ian Campbell <[email protected]> Cc: [email protected] Cc: Kumar Gala <[email protected]> Cc: [email protected] Cc: [email protected] Cc: [email protected] Cc: linux-edac <[email protected]> Cc: Mark Rutland <[email protected]> Cc: [email protected] Cc: Pawel Moll <[email protected]> Cc: Rob Herring <[email protected]> Cc: Russell King <[email protected]> Link: http://lkml.kernel.org/r/[email protected] Signed-off-by: Borislav Petkov <[email protected]>
2015-06-26Merge tag 'armsoc-dt' of ↵Linus Torvalds1-0/+12
git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC DT updates from Kevin Hilman: "As usual, quite a few device-tree updates in ARM land. There was one minor churn in DTs due to relicensing under a dual-license, and lots of little additions of new peripherals, features etc, but nothing really exciting to call to your attention. Some higlights, focsuing on support for new SoCs and boards: - AT91: new boards: Overkiz, Acme Systems' Arietta G25 - tegra: HDA support - bcm: new platforms: Buffalo WXR-1900DHP, SmartRG SR400ac, ASUS RT-AC87U - mvebu: new platforms: Compulab CM-A510, Armada 385-based Linksys boards, DLink DNS-327L - OMAP: new platforms: Baltos IR5221, LogicPD Torpedo, Toby-Churchill SL50 - ARM: added support for Juno r1 board - sunxi: A33 SoC support; new boards: A23 EVB, SinA33, GA10H-A33, Mele A1000G - imx: i.MX7D SoC support; new boards: Armadeus Systems APF6, Gateworks GW5510, and aristainetos2 boards - hisilicon: hi6220 SoC support; new boards: 96boards hikey" * tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (462 commits) ARM: hisi: revert changes from hisi/hip04-dt branch ARM: nomadik: set proper compatible for accelerometer ARM64: juno: add GPIO keys ARM: at91/dt: sama5d4: fix dma conf for aes, sha and tdes nodes ARM: dts: Introduce STM32F429 MCU ARM: socfpga: dts: enable ethernet for Arria10 devkit ARM: dts: k2l: fix the netcp range size ARM: dts: k2e: fix the netcp range size ARM: dts: k2hk: fix the netcp range size ARM: dts: k2l-evm: Add device bindings for netcp driver ARM: dts: k2e-evm: Add device bindings for netcp driver ARM: dts: k2hk-evm: Add device bindings for netcp driver ARM: BCM5301X: Add DT for Asus RT-AC87U ARM: BCM5301X: add IRQ numbers for PCIe controller ARM: BCM5301X: add NAND flash chip description arm64: dts: Add dts files for Hisilicon Hi6220 SoC clk: hi6220: Document devicetree bindings for hi6220 clock arm64: hi6220: Document devicetree bindings for Hisilicon hi6220 SoC ARM: at91/dt: sama5d4ek: mci0 uses slot 0 ARM: at91/dt: kizbox: fix mismatch LED PWM device ...
2015-06-24arm: socfpga: dts: Add Arria10 SDRAM EDAC DTS supportThor Thayer1-1/+1
Add support for the Arria10 SDRAM EDAC. Update the bindings document for the new match string. Signed-off-by: Thor Thayer <[email protected]> Cc: Arnd Bergmann <[email protected]> Cc: [email protected] Cc: [email protected] Cc: [email protected] Cc: [email protected] Cc: [email protected] Cc: [email protected] Cc: linux-edac <[email protected]> Cc: [email protected] Cc: [email protected] Cc: [email protected] Cc: [email protected] Cc: [email protected] Link: http://lkml.kernel.org/r/[email protected] Signed-off-by: Borislav Petkov <[email protected]>
2015-06-02ARM: socfpga: dts: add sdram controller dt binding docAlan Tull1-0/+12
Add binding doc for Altera SOCFPGA SDRAM controller. Signed-off-by: Alan Tull <[email protected]> Signed-off-by: Dinh Nguyen <[email protected]>
2014-09-04arm: dts: Add Altera SDRAM EDAC bindings & devicetree entries.Thor Thayer1-0/+15
Add the Altera SDRAM EDAC bindings and device tree changes to the Altera SoC project. There was a discussion thread on whether this driver should be an mfd driver or just make use of syscon, which is already a mfd. Ultimately, the decision to use a simple syscon interface was reached.[1] [1] https://lkml.org/lkml/2014/7/30/514 Signed-off-by: Thor Thayer <[email protected]> Acked-by: Pavel Machek <[email protected]> [dinguyen] cleaned-up commit header and remove version history. Signed-off-by: Dinh Nguyen <[email protected]>
2014-05-05Documentation: dt: reset: move socfpga-resetSteffen Trumtrar1-13/+0
Instead of having the documentation for the socfpga-reset controller in a vendor specific directory, move it to the reset folder to all the other reset drivers. Signed-off-by: Steffen Trumtrar <[email protected]> Signed-off-by: Dinh Nguyen <[email protected]>
2014-05-05Documentation: dt: socfpga: add reset-cells propertySteffen Trumtrar1-0/+2
To be able to use the reset-controller framework, the property #reset-cells is mandatory. Signed-off-by: Steffen Trumtrar <[email protected]> Signed-off-by: Dinh Nguyen <[email protected]>
2013-04-14ARM: socfpga: Add clock entries into device treeDinh Nguyen1-0/+11
Adds the main PLL clock groups for SOCFPGA into device tree file so that the clock framework to query the clock and clock rates appropriately. $cat /sys/kernel/debug/clk/clk_summary clock enable_cnt prepare_cnt rate --------------------------------------------------------------------- osc1 2 2 25000000 sdram_pll 0 0 400000000 s2f_usr2_clk 0 0 66666666 ddr_dq_clk 0 0 200000000 ddr_2x_dqs_clk 0 0 400000000 ddr_dqs_clk 0 0 200000000 periph_pll 2 2 500000000 s2f_usr1_clk 0 0 50000000 per_base_clk 4 4 100000000 per_nand_mmc_clk 0 0 25000000 per_qsi_clk 0 0 250000000 emac1_clk 1 1 125000000 emac0_clk 0 0 125000000 main_pll 1 1 1600000000 cfg_s2f_usr0_clk 0 0 100000000 main_nand_sdmmc_clk 0 0 100000000 main_qspi_clk 0 0 400000000 dbg_base_clk 0 0 400000000 mainclk 0 0 400000000 mpuclk 1 1 800000000 smp_twd 1 1 200000000 Signed-off-by: Dinh Nguyen <[email protected]> Reviewed-by: Pavel Machek <[email protected]> Signed-off-by: Olof Johansson <[email protected]>
2013-02-11arm: socfpga: Add SMP support for actual socfpga harwareDinh Nguyen1-0/+2
Because the CPU1 start address is different for socfpga-vt and socfpga-cyclone5, we add code to use the correct CPU1 start addr. Signed-off-by: Dinh Nguyen <[email protected]> Signed-off-by: Pavel Machek <[email protected]> Cc: Russell King <[email protected]> Cc: Arnd Bergmann <[email protected]> Cc: Olof Johansson <[email protected]> Cc: Rob Herring <[email protected]> Cc: Grant Likely <[email protected]> Signed-off-by: Olof Johansson <[email protected]>
2012-10-26ARM: socfpga: Enable SMP for socfpgaDinh Nguyen2-0/+22
Enable SMP for the SOCFPGA platform. Signed-off-by: Pavel Machek <[email protected]> Signed-off-by: Dinh Nguyen <[email protected]> Reviewed-by: Rob Herring <[email protected]> Signed-off-by: Arnd Bergmann <[email protected]>
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