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2018-11-05drm/amdgpu: Remove useless csa gpu address in vmid0Rex Zhu2-3/+2
driver didn't use this address so far. Reviewed-by: Monk Liu <[email protected]> Signed-off-by: Rex Zhu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-11-05drm/amdgpu: fix gfx wptr for sdma v4Junwei Zhang1-9/+4
The wptr value will be shitfed when function returns. Remove the redundant shift and clean up. Signed-off-by: Junwei Zhang <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-11-05drm/amdgpu: disable page queue on SDMA for Vega12Junwei Zhang1-1/+2
It blocks most of sanity tests, so disable it for now. Tested-by: Chen Gong <[email protected]> Signed-off-by: Junwei Zhang <[email protected]> Acked-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-11-05drm/amdgpu: update smu firmware images for VI variants (v2)Alex Deucher2-5/+31
Some new variants require updated firmware. V2: add MODULE_FIRMWARE for new firmwares Reviewed-by: Huang Rui <[email protected]> (v1) Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-11-05drm/amd/display: Add condition to sync eDP SW status and HW statusLewis Huang6-0/+120
[Why] Need to disable EDP backlight when enter S4 with EDP only and resume from S4 with secondary only. [How] Align the real hw and sw state via vBios scratch register in function enable_accelerated_mode when resume from S4. Signed-off-by: Lewis Huang <[email protected]> Reviewed-by: Charlene Liu <[email protected]> Acked-by: Leo Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-11-05drm/amd/display: Remove the check to see if pp_display_cfg is changedFatemeh Darbehani1-2/+1
[Why] When going to full-screen mode commit_planes_for_stream tries to decrease dcf_deep_sleep value, but safe_to_lower is false, so we don't send the new value to SMU but dc context gets updated. Later when dc_post_update_surfaces_to_stream tries to lower dcf_ds when safe_to_lower is true, this check prevents the message from being sent. [How] Remove the check that compares new value with what is stored in dc_context. This check is not necessary as dcn1_update_clocks already checks if the value is different from the current dcf_dp value. Signed-off-by: Fatemeh Darbehani <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Leo Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-11-05drm/amd/display: remove CRTC_3D_STRUCTURE_V_UPDATE_MODE bit programming.Charlene Liu1-4/+2
[Description] This is based on HW programming guide update. Signed-off-by: Charlene Liu <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Leo Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-11-05drm/amd/display: Expose target backlight levelAnthony Koo2-0/+13
[Why] DM may want to understand any backlight optimizations applied, so DM needs a way to query from the HW both the real current backlight, which may be value during transition. And also target backlight, which may be after some backlight optimizations applied. [How] Add interface to query current and target backlight levels Target level may indicate backlight level after backlight optimization and reductions are applied. Signed-off-by: Anthony Koo <[email protected]> Reviewed-by: Krunoslav Kovac <[email protected]> Acked-by: Leo Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-11-05drm/amd/display: Guard against null stream_state in set_crc_sourceNicholas Kazlauskas1-0/+5
[Why] The igt@kms_plane@pixel-format-pipe tests can create a sequence where stream_state is NULL during amdgpu_dm_crtc_set_crc_source which results in a null pointer dereference. [How] Guard against stream_state being NULL before accessing its fields. This doesn't fix the root cause of the issue so a DRM_ERROR is generated to still fail the tests. Signed-off-by: Nicholas Kazlauskas <[email protected]> Reviewed-by: David Francis <[email protected]> Acked-by: Leo Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-11-05drm/amd/display: fix mirror rotation scaling mathDmytro Laktyushkin1-41/+24
Curretly dc will incorrectly calculate viewport when there is rotation or mirror being applied Signed-off-by: Dmytro Laktyushkin <[email protected]> Reviewed-by: Su Chung <[email protected]> Acked-by: Leo Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-11-05drm/amd/display: Retiring set_display_requirements in dm_pp_smu.h - part4Fatemeh Darbehani4-37/+37
[Why] In DCN we want direct DC to SMU calls, with minimal interference from pplib. The reason for each pp_smu interface mapping to 1 SMU message is so we can have the sequencing of different SMU message in DC and shared across different OS's. This will also simplify debugging as DAL owns this interaction and there's no confusion about division of ownership. [How] Part 4: Change clock units so they match the values PPLib sends to SMU. Signed-off-by: Fatemeh Darbehani <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Leo Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-11-05drm/amd/display: Remove program_csc_matrixKrunoslav Kovac4-49/+11
[Why] On DCN1/DCE, There are two functions programming OCSC: program_csc_matrix and program_output_csc. They do the same thing. [How] Consolidate to use only program_output_csc. Signed-off-by: Krunoslav Kovac <[email protected]> Reviewed-by: Aric Cyr <[email protected]> Acked-by: Leo Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-11-05drm/amd/display: Fix some backlight variable stylingAnthony Koo1-10/+8
variableNamingsLikeSo aren't to convention. use_this_instead. Signed-off-by: Anthony Koo <[email protected]> Reviewed-by: Aric Cyr <[email protected]> Acked-by: Leo Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-11-05drm/amd/display: Expand dc to use 16.16 bit backlightAnthony Koo7-79/+80
[Why] We want to increase precision for backlight setting. But DC interface takes 8 bit backlight level value only. [How] DMCU already takes 16 bit backlight level. Expand the DC interface to take 16.16 bit value. Max 32 bit backlight value (0xFFFF) will represent max backlight (100%) Signed-off-by: Anthony Koo <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Leo Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-11-05drm/amd/display: Remove some old TODO'sEric Bernstein1-6/+0
They are no longer relevant Signed-off-by: Eric Bernstein <[email protected]> Reviewed-by: Dmytro Laktyushkin <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Leo Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-11-05drm/amd/display: Initial documentation for AMDgpu DCLeo Li5-41/+320
[Why] Documentation is helpful for the community to understand our code. This change does some high-level documentation of some DM interfaces with DRM, and the amdgpu base driver. [How] An entry for AMDgpu DC has been added to Documentation/gpu/drivers.rst TOC. amdgpu-dc.rst is created to pull in inline doc-strings, which: - Provides an overview for "What is DM?" - Documents AMDgpu DM lifecyle - Documents IRQ management - Documents atomic_check and commit_tail interfaces Signed-off-by: Leo Li <[email protected]> Reviewed-by: David Francis <[email protected]> Acked-by: Leo Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-11-05drm/amd/display: Fix potential nullptr errorBhawanpreet Lakha1-0/+6
[Why] Fix surface/plane potential nullptr [How] add null check Signed-off-by: Bhawanpreet Lakha <[email protected]> Reviewed-by: Aric Cyr <[email protected]> Acked-by: Leo Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-11-05drm/amd/display: 3.2.04Steven Chiu1-1/+1
Signed-off-by: Steven Chiu <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Leo Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-11-05drm/amd/display: Fix up coverity issuesAric Cyr3-8/+7
[Why] Coverity found various high-impact issues that need resolving. [How] Fix some buffer overruns and uninitialized variables. Signed-off-by: Aric Cyr <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Leo Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-11-05drm/amd/display: remove interlace scaling adjustmentDmytro Laktyushkin1-9/+0
We do not need to adjust surface scaling when p2i is enabled and we do not support interlaced timing otherwise Signed-off-by: Dmytro Laktyushkin <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Leo Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-11-05drm/amd/display: Add missing pipes registers for VGA enable/disableNevenko Stupar1-0/+2
Signed-off-by: Nevenko Stupar <[email protected]> Reviewed-by: Aric Cyr <[email protected]> Acked-by: Leo Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-11-05drm/amd/display: fix dml max voltage stateDmytro Laktyushkin1-1/+2
Gabe's formula sometimes uses values from non-existent 'unsupported' state to do validation. This change adds this extra state so validation can work correctly. Signed-off-by: Dmytro Laktyushkin <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Leo Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-11-05drm/amd/display: Clip all remaining regamma points after first clipped pointSivapiriyanKumarasamy1-18/+26
[Why] All values computed in the gamma curve after the first upperbound clipped point will need to be clipped anyways. We can avoid unnecessary computations and potential fixed point overflow by instead clipping these values to 1 automatically. [How] Track if upper-bound clipping has been done, and clip all values after this threshold is reached without computing the output gamma point. Signed-off-by: SivapiriyanKumarasamy <[email protected]> Reviewed-by: Krunoslav Kovac <[email protected]> Acked-by: Leo Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-11-05drm/amd/display: 3.2.03SivapiriyanKumarasamy1-1/+1
Signed-off-by: SivapiriyanKumarasamy <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Reviewed-by: Steven Chiu <[email protected]> Acked-by: Leo Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-11-05drm/amd/display: Set gamma not working on MPO planesKrunoslav Kovac4-91/+180
[Why] Set gamma not working on certain planes in MPO configuration Root cause is that video format (YUV-420) isn't allowed for IGAM where gamma is applied. Fix is not easy though: 1. allowing will not work because IGAM is before ICSC so RGB gamma would be applied on YUV pixels. 2. Moving OS gamma to DGAM or RGAM resulted in weird artifacts. Ultimately the root cause for these artifacts was due to handling end points and the fact that YUV->RGB conversion will frequently "overshoot" FP 1.0 value. DCE has a single end point and slope, so we would take max. In nightlight mode, blue channel is reduced, sometimes to flat 0 line, but red is virtually unchanged. Any "overshot" in blue will be clipped to 1 (max R,G,B) instead of max blue value. [How] Fortunately, this can be fixed on DCN where we have end point and slope for all three color channels. We cannot fix this problem on DCE. Other things fixed: - switch (back) to using RGAM for OS gamma instead of IGAM - add coeffs for 709 YUV->RGB (we used RGB->YUV for both conversions) - switch color temperature method to scaled bradford - otherwise we would have clipping problems that caused us to switch to IGAM for OS gamma in the first place. - comments and some minor improvements - there are some more issues but they will be addressed in separate commits. Signed-off-by: Krunoslav Kovac <[email protected]> Reviewed-by: Aric Cyr <[email protected]> Acked-by: Leo Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-11-05drm/amdgpu: drop the remaining uses of ring idx in messagesChristian König3-8/+7
Consistently use the ring name instead. Signed-off-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-11-05drm/amdgpu: cleanup si_dma_ring_test_ibChristian König1-5/+2
Accidentially missed during the last cleanup. Signed-off-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-11-05drm/amdgpu: cleanup uvd_v6_0_ring_test_ringChristian König1-12/+5
Accidentially missed during the last cleanup. Signed-off-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-11-05drm/amdgpu: use ring name instead of idx in tracesChristian König1-7/+8
Further remove using the ring index in messages and traces. Signed-off-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-11-05drm/amdgpu: print an error when the parser can't be initializedSamuel Pitoiset1-1/+1
Similar to other error messages, might help for tracking down issues. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-11-05drm/scheduler: Add drm_sched_job_cleanupSharat Masetty7-4/+21
This patch adds a new API to clean up the scheduler job resources. This is primarliy needed in cases the job was created but was not queued to the scheduler queue. Additionally with this change, the layer which creates the scheduler job also gets to free up the job's resources and this entails moving the dma_fence_put(finished_fence) to the drivers ops free handler routines. Signed-off-by: Sharat Masetty <[email protected]> Reviewed-by: Christian König <[email protected]> Acked-by: Andrey Grodzovsky <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-11-05drm/amdgpu: remove messages from IB testsChristian König14-212/+80
We already print an error message that an IB test failed in the common code. Signed-off-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Andrey Grodzovsky <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-11-05drm/amdgpu: cleanup skipping IB test on KIQChristian König3-12/+3
Instead of hard coding the ring type in the function just never provide a test_ib callback. Additional to that remove the emit_ib callback to make sure the nobody ever tries to execute an IB on the KIQ. Signed-off-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Andrey Grodzovsky <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-11-05drm/amdgpu: cleanup amdgpu_ib_ring_testsChristian König1-16/+19
Test only initialized rings, use the ring name instead of the index in the error message and note on which device the error occured. Signed-off-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Andrey Grodzovsky <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-11-05drm/amdgpu: further ring test cleanupsChristian König16-249/+114
Move all error messages from IP specific code into the common helper. This way we now uses the ring name in the messages instead of the index and note which device is affected as well. Also cleanup error handling in the IP specific code and consequently use ETIMEDOUT when the ring test timed out. Signed-off-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Andrey Grodzovsky <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-11-05drm/amdgpu/amdkfd: clean up mmhub and gfxhub includesAlex Deucher4-7/+6
Use the appropriate mmhub and gfxhub headers rather than adding them to the gmc9 header. Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-11-05drm/amdgpu: Enable default GPU reset for dGPU on gfx8/9 v3Andrey Grodzovsky1-4/+26
After testing looks like these subset of ASICs has GPU reset working for the most part. Enable reset due to job timeout. v2: Switch from GFX version to ASIC type. v3: Fix identation Signed-off-by: Andrey Grodzovsky <[email protected]> Acked-by: Alex Deucher <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-11-05drm/amdgpu: Retire amdgpu_ring.ready flag v4Andrey Grodzovsky26-187/+129
Start using drm_gpu_scheduler.ready isntead. v3: Add helper function to run ring test and set sched.ready flag status accordingly, clean explicit sched.ready sets from the IP specific files. v4: Add kerneldoc and rebase. Signed-off-by: Andrey Grodzovsky <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-11-05drm/sched: Add boolean to mark if sched is ready to work v5Andrey Grodzovsky3-1/+17
Problem: A particular scheduler may become unsuable (underlying HW) after some event (e.g. GPU reset). If it's later chosen by the get free sched. policy a command will fail to be submitted. Fix: Add a driver specific callback to report the sched status so rq with bad sched can be avoided in favor of working one or none in which case job init will fail. v2: Switch from driver callback to flag in scheduler. v3: rebase v4: Remove ready paramter from drm_sched_init, set uncoditionally to true once init done. v5: fix missed change in v3d in v4 (Alex) Signed-off-by: Andrey Grodzovsky <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-11-05drm: Remove drm_global.{c,h} v2Thomas Zimmermann6-195/+1
The content of drm_global.{c,h} is obsolete. v2: rebase on dropping TTM functionality Signed-off-by: Thomas Zimmermann <[email protected]> Signed-off-by: Christian König <[email protected]> Reviewed-by: Junwei Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-11-05drm/ttm: initialize globals during device init (v2)Christian König27-521/+17
Make sure that the global BO state is always correctly initialized. This allows removing all the device code to initialize it. v2: fix up vbox (Alex) Signed-off-by: Christian König <[email protected]> Reviewed-by: Junwei Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-11-05drm/ttm: use a static ttm_bo_global instanceChristian König2-15/+31
As the name says we only need one global instance of ttm_bo_global. Just use a single exported instance which is save to initialize multiple times. Signed-off-by: Christian König <[email protected]> Reviewed-by: Junwei Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-11-05drm/ttm: make the device list mutex staticChristian König2-6/+9
This way it can protect the whole BO global state. Signed-off-by: Christian König <[email protected]> Reviewed-by: Junwei Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-11-05drm/ttm: use a static ttm_mem_global instanceChristian König29-380/+32
As the name says we only need one global instance of ttm_mem_global. Drop all the driver initialization and just use a single exported instance which is initialized during BO global initialization. Signed-off-by: Christian König <[email protected]> Reviewed-by: Junwei Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-11-05drm/amd/powerplay: remove duplicated includesYueHaibing5-8/+0
Remove some duplicated include. Signed-off-by: YueHaibing <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-11-05drm/radeon/kms: remove set but not used variable 'pll'YueHaibing1-10/+0
Fixes gcc '-Wunused-but-set-variable' warning: drivers/gpu/drm/radeon/radeon_legacy_tv.c: In function 'radeon_legacy_tv_init_restarts': drivers/gpu/drm/radeon/radeon_legacy_tv.c:435:21: warning: variable 'pll' set but not used [-Wunused-but-set-variable] struct radeon_pll *pll; It never used since introduction in commit 4ce001abafaf ("drm/radeon/kms: add initial radeon tv-out support.") Also remove related variables 'dev, rdev, radeon_crtc' Signed-off-by: YueHaibing <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-11-05drm/amdgpu: Added a few comments for gartOak Zeng2-0/+3
Signed-off-by: Oak Zeng <[email protected]> Reviewed-by: Christian Konig <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-11-05drm/amdkfd: Use functions from amdgpu to invalidate vmid in kfdYong Zhao1-36/+1
As part of the change, we stop taking the srbm lock, and start to use the same invalidation engine and software lock as amdgpu. Signed-off-by: Yong Zhao <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-11-05drm/amdgpu: Reorganize amdgpu_gmc_flush_gpu_tlb() for kfd to useYong Zhao6-20/+22
Add a flush_type parameter to that series of functions. Signed-off-by: Yong Zhao <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-11-05drm/amdkfd: Remove unnecessary register setting when invalidating tlb in kfdYong Zhao1-17/+0
Those register settings have been done in gfxhub_v1_0_program_invalidation() and mmhub_v1_0_program_invalidation(). Signed-off-by: Yong Zhao <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
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