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2022-09-13drm/amd/display: Avoid force minimal transaction in case of surface_count ↵JeromeHong1-5/+7
equal to 0 [why] Call commit_minimal_transition_state wrongly in case of surface_count equal to 0. [how] Add a condition to filter case of surface_count equal to 0. Tested-by: Daniel Wheeler <[email protected]> Reviewed-by: Aric Cyr <[email protected]> Acked-by: Pavle Kotarac <[email protected]> Signed-off-by: JeromeHong <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-09-13drm/amd/display: Don't adjust VRR unnecessarilyAric Cyr3-11/+3
[why] Do not need to spend time reprogramming DRR if there were no updates to the parameters. [how] Compare the current stream state to the requested one to determine if an update is required. In amdgpu_dm the timing_changed flag is set but never used so can remove it. Similarly, the stream update for VRR is done after dc_commit and should not update its adjust field until after the update is completed. The adjust field is managed by dc_stream_adjust_vmin_vmax and should not be manually updated in amdgpu_dm. Tested-by: Daniel Wheeler <[email protected]> Reviewed-by: Anthony Koo <[email protected]> Acked-by: Pavle Kotarac <[email protected]> Signed-off-by: Aric Cyr <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-09-13drm/amd/display: Adding log for spread_spectrum_infoLeo Chen1-0/+20
[Why & How] Enable logging for spread_spectrum_percentage in spread_spectrum_info to facilitate debugging for audio compliance issues Tested-by: Daniel Wheeler <[email protected]> Co-authored-by: Leo Chen <[email protected]> Reviewed-by: Charlene Liu <[email protected]> Acked-by: Pavle Kotarac <[email protected]> Signed-off-by: Leo Chen <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-09-13drm/amd/display: Limit user regamma to a valid valueYao Wang11-0/+4
[Why] For HDR mode, we get total 512 tf_point and after switching to SDR mode we actually get 400 tf_point and the rest of points(401~512) still use dirty value from HDR mode. We should limit the rest of the points to max value. [How] Limit the value when coordinates_x.x > 1, just like what we do in translate_from_linear_space for other re-gamma build paths. Tested-by: Daniel Wheeler <[email protected]> Reviewed-by: Krunoslav Kovac <[email protected]> Reviewed-by: Aric Cyr <[email protected]> Acked-by: Pavle Kotarac <[email protected]> Signed-off-by: Yao Wang1 <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-09-13drm/amd/display: add workaround for subvp cursor corruption for DCN32/321Aurabindo Pillai2-2/+4
[Why&How] Kernel does not have a means to tell the userspace to use software cursor. Due to lack of this functionality, reducing the max cursor size is the only way to ensure that power savings of Subview port feature is utilized for asics that support it. The workaround could be removed after cursor caching is fixed while a subviewport config is active. Tested-by: Daniel Wheeler <[email protected]> Reviewed-by: Alvin Lee <[email protected]> Acked-by: Pavle Kotarac <[email protected]> Signed-off-by: Aurabindo Pillai <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-09-13drm/amd/display: Added debug option for forcing subvp num waysLee, Alvin2-3/+9
[Description] Regkey option for forcing num ways for subvp for debug purposes Tested-by: Daniel Wheeler <[email protected]> Reviewed-by: Jun Lei <[email protected]> Acked-by: Pavle Kotarac <[email protected]> Signed-off-by: Alvin Lee <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-09-13drm/amd/display: Update viewport position for phantom pipesAlvin Lee5-2/+47
[Description] In some cases the viewport position of the main pipes can change without triggering a full update. In this case the subvp phantom viewports must be updated accordingly. Tested-by: Daniel Wheeler <[email protected]> Reviewed-by: Jun Lei <[email protected]> Acked-by: Pavle Kotarac <[email protected]> Signed-off-by: Alvin Lee <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-09-13drm/amd/display: Round cursor width up for MALL allocationTaimur Hassan2-2/+46
[Why & How] When calculating cursor size for MALL allocation, the cursor width should be the actual width rounded up to 64 alignment. Additionally, the bit depth should vary depending on color format. Tested-by: Daniel Wheeler <[email protected]> Reviewed-by: Alvin Lee <[email protected]> Acked-by: Pavle Kotarac <[email protected]> Signed-off-by: Taimur Hassan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-09-13drm/amd/display: Correct dram channel width for dcn314Duncan Ma3-0/+6
[Why] The interpretation of the number of memory channels differ by memory type, and this affects channel width for the DML input. [How] Set dram channel width according to memory type for dcn314. Tested-by: Daniel Wheeler <[email protected]> Reviewed-by: Nicholas Kazlauskas <[email protected]> Reviewed-by: Jun Lei <[email protected]> Acked-by: Pavle Kotarac <[email protected]> Signed-off-by: Duncan Ma <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-09-13drm/amd/display: Relax swizzle checks for video non-RGB formats on DCN314Nicholas Kazlauskas1-3/+1
[Why] HW can support the display swizzle modes for video, and those are preferable over standard or linear for decode use. [How] Remove the check for DCN314. Tested-by: Daniel Wheeler <[email protected]> Reviewed-by: Jun Lei <[email protected]> Acked-by: Pavle Kotarac <[email protected]> Signed-off-by: Nicholas Kazlauskas <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-09-13drm/amd/display: Hook up DCN314 specific dml implementationNicholas Kazlauskas3-1/+14
[Why & How] Add support for the DML314 functions and hook up DCN314 to use them. This has some necessary additions for calculating Max VSTARTUP for future features, but there's also some changes that we have to make for pixel format/swizzle support. That will come in a following patch to make this transition easier to bisect. Tested-by: Daniel Wheeler <[email protected]> Reviewed-by: Jun Lei <[email protected]> Acked-by: Pavle Kotarac <[email protected]> Signed-off-by: Nicholas Kazlauskas <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-09-13drm/amd/display: Enable dlg and vba compilation for dcn314Rodrigo Siqueira1-0/+3
We were not using the VBA and DLG files for DCN314, but the next sequence of changes for DCN314 will require those files. This commit adds the necessary files to the Makefile. Cc: Roman Li <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-09-13drm/amd/display: Fix compilation errors on DCN314Rodrigo Siqueira1-4/+5
We have some compilation errors in some DML files from DCN314 that we never noticed because we were not compiling some of the DML files. This commit fixes those syntax errors before we enable the compilation. Cc: Roman Li <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-09-13drm/amd/display: Fix divide by zero in DMLAric Cyr2-18/+16
[why] Incorrectly using MicroTileWidth instead of MacroTileWidth for calculations. [how] Remove all unused references to MicroTile and change them to MacroTile. Tested-by: Daniel Wheeler <[email protected]> Reviewed-by: Alvin Lee <[email protected]> Reviewed-by: Jun Lei <[email protected]> Acked-by: Pavle Kotarac <[email protected]> Signed-off-by: Aric Cyr <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-09-13drm/amd/display: Fixing DIG FIFO ErrorLeo Chen1-2/+1
[Why & How] DIG_FIFO_READ_START_LEVEL should only be set to default value (7) by software. Removed all instances of resetting the register to 0 Tested-by: Daniel Wheeler <[email protected]> Reviewed-by: Nicholas Kazlauskas <[email protected]> Acked-by: Pavle Kotarac <[email protected]> Signed-off-by: Leo Chen <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-09-13drm/amd/display: SW cursor fallback for SubVPAlvin Lee4-0/+8
[Description] Leverage SW cursor fall back for SubVP when the cursor is too big. We want to take advantage of being able to fallback to SW cursor when possible because it's not worth it to disable MCLK switching because the cursor is slightly too big. Tested-by: Daniel Wheeler <[email protected]> Reviewed-by: Aurabindo Pillai <[email protected]> Acked-by: Pavle Kotarac <[email protected]> Signed-off-by: Alvin Lee <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-09-13drm/amd/display: Assign link type before check dsc workaround.JinZe.Xu1-1/+2
[Why] link type is not assigned before check dpia_mst_dsc_always_on conditions. Tested-by: Daniel Wheeler <[email protected]> Reviewed-by: Wenjing Liu <[email protected]> Acked-by: Pavle Kotarac <[email protected]> Signed-off-by: JinZe.Xu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-09-13drm/amd/display: Reverted DSC programming sequence changeNagulendran, Iswara2-13/+13
[HOW&WHY] Revert a previous commit by moving DSC programming back to before link enablement. Tested-by: Daniel Wheeler <[email protected]> Reviewed-by: Jayendran Ramani <[email protected]> Acked-by: Pavle Kotarac <[email protected]> Signed-off-by: Nagulendran, Iswara <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-09-13drm/amd/display: Update MBLK calculation for SubVPAlvin Lee2-8/+54
[Description] Update MBLK calculation according to hardware doc. For DCC case we were not allocation enough MALL due to an inaccurate MBLK calculation. Tested-by: Daniel Wheeler <[email protected]> Reviewed-by: Jun Lei <[email protected]> Acked-by: Pavle Kotarac <[email protected]> Signed-off-by: Alvin Lee <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-09-13drm/amd/display: Revert "Fallback to SW cursor if SubVP + cursor too big"Aurabindo Pillai1-5/+0
This reverts commit a4f1b04216023ff0f4cd89328b59ee6890248130 since returning false in case of SubVP results in no cursor being visible on desktop as there is no sw cursor fallback path on all platforms. Tested-by: Daniel Wheeler <[email protected]> Reviewed-by: Alvin Lee <[email protected]> Acked-by: Pavle Kotarac <[email protected]> Signed-off-by: Aurabindo Pillai <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-09-13drm/amd/display: Correct I2C register offsetChris Park3-10/+25
[Why] I2C register name starts with 1, unlike other registers that start with 0. This creates a problem with the new register macro refactoring when I2C HW objects are created in an array. [How] Correct I2C register offset by making a new macro to account for array offset. Tested-by: Daniel Wheeler <[email protected]> Reviewed-by: Charlene Liu <[email protected]> Acked-by: Pavle Kotarac <[email protected]> Signed-off-by: Chris Park <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-09-13drm/amd/display: Optimizations for DML mathAric Cyr9-61/+53
[why] Conditionals in the DML basic math functions significantly impact mode enumeration. [how] Remove conditionals for floor/ceil operations which are used frequently in DML and add an assertion for invalid callers using zero granuality. Fix existing callers that rely on 0 granularity. Tested-by: Daniel Wheeler <[email protected]> Reviewed-by: Nevenko Stupar <[email protected]> Acked-by: Pavle Kotarac <[email protected]> Signed-off-by: Aric Cyr <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-09-13drm/amdgpu: Skip reset error status for psp v13_0_0Candice Li1-1/+2
No need to reset error status since only umc ras supported on psp v13_0_0. Signed-off-by: Candice Li <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-09-13drm/amdgpu: Add EEPROM I2C address for smu v13_0_0Candice Li1-0/+10
Set correct EEPROM I2C address for smu v13_0_0. Signed-off-by: Candice Li <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-09-13drm/amdgpu: added support for ras driver loadingJohn Clements4-0/+29
copy ras driver to psp if present Signed-off-by: John Clements <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-09-13drm/amdgpu: add HDP remap functionality to nbio 7.7Alex Deucher1-0/+9
Was missing before and would have resulted in a write to a non-existant register. Normally APUs don't use HDP, but other asics could use this code and APUs do use the HDP when used in passthrough. Reviewed-by: Lijo Lazar <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-09-13drm/amdgpu/display: remove unneeded "default n" optionsJingyu Wang1-2/+0
Remove "default n" options. If the "default" line is removed, it defaults to 'n'. Signed-off-by: Jingyu Wang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-09-13drm/amd/display: fix repeated words in commentsJilin Yuan1-1/+1
Delete the redundant word 'in'. Signed-off-by: Jilin Yuan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-09-13drm/amdgpu: cleanup coding style in amdgpu_amdkfd_gpuvm.cJingyu Wang1-1/+3
Fix everything checkpatch.pl complained about in amdgpu_amdkfd_gpuvm.c Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Jingyu Wang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-09-13drm/amdgpu: cleanup coding style in amdgpu_amdkfd.cJingyu Wang1-0/+2
Fix everything checkpatch.pl complained about in amdgpu_amdkfd.c Signed-off-by: Jingyu Wang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-09-13drm/amdgpu: cleanup coding style in amdgpu_sync.c fileJingyu Wang1-1/+3
This is a patch to the amdgpu_sync.c file that fixes some warnings found by the checkpatch.pl tool Signed-off-by: Jingyu Wang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-09-13drm/amdgpu: cleanup coding style in amdgpu_acpi.cJingyu Wang1-4/+7
Fix everything checkpatch.pl complained about in amdgpu_acpi.c Signed-off-by: Jingyu Wang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-09-13drm/amdgpu: Remove the unneeded result variablezhang songyi1-4/+1
Return the sdma_v6_0_start() directly instead of storing it in another redundant variable. Reported-by: Zeal Robot <[email protected]> Signed-off-by: zhang songyi <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-09-13drm/radeon: Remove the unneeded result variableye xingchen1-4/+1
Return the value radeon_drm_ioctl() directly instead of storing it in another redundant variable. Reported-by: Zeal Robot <[email protected]> Signed-off-by: ye xingchen <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-09-13drm/radeon/ci_dpm: Remove the unneeded result variableye xingchen1-4/+2
Return the value ci_load_smc_ucode() directly instead of storing it in another redundant variable. Reported-by: Zeal Robot <[email protected]> Signed-off-by: ye xingchen <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-09-13drm/amd/display: remove possible condition with no effect (if == else)Yang Li1-4/+0
Conditional statements have no effect to next process.So remove it. Link: https://bugzilla.openanolis.cn/show_bug.cgi?id=2028 Reported-by: Abaci Robot <[email protected]> Signed-off-by: Yang Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-09-13drm/amd/display: Simplify bool conversionYang Li1-1/+1
The result of relational operation is Boolean, and the question mark expression is redundant. Link: https://bugzilla.openanolis.cn/show_bug.cgi?id=2027 Reported-by: Abaci Robot <[email protected]> Signed-off-by: Yang Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-09-13drm/amd/display: clean up some inconsistent indentingsYang Li1-2/+2
This if statement is the content of the for statement above it. It should be indented. Link: https://bugzilla.openanolis.cn/show_bug.cgi?id=2026 Reported-by: Abaci Robot <[email protected]> Signed-off-by: Yang Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-09-13drm/amdgpu: Fix hive reference count leakVignesh Chander1-2/+2
both get_xgmi_hive and put_xgmi_hive can be skipped since the reset domain is not necessary for VF Signed-off-by: Vignesh Chander <[email protected]> Reviewed-by: Shaoyun Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-09-13drm/amdkfd: Migrate in CPU page fault use current mmPhilip Yang1-1/+2
migrate_vma_setup shows below warning because we don't hold another process mm mmap_lock. We should use current vmf->vma->vm_mm instead, the caller already hold current mmap lock inside CPU page fault handler. WARNING: CPU: 10 PID: 3054 at include/linux/mmap_lock.h:155 find_vma Call Trace: walk_page_range+0x76/0x150 migrate_vma_setup+0x18a/0x640 svm_migrate_vram_to_ram+0x245/0xa10 [amdgpu] svm_migrate_to_ram+0x36f/0x470 [amdgpu] do_swap_page+0xcfe/0xec0 __handle_mm_fault+0x96b/0x15e0 handle_mm_fault+0x13f/0x3e0 do_user_addr_fault+0x1e7/0x690 Fixes: e1f84eef313f ("drm/amdkfd: handle CPU fault on COW mapping") Signed-off-by: Philip Yang <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-09-13drm/amdgpu: change the alignment size of TMR BO to 1MYang Wang2-1/+2
align TMR BO size TO tmr size is not necessary, modify the size to 1M to avoid re-create BO fail when serious VRAM fragmentation. v2: add new macro PSP_TMR_ALIGNMENT for TMR BO alignment size Signed-off-by: Yang Wang <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-09-13drm/amdgpu: Enable full reset when RAS is supported on gc v11_0_0Candice Li1-0/+1
Enable full reset for RAS supported configuration on gc v11_0_0. v2: simplify the code. Signed-off-by: Candice Li <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-09-13drm/amdgpu: Rely on MCUMC_STATUS for umc v8_10 correctable error counter onlyCandice Li1-9/+3
Only check MCUMC_STATUS for CE counter for umc v8_10. Signed-off-by: Candice Li <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-09-13drm/amd/display: update header filesCharlene Liu3-19/+2
[why] update header files, and remove not used register access marco Reviewed-by: Hansen Dsouza <[email protected]> Acked-by: Pavle Kotarac <[email protected]> Signed-off-by: Charlene Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-09-13drm/amdkfd: Remove prefault before migrating to VRAMPhilip Yang3-31/+5
Prefaulting potentially allocates system memory pages before a migration. This adds unnecessary overhead. Instead we can skip unallocated pages in the migration and just point migrate->dst to a 0-initialized VRAM page directly. Then the VRAM page will be inserted to the PTE. A subsequent CPU page fault will migrate the page back to system memory. Signed-off-by: Philip Yang <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-09-13drm/amdkfd: handle CPU fault on COW mappingPhilip Yang1-13/+29
If CPU page fault in a page with zone_device_data svm_bo from another process, that means it is COW mapping in the child process and the range is migrated to VRAM by parent process. Migrate the parent process range back to system memory to recover the CPU page fault. Signed-off-by: Philip Yang <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-09-13amd/amdkfd: fix repeated words in commentswangjianli1-1/+1
Delete the redundant word 'to'. Signed-off-by: wangjianli <[email protected]> Signed-off-by: Felix Kuehling <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-09-13drm/amdgpu: Use per device reset_domain for XGMI on sriov configurationshaoyunl2-23/+34
For SRIOV configuration, host driver control the reset method(either FLR or heavier chain reset). The host will notify the guest individually with FLR message if individual GPU within the hive need to be reset. So for guest side, no need to use hive->reset_domain to replace the original per device reset_domain Signed-off-by: shaoyunl <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-09-13drm/amd/amdgpu: update GC 10.3.0 pwrdecTom St Denis2-1/+1558
The 10.3 GC headers were missing most of the pwrdec block. This patch adds the registers and bits present in the 10.1 header but based on the contents of the 10.3 specs. Signed-off-by: Tom St Denis <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-09-13drm/amdkfd: Fix CRIU restore op due to doorbell offsetRajneesh Bhardwaj3-0/+16
Recently introduced change to allocate doorbells only when the first queue is created or mapped for CPU / GPU access, did not consider Checkpoint Restore scenario completely. This fix allows the CRIU restore operation by extending the doorbell optimization to CRIU restore scenario. Fixes: 16f0013157bf ("drm/amdkfd: Allocate doorbells only when needed") Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Rajneesh Bhardwaj <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
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