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authorLeo Chen <[email protected]>2022-08-24 15:34:24 -0400
committerAlex Deucher <[email protected]>2022-09-13 14:32:59 -0400
commit94caa423e2b5658626382ba9d98f989a47bd2b8a (patch)
treed610f1730f5d19618fd8de096a3615f7f4886bbf
parentfe77d95f7a7f2f567205ce747124efa465fb01be (diff)
drm/amd/display: Fixing DIG FIFO Error
[Why & How] DIG_FIFO_READ_START_LEVEL should only be set to default value (7) by software. Removed all instances of resetting the register to 0 Tested-by: Daniel Wheeler <[email protected]> Reviewed-by: Nicholas Kazlauskas <[email protected]> Acked-by: Pavle Kotarac <[email protected]> Signed-off-by: Leo Chen <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
-rw-r--r--drivers/gpu/drm/amd/display/dc/dcn314/dcn314_dio_stream_encoder.c3
1 files changed, 1 insertions, 2 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_dio_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_dio_stream_encoder.c
index e3351ddc566c..06d8638db696 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_dio_stream_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_dio_stream_encoder.c
@@ -67,8 +67,7 @@ static void enc314_disable_fifo(struct stream_encoder *enc)
{
struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
- REG_UPDATE_2(DIG_FIFO_CTRL0, DIG_FIFO_ENABLE, 0,
- DIG_FIFO_READ_START_LEVEL, 0);
+ REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_ENABLE, 0);
}
static void enc314_dp_set_odm_combine(