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2014-09-03drm/tegra: Renaming DP training vswing pre emph definesSonika Jindal1-2/+2
Rename the defines to have levels instead of values for vswing and pre-emph levels as the values may differ in other scenarios like low vswing of eDP1.4 where the values are different. Done using following cocci patch for each define: @@ @@ # define DP_TRAIN_VOLTAGE_SWING_400 (0 << 0) + # define DP_TRAIN_VOLTAGE_SWING_LEVEL_0 (0 << 0) ... Signed-off-by: Sonika Jindal <[email protected]> Acked-by: Dave Airlie <[email protected]> Acked-by: Thierry Reding <[email protected]> Signed-off-by: Daniel Vetter <[email protected]>
2014-09-03drm/radeon: Renaming DP training vswing pre emph definesSonika Jindal1-2/+2
Rename the defines to have levels instead of values for vswing and pre-emph levels as the values may differ in other scenarios like low vswing of eDP1.4 where the values are different. Done using following cocci patch for each define: @@ @@ # define DP_TRAIN_VOLTAGE_SWING_1200 (3 << 0) + # define DP_TRAIN_VOLTAGE_SWING_LEVEL_3 (0 << 0) ... Signed-off-by: Sonika Jindal <[email protected]> Acked-by: Alex Deucher <[email protected]> Acked-by: Dave Airlie <[email protected]> Signed-off-by: Daniel Vetter <[email protected]>
2014-09-03drm/gma500: Renaming DP training vswing pre emph definesSonika Jindal2-10/+10
Rename the defines to have levels instead of values for vswing and pre-emph levels as the values may differ in other scenarios like low vswing of eDP1.4 where the values are different. Done using following cocci patch for each define: @@ @@ # define DP_TRAIN_VOLTAGE_SWING_400 (0 << 0) + # define DP_TRAIN_VOLTAGE_SWING_LEVEL_0 (0 << 0) ... Signed-off-by: Sonika Jindal <[email protected]> Acked-by: Dave Airlie <[email protected]> Signed-off-by: Daniel Vetter <[email protected]>
2014-09-03drm/exynos: Renaming DP training vswing pre emph definesSonika Jindal1-2/+2
Rename the defines to have levels instead of values for vswing and pre-emph levels as the values may differ in other scenarios like low vswing of eDP1.4 where the values are different. Done using following cocci patch for each define: @@ @@ # define DP_TRAIN_VOLTAGE_SWING_400 (0 << 0) + # define DP_TRAIN_VOLTAGE_SWING_LEVEL_0 (0 << 0) ... Signed-off-by: Sonika Jindal <[email protected]> Acked-by: Dave Airlie <[email protected]> Acked-by: Jingoo Han <[email protected]> Signed-off-by: Daniel Vetter <[email protected]>
2014-09-03drm: Renaming DP training vswing pre emph definesSonika Jindal1-0/+8
Adding new defines, older one will be removed in the last patch in the series. This is to rename the defines to have levels instead of values for vswing and pre-emph levels as the values may differ in other scenarios like low vswing of eDP1.4 where the values are different. Done using following cocci patch for each define: @@ @@ # define DP_TRAIN_VOLTAGE_SWING_400 (0 << 0) + # define DP_TRAIN_VOLTAGE_SWING_LEVEL_0 (0 << 0) ... Cc: [email protected] Signed-off-by: Sonika Jindal <[email protected]> Acked-by: Dave Airlie <[email protected]> Signed-off-by: Daniel Vetter <[email protected]>
2014-09-03drm/i915: debug sink dpms aux errors also on enableJani Nikula1-2/+4
Signed-off-by: Jani Nikula <[email protected]> Signed-off-by: Daniel Vetter <[email protected]>
2014-09-03drm/i915: Don't call intel_plane_restore() when the prop value didn't changeVille Syrjälä1-0/+3
No point in calling intel_plane_restore() in .set_property() if the value didn't change. More importantly this papers over a bug where the current primary plane code forgets to update the user coordinates we store under intel_plane unless the primary plane .update_plane() hook is actually called. This means we have 0 in the coordinates straight after boot and any call to intel_restore_plane() (such as from restore_fbdev_mode()) will actually turn off the primary plane. This mess needs to be fixed properly but that's a bigger task and the first step there is killing off intel_pipe_set_base() and just calling the primary plane .update_plane() hook. For the immediate problem of black screen after boot this small patch is enough to hide it. The problem originates from these two commits: commit 3a5f87c286515c54ff5c52c3e64d0c522b7570c0 Author: Thomas Wood <[email protected]> Date: Wed Aug 20 14:45:00 2014 +0100 drm: fix plane rotation when restoring fbdev configuration commit d91a2cb8e5104233c02bbde539bd4ee455ec12ac Author: Sonika Jindal <[email protected]> Date: Fri Aug 22 14:06:04 2014 +0530 drm/i915: Add 180 degree primary plane rotation support Cc: Thomas Wood <[email protected]> Cc: Sonika Jindal <[email protected]> Tested-by: Mika Kuoppala <[email protected]> Signed-off-by: Ville Syrjälä <[email protected]> Reviewed-by: Damien Lespiau <[email protected]> Tested-by: Alan Stern <[email protected]> Signed-off-by: Daniel Vetter <[email protected]>
2014-09-03drm: i915: reduce memory footprint when debuggingAndy Shevchenko1-5/+1
There is no need to use hex_dump_to_buffer() since we have a kernel helper to dump up to 64 bytes just via printk(). In our case the actual size is 15 bytes. Signed-off-by: Andy Shevchenko <[email protected]> Reviewed-by: Jani Nikula <[email protected]> [danvet: Add cast since %*ph expects and int for the size parameter.] Signed-off-by: Daniel Vetter <[email protected]>
2014-09-03drm/i915: Don't use WaGsvRC0ResidenncyMethod on chvVille Syrjälä1-2/+2
WaGsvRC0ResidenncyMethod is for vlv, it doesn't deal with chv appropriately (eg. doesn't limit rps values to even numbers). Fix a typo in the w/a name while at it. Cc: Deepak S <[email protected]> Signed-off-by: Ville Syrjälä <[email protected]> Reviewed-by: Deepak S <[email protected]> Signed-off-by: Daniel Vetter <[email protected]>
2014-09-03drm/i915: Preserve VGACNTR bits from the BIOSVille Syrjälä2-1/+9
My Fujistsu-Siemens Lifebook S6010 doesn't like to resume from S3 unless VGACNTR has been restore to the original value. The BIOS value in this case was 0x0124008E. Setting the "VGA disable" bit doesn't interfere with the S3 resume fortunately. Signed-off-by: Ville Syrjälä <[email protected]> Tested-by: Thomas Richter <[email protected]> Signed-off-by: Daniel Vetter <[email protected]>
2014-09-03drm/i915: Add pipe B force quirk for 830MVille Syrjälä2-12/+28
830M has problems when some of the pipes are disabled. Namely if a plane, DVO port etc. is currently assigned to a disabled pipe, it can't moved to the other pipe until the current pipe is also enabled. To keep things simple just leave both pipes running all the time. Ideally I think should turn the pipes off if neither is active, and when either becomes active we enable both. But that would reuquire proper atomic modeset support, and probably a bit of extra care in the order things get enabled. v2: Reorder wrt. double wide handling changes Signed-off-by: Ville Syrjälä <[email protected]> Tested-by: Thomas Richter <[email protected]> Signed-off-by: Daniel Vetter <[email protected]>
2014-09-03Revert "drm/i915: Nuke pipe A quirk on i830M"Ville Syrjälä1-0/+3
830 really does want the pipe A quirk. The planes and ports don't react to any register writes unless the pipe currently attached to them is running, so it's impossible to move them to the other pipe unless both pipes are running. Also it's documented that the DPLL must be enabled on both pipes whenever it's needed. This reverts commit ac6696d3236bd61503f89a1a99680fd7894d5d53. Signed-off-by: Ville Syrjälä <[email protected]> Tested-by: Thomas Richter <[email protected]> Signed-off-by: Daniel Vetter <[email protected]>
2014-09-03drm/i915: Check pixel clock in ns2501 mode_valid hookVille Syrjälä1-3/+3
The vbt on my Fujitsu-Siemens Lifebook S6010 provides two 800x600 modes, 60Hz and 56Hz. The magic register values we have correspond to the 60Hz mode, and as I don't know how one would trick the VGA BIOS to set up the 56Hz mode we can't get the magic values for the orther mode. So when checking whether a mode is valid also check the pixel clock so that we filter out the 56Hz variant. Signed-off-by: Ville Syrjälä <[email protected]> Reviewed-by: Thomas Richter <[email protected]> Signed-off-by: Daniel Vetter <[email protected]>
2014-09-03drm/i915: Init important ns2501 registersVille Syrjälä1-0/+10
In my earlier rewrite I missed a few important registers. Thomas Richter noticed that they're needed to make his machine resume correctly. Looks like IEGD does a one time init of these three registers. We don't have a good one time init place in the ns2501 driver, so let's just stick them into the .mode_set() hook and see if that helps things along. Signed-off-by: Ville Syrjälä <[email protected]> Reviewed-by: Thomas Richter <[email protected]> Signed-off-by: Daniel Vetter <[email protected]>
2014-09-03drm/i915: Rewrite ns2501 driver a bitVille Syrjälä1-204/+325
Try to use the same programming sequence as used by the IEGD driver. Also shovel the magic register values into a big static const array. The register values are actually the based on what the BIOS programs on the Fujitsu-Siemens Lifebook S6010. IEGD seemed to have hardcoded register values (which also enabled the scaler for 1024x768 mode). However those didn't actually work so well on the S6010. Possibly the pipe timings that got used didn't match the ns2501 configuration. Signed-off-by: Ville Syrjälä <[email protected]> Reviewed-by: Thomas Richter <[email protected]> Signed-off-by: Daniel Vetter <[email protected]>
2014-09-03drm/i915: Kill useless ns2501_dump_regsVille Syrjälä1-17/+0
Signed-off-by: Ville Syrjälä <[email protected]> Reviewed-by: Thomas Richter <[email protected]> Signed-off-by: Daniel Vetter <[email protected]>
2014-09-03drm/i915: Don't call DVO mode_set hook on DPMS changesVille Syrjälä1-4/+0
Calling the mode_set hook on DPMS changes doesn't seem to be necessary for ns2501. Just drop it. Signed-off-by: Ville Syrjälä <[email protected]> Tested-by: Thomas Richter <[email protected]> Signed-off-by: Daniel Vetter <[email protected]>
2014-09-03drm/i915: Enable DVO between mode_set and dpms hooksVille Syrjälä1-2/+3
To more closely match the IEGD ns2501 driver behaviour, call the mode_set hook while the DVO port is still disabled, then enable the DVO port, and finally call the dpms hook. Signed-off-by: Ville Syrjälä <[email protected]> Tested-by: Thomas Richter <[email protected]> Signed-off-by: Daniel Vetter <[email protected]>
2014-09-03drm/i915: ns2501 is on DVOBVille Syrjälä1-1/+1
On Fujitsu-Siememens S6010 the ns2501 chip is hooked up to DVOB instead of DVOC. FIXME: Maybe need to dig out the correct DVO port from VBT Signed-off-by: Ville Syrjälä <[email protected]> Tested-by: Thomas Richter <[email protected]> Signed-off-by: Daniel Vetter <[email protected]>
2014-09-03drm/i915: Disable double wide even when leaving the pipe onVille Syrjälä1-6/+14
Disable double wide even if the pipe quirk compels us to leave the pipe running. Double wide has certain implications for the plane assignments so best keep it off. Also helps resuming from S3 on the Fujitsu-Siemens Lifebook S6010 when double wide was enabled prior to suspend. We do leave the pixel clock ticking at the original rate which would require double wide to be enabled. But since the planes are all disabled I'm hoping that the overly fast clock won't cause any problems. Seems to be fine so far. v2: Disable double wide also when turning the pipe off v3: Reorder wrt. force pipe B quirk Signed-off-by: Ville Syrjälä <[email protected]> Tested-by: Thomas Richter <[email protected]> Signed-off-by: Daniel Vetter <[email protected]>
2014-09-03drm/i915: Pass intel_crtc to intel_disable_pipe() and intel_wait_for_pipe_off()Ville Syrjälä2-21/+17
Just pass the intel_crtc around instead of dev_priv+pipe. Also make intel_wait_for_pipe_off() static since it's only used in intel_display.c. Signed-off-by: Ville Syrjälä <[email protected]> Tested-by: Thomas Richter <[email protected]> Signed-off-by: Daniel Vetter <[email protected]>
2014-09-03drm/i915: Idle unused rings on gen2/3 during init/resumeVille Syrjälä2-0/+42
gen2/3 platforms have a boatload of rings we're not using. On my 830 the BIOS/hw can leave some of those "active" after resume which will prevent c3 entry. The ring is apparently considered active whenever head != tail even if the ring is disabled. Disable and clear all such unused ringbuffers on init/resume. Signed-off-by: Ville Syrjälä <[email protected]> Signed-off-by: Daniel Vetter <[email protected]>
2014-09-03drm/i915: Disable trickle feed for gen2/3Ville Syrjälä2-0/+14
My 830 is unhappy with trickle feed enabled. The symptom is that the image on the screen shifts a bit to right occasionally. The BIOS initially disables trickle feed, but it gets reset during suspend, so we need to re-disable it ourselves. Juse disable it always. Also disable it for all other gen2/3 platforms since we disable it for all more recent platforms as well (until HSW that is). At least my 855 doesn't seem to mind us doing this. I don't have gen3 hardware to test that. Signed-off-by: Ville Syrjälä <[email protected]> Signed-off-by: Daniel Vetter <[email protected]>
2014-09-03drm/i915: Fix gen2 planes B and C max watermark valueVille Syrjälä1-4/+20
The max watermark value for gen2 planes B and C is 0x1f, instead of the 0x3f that plane A uses. Also check against the max even if the pipe is disabled since the FIFO size exceeds the plane B and C max watermark value. Signed-off-by: Ville Syrjälä <[email protected]> Tested-by: Thomas Richter <[email protected]> Signed-off-by: Daniel Vetter <[email protected]>
2014-09-03drm/i915: make fbdev initialization asynchronous v2Jesse Barnes3-5/+9
This gets us out of our init code and out to userspace quite a bit faster, but does open us up to some bugs given the state of our init time locking. v2: switch to async_schedule (Chris) check with lockdep, seems happy (Jesse) move hotplug enable flag set to fbdev_initial_config (Jesse) Signed-off-by: Jesse Barnes <[email protected]> Reviewed-by: Chris Wilson <[email protected]> [danvet: Rebase on top of the dev_priv->enable_hotplug_processing removal.] Signed-off-by: Daniel Vetter <[email protected]>
2014-09-03drm/i915: Init some CHV workarounds via LRIs in ring->init_context()Ville Syrjälä2-16/+44
Follow the BDW example and apply the workarounds touching registers which are saved in the context image through LRIs in the new ring->init_context() hook. This makes Mesa much happier and eg. glxgears doesn't hang after the first frame. Cc: Arun Siluvery <[email protected]> Signed-off-by: Ville Syrjälä <[email protected]> [danvet: Add missing wa table initialization to avoid a functional conflict with Arun's wa table debugfs support.] Reviewed-by: "Barbalho, Rafael" <[email protected]> Signed-off-by: Daniel Vetter <[email protected]>
2014-09-03drm/i915: trivial: remove unneed set to NULLGustavo Padovan1-1/+0
At this point of the code the obj var is already NULL, so we don't need to set it again to NULL. Signed-off-by: Gustavo Padovan <[email protected]> Reviewed-by: Jani Nikula <[email protected]> Signed-off-by: Daniel Vetter <[email protected]>
2014-09-03drm/i915: Warn about odd rps values on CHVVille Syrjälä1-0/+11
CHV wants even rps opcodes so print a warning of the min/max/rpe/rp1 values are odd, and warn if an odd value slips through to valleyview_set_rps() and truncate it to an even value. Also add a comment to chv_freq_opcode() to make sure no one changes the code without considering this requirement. Signed-off-by: Ville Syrjälä <[email protected]> Reviewed-by: Deepak S <[email protected]> [danvet: Help git along in applying the patch, somehow it silently ended up in the vlv init_gt_powersave function.] Signed-off-by: Daniel Vetter <[email protected]>
2014-09-03MAINTAINERS: Update Daniel Vetter's email addressDaniel Vetter1-1/+1
Signed-off-by: Daniel Vetter <[email protected]>
2014-09-03drm/i915/bdw: Render state init for ExeclistsOscar Mateo6-39/+135
The batchbuffer that sets the render context state is submitted in a different way, and from different places. We needed to make both the render state preparation and free functions outside accesible, and namespace accordingly. This mess is so that all LR, LRC and Execlists functionality can go together in intel_lrc.c: we can fix all of this later on, once the interfaces are clear. v2: Create a separate ctx->rcs_initialized for the Execlists case, as suggested by Chris Wilson. Signed-off-by: Oscar Mateo <[email protected]> v3: Setup ring status page in lr_context_deferred_create when the default context is being created. This means that the render state init for the default context is no longer a special case. Execute deferred creation of the default context at the end of logical_ring_init to allow the render state commands to be submitted. Fix style errors reported by checkpatch. Rebased. Signed-off-by: Thomas Daniel <[email protected]> Signed-off-by: Daniel Vetter <[email protected]>
2014-09-03drm/i915/bdw: BDW Software TurboDaisy Sun5-39/+241
BDW supports GT C0 residency reporting in constant time unit. Driver calculates GT utilization based on C0 residency and adjusts RP frequency up/down accordingly. For offscreen workload specificly, set frequency to RP0. Offscreen task is not restricted by frame rate, it can be executed as soon as possible. Transcoding and serilized workload between CPU and GPU both need high GT performance, RP0 is a good option in this case. RC6 will kick in to compensate power consumption when GT is not active. v2: Rebase on recent drm-intel-nightly v3: Add flip timerout monitor, when no flip is deteced within 100ms, set frequency to RP0. Signed-off-by: Daisy Sun <[email protected]> [torourke: rebased on latest and resolved conflict] Signed-off-by: Tom O'Rourke <Tom.O'[email protected]> Acked-by: Jesse Barnes <[email protected]> Signed-off-by: Daniel Vetter <[email protected]>
2014-09-03drm/i915: Populate mem_freq in init_gt_powerwave()Ville Syrjälä2-53/+43
init_clock_gating() is too late to read out the mem_freq. We already want to print out the GPU MHz numbers before it's called. Move the mem_freq setup to init_gt_powersave(). v2: Also kill the CHV_CZ_CLOCK_FREQ_MODE_* defines Signed-off-by: Ville Syrjälä <[email protected]> Reviewed-by: Deepak S <[email protected]> Signed-off-by: Daniel Vetter <[email protected]>
2014-09-03drm/i915: s, fb->bits_per_pixel/8, pixel_size, in primary plane codeVille Syrjälä1-4/+4
Use the pixel_size we got from drm_format_plane_cpp() instead of fb->bits_per_pixel/8 when computing the primary plane page/linear offsets. Avoids a few divs and makes the code more future proof against funky pixel formats where bits_per_pixel isn't well defined. This is what we already did in the sprite code. Note that the relevant sprite patch was commit ca320ac456099c29290568353d924157e626ede9 Author: Chris Wilson <[email protected]> Date: Wed Dec 19 12:14:22 2012 +0000 drm/i915: Use pixel size for computing linear offsets into a sprite This change was required on sprites because they support yuv formats which have fb->bits_per_pixel undefined. Signed-off-by: Ville Syrjälä <[email protected]> Reviewed-by: Chris Wilson <[email protected]> [danvet: Add Chris' software archeology as a note to the commit message.] Signed-off-by: Daniel Vetter <[email protected]>
2014-09-03drm/i915: Don't dereference fb when disabling primary planeVille Syrjälä1-6/+14
During driver init we may not have a valid framebuffer for the primary plane even though the plane is enabled due to failed BIOS fb takeover. This means we have to avoid dereferencing the fb in .update_primary_plane() when disabling the plane. The introduction of the primary plane rotation in commit d91a2cb8e5104233c02bbde539bd4ee455ec12ac Author: Sonika Jindal <[email protected]> Date: Fri Aug 22 14:06:04 2014 +0530 drm/i915: Add 180 degree primary plane rotation support caused a regression by trying to look up the pixel format before we can be sure there's a valid fb available. This isn't entirely unsurprising since the rotation patches originally predate the change to the primary plane code that calls .update_primary_plane() also when disabling the plane: commit fdd508a6419217cce28213f3c9bd27c02a0d4c71 Author: Ville Syrjälä <[email protected]> Date: Fri Aug 8 21:51:11 2014 +0300 drm/i915: Call .update_primary_plane in intel_{enable, disable}_primary_hw_plane() v2: Warn but don't blow up when trying to enable a plane w/o an fb (Chris) Cc: Sonika Jindal <[email protected]> Signed-off-by: Ville Syrjälä <[email protected]> Reviewed-by: Chris Wilson <[email protected]> Signed-off-by: Daniel Vetter <[email protected]>
2014-09-03drm/i915/bdw: Export workaround data to debugfsArun Siluvery3-0/+77
The workarounds that are applied are exported to a debugfs file; this is used to verify their state after the test case (reset or suspend/resume etc). This patch is only required to support i-g-t. Signed-off-by: Arun Siluvery <[email protected]> Signed-off-by: Daniel Vetter <[email protected]>
2014-09-03drm/i915/bdw: Apply workarounds in render ring init functionArun Siluvery4-48/+87
For BDW workarounds are currently initialized in init_clock_gating() but they are lost during reset, suspend/resume etc; this patch moves the WAs that are part of register state context to render ring init fn otherwise default context ends up with incorrect values as they don't get initialized until init_clock_gating fn. v2: Add workarounds to golden render state This method has its own issues, first of all this is different for each gen and it is generated using a tool so adding new workaround and mainitaining them across gens is not a straightforward process. v3: Use LRIs to emit these workarounds (Ville) Instead of modifying the golden render state the same LRIs are emitted from within the driver. v4: Use abstract name when exporting gen specific routines (Chris) For: VIZ-4092 Signed-off-by: Arun Siluvery <[email protected]> Reviewed-by: Ville Syrjälä <[email protected]> Signed-off-by: Daniel Vetter <[email protected]>
2014-09-03drm/i915: FBC flush nuke for BDWRodrigo Vivi4-1/+22
According to spec FBC on BDW and HSW are identical without any gaps. So let's copy the nuke and let FBC really start compressing stuff. Without this patch we can verify with false color that nothing is being compressed. With the nuke in place and false color it is possible to see false color debugs. Unfortunatelly on some rings like BCS on BDW we have to avoid Bits 22:18 on LRIs due to a high risk of hung. So, when using Blt ring for frontbuffer rend cache would never been cleaned and FBC would stop compressing buffer. One alternative is to cache clean on software frontbuffer tracking. v2: Fix rebase conflict. v3: Do not clean cache on BCS ring. Instead use sw frontbuffer tracking. Signed-off-by: Rodrigo Vivi <[email protected]> Signed-off-by: Daniel Vetter <[email protected]>
2014-09-03drm/i915/ddi: use struct for ddi buf translation tablesJani Nikula1-92/+97
Try to avoid confusion with ARRAY_SIZE()/2 and hdmi_level*2. Signed-off-by: Jani Nikula <[email protected]> [danvet: Resolve silent patch conflict (didn't even fail to build) with with Sonika's preceding patch to use the hsw_ddi_translations_fdi table to driver the fdi link training iteration loop. Also drop the double-write loop Damien spotted.] Signed-off-by: Daniel Vetter <[email protected]>
2014-09-03drm/i915: Rename defines for selection of ddi buffer translation slotSonika Jindal3-34/+16
Renaming the HSW-specific macros for ddi buffer translation slot to denote the slot and not the vswing/pre-emph values as they are platform-dependent. This patch is based on top of the patch series for renaming the DP training vswing/pre-emph defines: http://lists.freedesktop.org/archives/intel-gfx/2014-August/050407.html v2: Creating single macro with argument for slot number (Damien) v3: Adding macro for num of translation entries (Damien) Signed-off-by: Sonika Jindal <[email protected]> Reviewed-by: Damien Lespiau <[email protected]> Signed-off-by: Daniel Vetter <[email protected]>
2014-09-03drm/i915/dp: debug log whether backlight is being enabled or disabledJani Nikula1-1/+2
Signed-off-by: Jani Nikula <[email protected]> Signed-off-by: Daniel Vetter <[email protected]>
2014-09-03drm/i915/bdw: Let the memory controller do all the swizzlingDamien Lespiau1-1/+8
Previously, it was possible for the GPU memory accesses to be swizzled to try to optimize the fetches for tiled buffers. This swizzling was on top of what the memory controller in the uncore already does. With broadwell, we drop that GPU side swizzling, and the corresponding initialization in 3 units (GAM, GT, DE). All those bits are reserved, as specs put it: Before Gen8, there was a historical configuration control field to swizzle address bit[6] for in X/Y tiling modes. This was set in three different places: TILECTL[1:0], ARB_MODE[5:4], and DISP_ARB_CTL[14:13]" For Gen8 the swizzle fields are all reserved, and the CPU's memory controller performs all address swizzling modifications. This also means that user space doesn't have to manually swizzle when accessing tiled buffers from the CPU, and so we always return I915_BIT_6_SWIZZLE_NONE from i915_gem_detect_bit_6_swizzle(), which short-circuits the initialization of the registers mentionned above in i915_gem_init_swizzling(). v2: Refine the explanation a bit more (Daniel) v3: Make it BDW+ specific (Steve) Cc: Steve Aarnio <[email protected]> Signed-off-by: Damien Lespiau <[email protected]> [danvet: Keep the actual code to set the tiling bits for now, in case some bios escaped to the wild that uses this - we'd need it for fastboot.] Signed-off-by: Daniel Vetter <[email protected]>
2014-09-03drm/i915: Add "Intel Corporation" as module authorDamien Lespiau1-0/+1
Signed-off-by: Damien Lespiau <[email protected]> Signed-off-by: Daniel Vetter <[email protected]>
2014-09-03drm/i915: Don't use a define when it's clearer to just put the valueDamien Lespiau2-3/+2
Instead of going through hoops, just put the driver author directly as DRM_AUTHOR() argument. This will also make it consistent when we add Intel to the list. Signed-off-by: Damien Lespiau <[email protected]> Signed-off-by: Daniel Vetter <[email protected]>
2014-09-03drm/i915: improve assert_panel_unlockedJani Nikula1-7/+20
Fix assert_panel_unlocked for vlv/chv, and improve it a bit for non-LVDS. Also don't pretend it works for DDI. There's still work to do to get this right for eDP on PCH platforms, but this is a start. v2: WARN_ON(HAS_DDI) Reviewed-by: Ville Syrjälä <[email protected]> Signed-off-by: Jani Nikula <[email protected]> Signed-off-by: Daniel Vetter <[email protected]>
2014-09-03drm/i915/bdw: Add BDW support in the i915 debugfs entryVedang Patel1-1/+1
The patch introduces fixes for the debugfs attributes emitted by the i915 driver for GEN8. Currently, it is not emitting the correct attributes which include the status of RC6 states. Change-Id: Ib2068a0cac9a5wq3f228e547fa1a097ad369d242df Signed-off-by: Vedang Patel <[email protected]> Signed-off-by: Daniel Vetter <[email protected]>
2014-09-03drm/i915: Differentiate between LLC or snooped for the userChris Wilson4-7/+11
Rather than describing an object as either "snooped or LLC", we can do better as we should know what machine we are running on! Signed-off-by: Chris Wilson <[email protected]> Reviewed-by: Ville Syrjälä <[email protected]> Signed-off-by: Daniel Vetter <[email protected]>
2014-09-03drm/i915: send PCI_D3hot adapter opregion message on BDW RPM suspendPaulo Zanoni1-6/+22
On BDW we're seeing a problem that after we runtime resume, the outputs connected to DDI C are not detected: they don't appear in the SDEISR register and GMBUS transactions don't work. They stop working at the moment we call intel_opregion_notify_adapter() during runtime suspend, but they don't go back to work when we call the same function during runtime resume. They only work after we do a modeset and call intel_opregion_notify_encoder(), but this point is already too late. While debugging, I tried to pass PCI_D3hot which is the value that matches the spec, and it seems to have solved the problem. I couldn't find any explanation of why this solves the problem, but there's also no documented explanation - besides our code and git log - of why Haswell should use PCI_D1, so keep this for now in order to keep BDW runtime PM working. Also add a comment to point the fact that there's no spec documenting all the weirdness involved here. Cc: [email protected] Testcase: igt/pm_rpm/drm-resources-equal Testcase: igt/pm_rpm/i2c Signed-off-by: Paulo Zanoni <[email protected]> Reviewed-by: Damien Lespiau <[email protected]> Signed-off-by: Daniel Vetter <[email protected]>
2014-09-03drm/i915: rename gen8_init_clock_gating to broadwell_init_clock_gatingPaulo Zanoni1-2/+2
Because CHV uses cherryview_init_clock_gating instead of gen8_init_clock_gating. Signed-off-by: Paulo Zanoni <[email protected]> Reviewed-by: Damien Lespiau <[email protected]> Signed-off-by: Daniel Vetter <[email protected]>
2014-09-03drm/i915: call lpt_init_clock_gating on BDW tooPaulo Zanoni1-0/+2
Because BDW has WPT, which is equivalent to LPT. This is just like the CPT/PPT case. Signed-off-by: Paulo Zanoni <[email protected]> Reviewed-by: Damien Lespiau <[email protected]> Signed-off-by: Daniel Vetter <[email protected]>
2014-09-03drm/i915: fix panel unlock register maskJani Nikula1-1/+1
Use the correct mask for the unlock bits. In theory this could have lead to incorrect asserts but this is unlikely in practise. Signed-off-by: Jani Nikula <[email protected]> Reviewed-by: Paulo Zanoni <[email protected]> Reviewed-by: Ville Syrjälä <[email protected]> Signed-off-by: Daniel Vetter <[email protected]>
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