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2013-04-04ARM: dt: Add references to tegra_car clocksPeter De Schrijver3-3/+7
Add references to tegra_car clocks for the basic device nodes. Also remove the clock-frequency property of the serial node as the UART driver can now use the clock framework to obtain the frequency. Signed-off-by: Peter De Schrijver <[email protected]> Acked-by: Mike Turquette <[email protected]> Signed-off-by: Stephen Warren <[email protected]>
2013-04-04clk: tegra: devicetree match for nvidia,tegra114-carPeter De Schrijver2-0/+7
Signed-off-by: Peter De Schrijver <[email protected]> Acked-by: Mike Turquette <[email protected]> Signed-off-by: Stephen Warren <[email protected]>
2013-04-04clk: tegra: Implement clocks for Tegra114Peter De Schrijver2-0/+2086
Implement clocks for Tegra114. Signed-off-by: Peter De Schrijver <[email protected]> Acked-by: Mike Turquette <[email protected]> Signed-off-by: Stephen Warren <[email protected]>
2013-04-04ARM: tegra: Define Tegra114 CAR bindingPeter De Schrijver1-0/+303
The device tree binding models Tegra114 CAR (Clock And Reset) as a single monolithic clock provider. Signed-off-by: Peter De Schrijver <[email protected]> Acked-by: Mike Turquette <[email protected]> Signed-off-by: Stephen Warren <[email protected]>
2013-04-04clk: tegra: Workaround for Tegra114 MSENC problemPeter De Schrijver2-0/+11
Workaround a hardware bug in MSENC during clock enable. Signed-off-by: Peter De Schrijver <[email protected]> Acked-by: Mike Turquette <[email protected]> Signed-off-by: Stephen Warren <[email protected]>
2013-04-04clk: tegra: Add flags to tegra_clk_periph()Peter De Schrijver4-10/+14
We will need some tegra peripheral clocks with the CLK_IGNORE_UNUSED flag, most notably mselect, which is a bridge between AXI and most peripherals. Signed-off-by: Peter De Schrijver <[email protected]> Acked-by: Mike Turquette <[email protected]> Signed-off-by: Stephen Warren <[email protected]>
2013-04-04clk: tegra: Add new fields and PLL types for Tegra114Peter De Schrijver2-1/+888
Tegra114 introduces new PLL types. This requires new clocktypes as well as some new fields in the pll structure. Signed-off-by: Peter De Schrijver <[email protected]> Acked-by: Mike Turquette <[email protected]> Signed-off-by: Stephen Warren <[email protected]>
2013-04-04clk: tegra: move from a lock bit idx to a lock maskPeter De Schrijver4-25/+25
PLLC2 and PLLC3 on Tegra114 have separate phaselock and frequencylock bits. So switch to a lock mask to be able to test both at the same time. Signed-off-by: Peter De Schrijver <[email protected]> Acked-by: Mike Turquette <[email protected]> Signed-off-by: Stephen Warren <[email protected]>
2013-04-04clk: tegra: Add PLL post divider tablePeter De Schrijver4-6/+59
Some PLLs in Tegra114 don't use a power of 2 mapping for the post divider. Introduce a table based approach and switch PLLU to it. Signed-off-by: Peter De Schrijver <[email protected]> Acked-by: Mike Turquette <[email protected]> Signed-off-by: Stephen Warren <[email protected]>
2013-04-04clk: tegra: introduce TEGRA_PLL_HAS_LOCK_ENABLEPeter De Schrijver2-0/+7
Tegra114 PLLC2 and PLLC3 don't have a lock enable bit. The lock bits are always functional. Signed-off-by: Peter De Schrijver <[email protected]> Acked-by: Mike Turquette <[email protected]> Signed-off-by: Stephen Warren <[email protected]>
2013-04-04clk: tegra: Add TEGRA_PLL_BYPASS flagPeter De Schrijver2-4/+10
Not all PLLs in Tegra114 have a bypass bit. Adapt the common code to only use this bit when available. Signed-off-by: Peter De Schrijver <[email protected]> Acked-by: Mike Turquette <[email protected]> Signed-off-by: Stephen Warren <[email protected]>
2013-04-04clk: tegra: Refactor PLL programming codePeter De Schrijver4-293/+356
Refactor the PLL programming code to make it useable by the new PLL types introduced by Tegra114. The following changes were done: * Split programming the PLL into updating m,n,p and updating cpcon * Move locking from _update_pll_cpcon() to clk_pll_set_rate() * Introduce _get_pll_mnp() helper * Move check for identical m,n,p values to clk_pll_set_rate() * struct tegra_clk_pll_freq_table will always contain the values as defined by the hardware. * Simplify the arguments to clk_pll_wait_for_lock() * Split _tegra_clk_register_pll() Signed-off-by: Peter De Schrijver <[email protected]> Acked-by: Mike Turquette <[email protected]> Signed-off-by: Stephen Warren <[email protected]>
2013-04-04clk: tegra: provide dummy cpu car opsPeter De Schrijver1-1/+2
tegra_boot_secondary() relies on some of the car ops. This means having an uninitialized tegra_cpu_car_ops will lead to an early boot panic. Providing a dummy struct avoids this and makes adding Tegra114 clock support in a bisectable way a lot easier. Signed-off-by: Peter De Schrijver <[email protected]> Acked-by: Mike Turquette <[email protected]> Signed-off-by: Stephen Warren <[email protected]>
2013-04-04clk: tegra: defer application of init tableStephen Warren6-2/+29
The Tegra clock driver is initialized during the ARM machine descriptor's .init_irq() hook. It can't be initialized earlier, since dynamic memory usage is required. It can't be initialized later, since the .init_timer() hook needs the clocks initialized. However, at this time, udelay() doesn't work. The Tegra clock initialization table may enable some PLLs. Enabling a PLL may require usage of udelay(). Hence, this can't happen right when the clock driver is initialized. To solve this, separate the clock driver initialization from the clock table processing, so they can execute at separate times. Signed-off-by: Stephen Warren <[email protected]>
2013-04-04clk: tegra: Fix cdev1 and cdev2 IDsPrashant Gaikwad3-4/+4
Correct IDs for cdev1 and cdev2 are 94 and 93 respectively. Signed-off-by: Prashant Gaikwad <[email protected]> [swarren: split into separate driver and device-tree patches] Signed-off-by: Stephen Warren <[email protected]>
2013-04-04clk: tegra: Make gr2d and gr3d clocks children of pll_cThierry Reding2-0/+4
By default these clocks are children of pll_m, but in downstream kernels they are reparented to pll_c. While at it, decrease their frequencies to 300 MHz because the defaults aren't in the specified range. gr2d can reportedly run at much higher frequencies, but 300 MHz works and is a more conservative default. Signed-off-by: Thierry Reding <[email protected]> Acked-by: Mike Turquette <[email protected]> Acked-By: Peter De Schrijver <[email protected]> Signed-off-by: Stephen Warren <[email protected]>
2013-04-04clk: tegra: Export peripheral reset functionsThierry Reding1-0/+3
The tegra_periph_reset_assert() and tegra_periph_reset_deassert() functions can be used by drivers to reset peripherals. In order to allow such drivers to be built as modules, export the functions. Note that this restores the status quo as the functions were exported before the move to the drivers/clk tree. Signed-off-by: Thierry Reding <[email protected]> Acked-by: Mike Turquette <[email protected]> Signed-off-by: Stephen Warren <[email protected]>
2013-04-04clk: tegra: Fix periph_clk_to_bit macroYen Lin1-1/+1
The parameter name should be "gate", not "periph". This worked, however, because it happens that everywhere periph_clk_to_bit is called, "gate" was in the local scope. Signed-off-by: Yen Lin <[email protected]> Signed-off-by: Andrew Chew <[email protected]> Reviewed-by: Thierry Reding <[email protected]> Reviewed-by: Prashant Gaikwad <[email protected]> Acked-by: Peter De Schrijver <[email protected]> Acked-by: Mike Turquette <[email protected]> Signed-off-by: Stephen Warren <[email protected]>
2013-04-04Merge remote-tracking branch 'linaro_mturquette_linux/clk-for-3.10' into ↵Stephen Warren25-130/+1622
for-3.10/clk
2013-04-04Merge branch 'for-3.10/soc' into for-3.10/clkStephen Warren43-405/+1045
2013-04-04Merge branch 'omap-gpmc-for-v3.10-take2' of git://github.com/jonhunter/linux ↵Tony Lindgren10-309/+831
into omap-for-v3.10/gpmc
2013-04-04arm: zynq: Move timer to generic locationMichal Simek6-1/+23
Move zynq timer out of mach folder to generic location and enable it. Signed-off-by: Michal Simek <[email protected]>
2013-04-04arm: zynq: Do not use xilinx specific function namesMichal Simek1-106/+106
Remove all xilinx specific names from the driver because this is generic driver for cadence ttc. xttc->ttc ttcps->ttc ... No functional changes in this driver. Signed-off-by: Michal Simek <[email protected]>
2013-04-04arm: zynq: Move timer to clocksource interfaceMichal Simek3-26/+21
Use clocksource timer initialization. Signed-off-by: Michal Simek <[email protected]>
2013-04-04arm: zynq: Use standard timer bindingMichal Simek4-122/+195
Use cdns,ttc because this driver is Cadence Rev06 Triple Timer Counter and everybody can use it without xilinx specific function name or probing. Also use standard dt description for timer and also prepare for moving to clocksource initialization. Signed-off-by: Michal Simek <[email protected]>
2013-04-04clk: exynos5250: register display block gate clocks to common clock frameworkLeela Krishna Amudala2-1/+15
Add gate clocks for fimd, mie, dsim, dp, mixer and hdmi. Register it to common clock framework. Signed-off-by: Leela Krishna Amudala <[email protected]> Signed-off-by: Kukjin Kim <[email protected]>
2013-04-04clk: exynos4: Add support for SoC-specific register save listTomasz Figa5-8/+39
This patch extends suspend/resume support for SoC-specific registers to handle differences in register sets on particular SoCs. Signed-off-by: Tomasz Figa <[email protected]> Signed-off-by: Kyungmin Park <[email protected]> Reviewed-by: Thomas Abraham <[email protected]> Acked-by: Mike Turquette <[email protected]> Signed-off-by: Kukjin Kim <[email protected]>
2013-04-04clk: exynos4: Add missing registers to suspend save listTomasz Figa1-0/+33
This patch adds missing clock control registers to the list of registers that should be saved across system suspend. Signed-off-by: Tomasz Figa <[email protected]> Signed-off-by: Kyungmin Park <[email protected]> Reviewed-by: Thomas Abraham <[email protected]> Acked-by: Mike Turquette <[email protected]> Signed-off-by: Kukjin Kim <[email protected]>
2013-04-04clk: exynos4: Remove E4X12 prefix from SRC_DMC registerTomasz Figa1-2/+2
This register is present on all Exynos4 SoCs and so the prefix is misleading. Signed-off-by: Tomasz Figa <[email protected]> Signed-off-by: Kyungmin Park <[email protected]> Reviewed-by: Thomas Abraham <[email protected]> Acked-by: Mike Turquette <[email protected]> Signed-off-by: Kukjin Kim <[email protected]>
2013-04-04clk: exynos4: Add E4210 prefix to GATE_IP_PERIR registerTomasz Figa1-8/+8
This definition is specific for Exynos4210 (which has another location than the same register on Exynos4x12 SoCs) and so needs appropriate prefix. Signed-off-by: Tomasz Figa <[email protected]> Signed-off-by: Kyungmin Park <[email protected]> Reviewed-by: Thomas Abraham <[email protected]> Acked-by: Mike Turquette <[email protected]> Signed-off-by: Kukjin Kim <[email protected]>
2013-04-04clk: exynos4: Add E4210 prefix to LCD1 clock registersTomasz Figa1-11/+11
This patch adds E4210 prefix to all registers related to LCD1 clock domain, because they are present only on Exynos4210. Signed-off-by: Tomasz Figa <[email protected]> Signed-off-by: Kyungmin Park <[email protected]> Reviewed-by: Thomas Abraham <[email protected]> Acked-by: Mike Turquette <[email protected]> Signed-off-by: Kukjin Kim <[email protected]>
2013-04-04clk: exynos4: Remove SoC-specific registers from save listTomasz Figa1-16/+0
Current clock save list is shared for all Exynos4 SoCs, so it must contain only registers present in all supported SoCs, because accessing unavailable registers might have undefined effect. This patch removes registers specific for particular SoCs from shared save list, as they should be supported by separate SoC-specific lists. Signed-off-by: Tomasz Figa <[email protected]> Signed-off-by: Kyungmin Park <[email protected]> Reviewed-by: Thomas Abraham <[email protected]> Acked-by: Mike Turquette <[email protected]> Signed-off-by: Kukjin Kim <[email protected]>
2013-04-04clk: exynos4: Use SRC_MASK_PERIL{0,1} definitionsTomasz Figa1-11/+19
There are definitions of SRC_MASK_PERIL0 and SRC_MASK_PERIL1 registers, but they are not used for clock definitions. This patch modifies related clock definitions to use defined macros instead of numeric offsets. Signed-off-by: Tomasz Figa <[email protected]> Signed-off-by: Kyungmin Park <[email protected]> Reviewed-by: Thomas Abraham <[email protected]> Acked-by: Mike Turquette <[email protected]> Signed-off-by: Kukjin Kim <[email protected]>
2013-04-04clk: exynos4: Define {E,V}PLL registersTomasz Figa1-4/+12
This patch adds preprocessor definitions of EPLL and VPLL registers and replaces all occurences of offsets of related registers with new definitions. Signed-off-by: Tomasz Figa <[email protected]> Signed-off-by: Kyungmin Park <[email protected]> Reviewed-by: Thomas Abraham <[email protected]> Acked-by: Mike Turquette <[email protected]> Signed-off-by: Kukjin Kim <[email protected]>
2013-04-04clk: exynos4: Add missing mout_sata on Exynos4210Tomasz Figa1-0/+1
This patch adds missing mout_sata that is a parent of div_sata clock. Signed-off-by: Tomasz Figa <[email protected]> Signed-off-by: Kyungmin Park <[email protected]> Reviewed-by: Thomas Abraham <[email protected]> Acked-by: Mike Turquette <[email protected]> Signed-off-by: Kukjin Kim <[email protected]>
2013-04-04clk: exynos4: Add missing CMU_TOP and ISP clocksAndrzej Hajda2-3/+137
The patch adds missing clocks to TOP and ISP clock domains. It also adds clock gates for ISP sub-blocks. Signed-off-by: Andrzej Hajda <[email protected]> Signed-off-by: Tomasz Figa <[email protected]> Signed-off-by: Kyungmin Park <[email protected]> Reviewed-by: Thomas Abraham <[email protected]> Acked-by: Mike Turquette <[email protected]> Signed-off-by: Kukjin Kim <[email protected]>
2013-04-04clk: exynos4: Add G3D clocksTomasz Figa2-8/+18
This patch adds clocks needed for G3D block present on Exynos 4 SoCs. Signed-off-by: Tomasz Figa <[email protected]> Signed-off-by: Kyungmin Park <[email protected]> Reviewed-by: Thomas Abraham <[email protected]> Acked-by: Mike Turquette <[email protected]> Signed-off-by: Kukjin Kim <[email protected]>
2013-04-04clk: exynos4: Add camera related clock definitionsSylwester Nawrocki2-17/+53
This patch adds several gate and mux clocks related to camera and ISP blocks. Signed-off-by: Sylwester Nawrocki <[email protected]> Signed-off-by: Andrzej Hajda <[email protected]> Signed-off-by: Tomasz Figa <[email protected]> Signed-off-by: Kyungmin Park <[email protected]> Reviewed-by: Thomas Abraham <[email protected]> Acked-by: Mike Turquette <[email protected]> Signed-off-by: Kukjin Kim <[email protected]>
2013-04-04clk: exynos4: Export mout_core clock of Exynos4210Tomasz Figa1-1/+2
This patch enables clock lookup registration for mout_core clock used in Exynos4210 cpufreq driver. Signed-off-by: Tomasz Figa <[email protected]> Signed-off-by: Kyungmin Park <[email protected]> Reviewed-by: Thomas Abraham <[email protected]> Acked-by: Mike Turquette <[email protected]> Signed-off-by: Kukjin Kim <[email protected]>
2013-04-04clk: samsung: Remove unimplemented ops for pllTomasz Figa1-80/+0
Unimplemented clock operations should be simply omitted instead of returning error values. This patch removes unimplemented PLL operations to fix problems caused by returning error code in round_rate callback. Signed-off-by: Tomasz Figa <[email protected]> Signed-off-by: Kyungmin Park <[email protected]> Reviewed-by: Thomas Abraham <[email protected]> Acked-by: Mike Turquette <[email protected]> Signed-off-by: Kukjin Kim <[email protected]>
2013-04-04clk: exynos4: Export clocks used by exynos cpufreq driversLukasz Majewski2-3/+7
This patch exports clocks used by Exynos cpufreq drivers to allow lookup using device tree. (Support to cpufreq drivers will be added in further patches.) Signed-off-by: Lukasz Majewski <[email protected]> Signed-off-by: Tomasz Figa <[email protected]> Signed-off-by: Kyungmin Park <[email protected]> Reviewed-by: Thomas Abraham <[email protected]> Acked-by: Mike Turquette <[email protected]> Signed-off-by: Kukjin Kim <[email protected]>
2013-04-04clk: exynos4: Move dac and mixer to Exynos4210-specific clocksTomasz Figa1-2/+2
The sclk_dac and sclk_mixer clocks are not present on Exynos4x12. Signed-off-by: Tomasz Figa <[email protected]> Signed-off-by: Kyungmin Park <[email protected]> Reviewed-by: Thomas Abraham <[email protected]> Acked-by: Mike Turquette <[email protected]> Signed-off-by: Kukjin Kim <[email protected]>
2013-04-04clk: exynos4: Export sclk_pcm0Tomasz Figa2-2/+3
This clock is used by PCM interface 0. Signed-off-by: Tomasz Figa <[email protected]> Signed-off-by: Kyungmin Park <[email protected]> Reviewed-by: Thomas Abraham <[email protected]> Acked-by: Mike Turquette <[email protected]> Signed-off-by: Kukjin Kim <[email protected]>
2013-04-04clk: exynos4: Add missing sclk_audio0 clockTomasz Figa1-0/+2
This clock is a parent of mout_spdif and sclk_pcm0. Signed-off-by: Tomasz Figa <[email protected]> Signed-off-by: Kyungmin Park <[email protected]> Reviewed-by: Thomas Abraham <[email protected]> Acked-by: Mike Turquette <[email protected]> Signed-off-by: Kukjin Kim <[email protected]>
2013-04-04clk: exynos4: Add missing mout_mipihsi clockTomasz Figa1-0/+1
This patch adds missing output of mux MIPIHSI which is needed for div_mipihsi clock. Signed-off-by: Tomasz Figa <[email protected]> Signed-off-by: Kyungmin Park <[email protected]> Reviewed-by: Thomas Abraham <[email protected]> Acked-by: Mike Turquette <[email protected]> Signed-off-by: Kukjin Kim <[email protected]>
2013-04-04clk: exynos4: Use mout_mpll_user_* on Exynos4x12Tomasz Figa2-61/+113
Many clock muxes of Exynos 4x12 uses mout_mpll_user_* clocks instead of sclk_mpll as one of their parents. This patch moves such clocks from common array into SoC-specific arrays and adjusts their parent lists respectively. Signed-off-by: Tomasz Figa <[email protected]> Signed-off-by: Kyungmin Park <[email protected]> Reviewed-by: Thomas Abraham <[email protected]> Acked-by: Mike Turquette <[email protected]> Signed-off-by: Kukjin Kim <[email protected]>
2013-04-04clk: exynos4: Correct sclk_mfc clock definitionSylwester Nawrocki2-3/+3
This clock must be exported to allow lookup using device tree. Signed-off-by: Sylwester Nawrocki <[email protected]> Signed-off-by: Tomasz Figa <[email protected]> Signed-off-by: Kyungmin Park <[email protected]> Reviewed-by: Thomas Abraham <[email protected]> Acked-by: Mike Turquette <[email protected]> Signed-off-by: Kukjin Kim <[email protected]>
2013-04-04clocksource: mct: Add terminating entry for exynos_mct_ids tableAxel Lin1-0/+1
The of_device_id table is supposed to be zero-terminated. Signed-off-by: Axel Lin <[email protected]> Signed-off-by: Kukjin Kim <[email protected]>
2013-04-04clocksource: mct: Add missing semicolons in exynos_mct.cDoug Anderson1-2/+2
The CLOCKSOURCE_OF_DECLARE lines were added without a semicolon at the end. On my system this causes a compile-time error that looks like: drivers/clocksource/exynos_mct.c:557:202: warning: comparison of distinct pointer types lacks a cast [enabled by default] drivers/clocksource/exynos_mct.c:558:1: error: expected ',' or ';' before 'static' The error didn't show up till now because there was an extra semicolon at end of the CLOCKSOURCE_OF_DECLARE definition that was removed by Arnd Bergmann in "clocksource: make CLOCKSOURCE_OF_DECLARE type safe" Signed-off-by: Doug Anderson <[email protected]> Signed-off-by: Kukjin Kim <[email protected]>
2013-04-04irqchip: s3c24xx: add devicetree supportHeiko Stuebner2-6/+278
Add the necessary code to initialize the interrupt controller thru devicetree data using the irqchip infrastructure. Signed-off-by: Heiko Stuebner <[email protected]> Acked-by: Arnd Bergmann <[email protected]> Acked-by: Rob Herring <[email protected]> Signed-off-by: Kukjin Kim <[email protected]>
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