aboutsummaryrefslogtreecommitdiff
AgeCommit message (Collapse)AuthorFilesLines
2022-04-05drm/amd/display: 3.2.180Aric Cyr1-1/+1
- [FW Promotion] Release 0.0.111.0 - Check for invalid input params when building scaling params - Move link_trace for edp to dp_trace - Fix missing-prototypes warning - Enable 3 plane for DCN 3.0 and 3.02 - Extract set stream attribute into link_hwss - Revert Power down hardware if timer not trigger - Add support for handling 128b/132b link training test request - Add configuration options for AUX wake work around - Remove underflow IRQ type - Add flip interval workaround for low FPS in some game - Remove assert for odm transition case Tested-by: Daniel Wheeler <[email protected]> Acked-by: Tom Chung <[email protected]> Signed-off-by: Aric Cyr <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-04-05drm/amd/display: fix missing-prototypes warningBecle Lee1-0/+1
[Why] No declaration of hubp1_wait_pipe_read_start found in header file. [How] Add its declaration. Tested-by: Daniel Wheeler <[email protected]> Reviewed-by: Aric Cyr <[email protected]> Acked-by: Tom Chung <[email protected]> Signed-off-by: Becle Lee <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-04-05drm/amd/display: Enable 3 plane for DCN 3.0 and 3.02Krunoslav Kovac2-6/+6
[WHY&HOW] Increase num of bottom planes to 2. Note that DCN 3.03 is left out since it has max 2 planes. Tested-by: Daniel Wheeler <[email protected]> Reviewed-by: Aric Cyr <[email protected]> Acked-by: Tom Chung <[email protected]> Signed-off-by: Krunoslav Kovac <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-04-05drm/amd/display: extract set stream attribute to link_hwssWenjing Liu8-47/+94
[why] Extract set stream attribute into link_hwss as part of the link hwss refactor work. Tested-by: Daniel Wheeler <[email protected]> Reviewed-by: George Shen <[email protected]> Acked-by: Tom Chung <[email protected]> Signed-off-by: Wenjing Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-04-05drm/amd/display: revert Power down hardware if timer not triggerMartin Leung1-25/+1
Tested-by: Daniel Wheeler <[email protected]> Reviewed-by: George Shen <[email protected]> Acked-by: Tom Chung <[email protected]> Signed-off-by: Martin Leung <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-04-05drm/amd/display: add support for handling 128b/132b link training test requestWenjing Liu2-2/+36
[why] DP2.x added new enum values for UHBR link rates in link training test request for test automation. We need to add UHBR link rates test request support in preparation for compliance test automation. [how] added a function that translate test link rate to dc link rate. Call the translation function to decide the requested test link rate. Tested-by: Daniel Wheeler <[email protected]> Reviewed-by: George Shen <[email protected]> Acked-by: Tom Chung <[email protected]> Signed-off-by: Wenjing Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-04-05drm/amd/display: Add configuration options for AUX wake work around.Jimmy Kizito2-1/+24
[Why] Work around to try to wake unresponsive DP sinks may need to be adjusted for certain sinks. [How] Add options to disable work around or adjust time spent trying to wake unresponsive DPRX. Tested-by: Daniel Wheeler <[email protected]> Reviewed-by: Martin Leung <[email protected]> Acked-by: Tom Chung <[email protected]> Signed-off-by: Jimmy Kizito <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-04-05drm/amd/display: Remove underflow IRQ typeAngus Wang1-1/+0
[WHY] Feature using the underflow IRQ type reverted [HOW] Removed underflow IRQ type entry Tested-by: Daniel Wheeler <[email protected]> Reviewed-by: Martin Leung <[email protected]> Acked-by: Tom Chung <[email protected]> Signed-off-by: Angus Wang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-04-05drm/amd/display: Add flip interval workaroundAngus Wang2-1/+85
[WHY] Some games experience low FPS issues when FreeSync is on and VSync is toggled to half refresh rate. [HOW] First create a function to determine workaround conditions, which is when we detect 2 or more VSync interrupts between flips and a very short VSync to flip interval. We do the workaround during VSync interrupts and set the v_total_max and min to nominal. We also cleanup after we exit the game. Tested-by: Daniel Wheeler <[email protected]> Reviewed-by: Anthony Koo <[email protected]> Reviewed-by: Aric Cyr <[email protected]> Acked-by: Tom Chung <[email protected]> Signed-off-by: Angus Wang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-04-05drm/amd/display: remove assert for odm transition caseEric Bernstein1-1/+0
Remove assert that will hit during odm transition case, since this is a valid case. Tested-by: Daniel Wheeler <[email protected]> Reviewed-by: Alvin Lee <[email protected]> Acked-by: Tom Chung <[email protected]> Signed-off-by: Eric Bernstein <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-04-05drm/amdgpu: Flush TLB after mapping for VG20+XGMIPhilip Yang1-0/+6
For VG20 + XGMI bridge, all mappings PTEs cache in TC, this may have stall invalid PTEs in TC because one cache line has 8 pages. Need always flush_tlb after updating mapping. Signed-off-by: Philip Yang <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-04-05drm/amdgpu: don't use BACO for reset in S3Alex Deucher1-0/+11
Seems to cause a reboots or hangs on some systems. Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1924 Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1953 Fixes: daf8de0874ab5b ("drm/amdgpu: always reset the asic in suspend (v2)") Reviewed-by: Lijo Lazar <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-04-05drm/amdgpu/vcn: Remove unneeded semicolonHaowen Bai1-1/+1
report by coccicheck: drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c:1951:2-3: Unneeded semicolon Fixes: c543dcbe4237 ("drm/amdgpu/vcn: Add VCN ras error query support") Signed-off-by: Haowen Bai <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-04-05drm/amd/display: Fix unused-but-set-variable warningAashish Sharma1-4/+2
Fix the kernel test robot warning below: drivers/gpu/drm/amd/amdgpu/../display/dmub/inc/dmub_cmd.h:2893:12: warning: variable 'temp' set but not used [-Wunused-but-set-variable] Replaced the assignment to the unused temp variable with READ_ONCE() macro to flush the writes. READ_ONCE() helps avoid the use of volatile and makes it obvious from the code that the read here is intentional. Also verified on x86 that the generated code is exactly the same as before. Reported-by: kernel test robot <[email protected]> Signed-off-by: Aashish Sharma <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-04-05amdgpu/pm: Enable sysfs nodes for vclk and dclk for NAVI12Marko Zekovic1-2/+4
SMI clock measure API is failing on NAVI12, because sysfs node for pp_dpm_vclk is not existing. Enable sysfs node for pp_dpm_vclk for NAVI12. v2: Also enable sysfs node for pp_dpm_dclk. Reviewed-by: Lijo Lazar <[email protected]> Signed-off-by: Marko Zekovic <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-04-05drm/amdgpu: fix TLB flushing during evictionChristian König3-48/+48
Testing the valid bit is not enough to figure out if we need to invalidate the TLB or not. During eviction it is quite likely that we move a BO from VRAM to GTT and update the page tables immediately to the new GTT address. Rework the whole function to get all the necessary parameters directly as value. Signed-off-by: Christian König <[email protected]> Reviewed-by: Philip Yang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-04-05drm/amd/display: Fix by adding FPU protection for dcn30_internal_validate_bwCHANDAN VURDIGERE NATARAJ1-0/+2
[Why] Below general protection fault observed when WebGL Aquarium is run for longer duration. If drm debug logs are enabled and set to 0x1f then the issue is observed within 10 minutes of run. [ 100.717056] general protection fault, probably for non-canonical address 0x2d33302d32323032: 0000 [#1] PREEMPT SMP NOPTI [ 100.727921] CPU: 3 PID: 1906 Comm: DrmThread Tainted: G W 5.15.30 #12 d726c6a2d6ebe5cf9223931cbca6892f916fe18b [ 100.754419] RIP: 0010:CalculateSwathWidth+0x1f7/0x44f [ 100.767109] Code: 00 00 00 f2 42 0f 11 04 f0 48 8b 85 88 00 00 00 f2 42 0f 10 04 f0 48 8b 85 98 00 00 00 f2 42 0f 11 04 f0 48 8b 45 10 0f 57 c0 <f3> 42 0f 2a 04 b0 0f 57 c9 f3 43 0f 2a 0c b4 e8 8c e2 f3 ff 48 8b [ 100.781269] RSP: 0018:ffffa9230079eeb0 EFLAGS: 00010246 [ 100.812528] RAX: 2d33302d32323032 RBX: 0000000000000500 RCX: 0000000000000000 [ 100.819656] RDX: 0000000000000001 RSI: ffff99deb712c49c RDI: 0000000000000000 [ 100.826781] RBP: ffffa9230079ef50 R08: ffff99deb712460c R09: ffff99deb712462c [ 100.833907] R10: ffff99deb7124940 R11: ffff99deb7124d70 R12: ffff99deb712ae44 [ 100.841033] R13: 0000000000000001 R14: 0000000000000000 R15: ffffa9230079f0a0 [ 100.848159] FS: 00007af121212640(0000) GS:ffff99deba780000(0000) knlGS:0000000000000000 [ 100.856240] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [ 100.861980] CR2: 0000209000fe1000 CR3: 000000011b18c000 CR4: 0000000000350ee0 [ 100.869106] Call Trace: [ 100.871555] <TASK> [ 100.873655] ? asm_sysvec_reschedule_ipi+0x12/0x20 [ 100.878449] CalculateSwathAndDETConfiguration+0x1a3/0x6dd [ 100.883937] dml31_ModeSupportAndSystemConfigurationFull+0x2ce4/0x76da [ 100.890467] ? kallsyms_lookup_buildid+0xc8/0x163 [ 100.895173] ? kallsyms_lookup_buildid+0xc8/0x163 [ 100.899874] ? __sprint_symbol+0x80/0x135 [ 100.903883] ? dm_update_plane_state+0x3f9/0x4d2 [ 100.908500] ? symbol_string+0xb7/0xde [ 100.912250] ? number+0x145/0x29b [ 100.915566] ? vsnprintf+0x341/0x5ff [ 100.919141] ? desc_read_finalized_seq+0x39/0x87 [ 100.923755] ? update_load_avg+0x1b9/0x607 [ 100.927849] ? compute_mst_dsc_configs_for_state+0x7d/0xd5b [ 100.933416] ? fetch_pipe_params+0xa4d/0xd0c [ 100.937686] ? dc_fpu_end+0x3d/0xa8 [ 100.941175] dml_get_voltage_level+0x16b/0x180 [ 100.945619] dcn30_internal_validate_bw+0x10e/0x89b [ 100.950495] ? dcn31_validate_bandwidth+0x68/0x1fc [ 100.955285] ? resource_build_scaling_params+0x98b/0xb8c [ 100.960595] ? dcn31_validate_bandwidth+0x68/0x1fc [ 100.965384] dcn31_validate_bandwidth+0x9a/0x1fc [ 100.970001] dc_validate_global_state+0x238/0x295 [ 100.974703] amdgpu_dm_atomic_check+0x9c1/0xbce [ 100.979235] ? _printk+0x59/0x73 [ 100.982467] drm_atomic_check_only+0x403/0x78b [ 100.986912] drm_mode_atomic_ioctl+0x49b/0x546 [ 100.991358] ? drm_ioctl+0x1c1/0x3b3 [ 100.994936] ? drm_atomic_set_property+0x92a/0x92a [ 100.999725] drm_ioctl_kernel+0xdc/0x149 [ 101.003648] drm_ioctl+0x27f/0x3b3 [ 101.007051] ? drm_atomic_set_property+0x92a/0x92a [ 101.011842] amdgpu_drm_ioctl+0x49/0x7d [ 101.015679] __se_sys_ioctl+0x7c/0xb8 [ 101.015685] do_syscall_64+0x5f/0xb8 [ 101.015690] ? __irq_exit_rcu+0x34/0x96 [How] It calles populate_dml_pipes which uses doubles to initialize. Adding FPU protection avoids context switch and probable loss of vba context as there is potential contention while drm debug logs are enabled. Signed-off-by: CHANDAN VURDIGERE NATARAJ <[email protected]> Reviewed-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-03-31drm/amdkfd: Create file descriptor after client is added to smi_clients listLee Jones1-9/+15
This ensures userspace cannot prematurely clean-up the client before it is fully initialised which has been proven to cause issues in the past. Cc: Felix Kuehling <[email protected]> Cc: Alex Deucher <[email protected]> Cc: "Christian König" <[email protected]> Cc: "Pan, Xinhui" <[email protected]> Cc: David Airlie <[email protected]> Cc: Daniel Vetter <[email protected]> Cc: [email protected] Cc: [email protected] Signed-off-by: Lee Jones <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-03-31drm/amdgpu: Sync up header and implementation to use the same parameter namesMa Jun1-2/+2
Sync up header and implementation to use the same parameter names in function amdgpu_ring_init. ring_size -> max_dw, prio -> hw_prio Reviewed-by: Guchun Chen <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Ma Jun <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-03-31drm/amdgpu: fix incorrect GCR_GENERAL_CNTL addressRuili Ji1-3/+3
gfx10.3.3/gfx10.3.6/gfx10.3.7 shall use 0x1580 address for GCR_GENERAL_CNTL Acked-by: Prike Liang <[email protected]> Acked-by: Yifan Zhang <[email protected]> Reviewed-by: Aaron Liu <[email protected]> Signed-off-by: Ruili Ji <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-03-31drm/amdgpu: Fix unique_id references for Sienna CichlidKent Russell2-12/+4
Since unique_id is only supported in PMFW 0x3A5300 and higher, we will only be able to use it inside Smu_Metrics_V3_t, which requires PMFW 0x3A4900 and higher. Remove the unique_id/serial_number references from the v1 and v2 tables to avoid any confusion, and return 0 if metrics_v1 or metrics_v2 are used to try to get the unique_id/serial_number. Signed-off-by: Kent Russell <[email protected]> Reviewed-by: Lijo Lazar <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-03-31drm/amd/display: remove DC_FP_* wrapper from dml folderMelissa Wen4-18/+10
FPU documentation states that developers must not use DC_FP_START/END inside dml files, but use this macro to wrap calls to FPU functions in dc folder (outside dml folder). Therefore, this patch removes DC_FP_* wrappers from dml folder and wraps calls for these FPU operations outside dml, as required. Acked-by: Christian König <[email protected]> Reviewed-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Melissa Wen <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-03-31drm/amd/display: detach fpu operations from dcn10_validate_bandwidth in calcsMelissa Wen3-5/+16
dcn10_validate_bandwidth is only used on dcn10 files, but is declared in dcn_calcs files. Rename dcn10_* to dcn_* in calcs, remove DC_FP_* wrapper inside DML folder and create an specific dcn10_validate_bandwidth in dcn10_resources that calls dcn_validate_bandwidth and properly wraps that FPU function with DC_FP_* macro. Acked-by: Christian König <[email protected]> Reviewed-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Melissa Wen <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-03-31drm/amdgpu: Add unique_id support for sienna cichlidKent Russell3-2/+45
This is being added to SMU Metrics, so add the required tie-ins in the kernel. Also create the corresponding unique_id sysfs file. v2: Add FW version check, remove SMU mutex v3: Fix style warning v4: Add MP1 IP_VERSION check to FW version check Signed-off-by: Kent Russell <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-03-31drm/amdgpu: Use metrics data function to get unique_id for AldebaranKent Russell1-7/+9
This is abstracted well enough in the get_metrics_data function, so use the function Signed-off-by: Kent Russell <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-03-31drm/amdgpu: Add UNIQUE_ID to MetricsMember_tKent Russell1-0/+2
This will allow us to use the generic *_get_metrics_data functions for ASICs that support unique_id Signed-off-by: Kent Russell <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-03-31drm/amdgpu: Use switch case for unique_idKent Russell1-4/+9
To ease readability, use switch to set unique_id as supported for the supported IP_VERSIONs, and set it to unsupported by default for all other ASICs. This makes it easier to add IP_VERSIONs later on, and makes it obvious that it is not supported by default, instead of the current logic that assumes that it is supported unless it is not one of the specified IP_VERSIONs. v2: Rebase onto previous IP_VERSION change Signed-off-by: Kent Russell <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Kevin Wang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-03-31drm/amdkfd: Use atomic64_t type for pdd->tlb_seqPhilip Yang2-4/+8
To support multi-thread update page table. Signed-off-by: Philip Yang <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-03-31drm/amdgpu: fix incorrect size printing in error msgChristian König1-1/+1
That are bytes not pages. Signed-off-by: Christian König <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-03-31drm/amdgpu: fix some kerneldoc in the VM code v2Christian König2-2/+2
Fix two incorrect kerneldocs for the recent VM code changes. v2: fix one more typo Signed-off-by: Christian König <[email protected]> Reported-by: kernel test robot <[email protected]> Reported-by: Stephen Rothwell <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-03-31amd/display: set backlight only if requiredShirish S2-3/+10
[Why] comparing pwm bl values (coverted) with user brightness(converted) levels in commit_tail leads to continuous setting of backlight via dmub as they don't to match. This leads overdrive in queuing of commands to DMCU that sometimes lead to depending on load on DMCU fw: "[drm:dc_dmub_srv_wait_idle] *ERROR* Error waiting for DMUB idle: status=3" [How] Store last successfully set backlight value and compare with it instead of pwm reads which is not what we should compare with. Signed-off-by: Shirish S <[email protected]> Reviewed-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-03-31drm/amd/display: DCN3.1: don't mark as kernel-docRandy Dunlap1-2/+1
There is no need for this one static function to be marked as kernel-doc notation. Avoid this doc build warning: warning: This comment starts with '/**', but isn't a kernel-doc comment. Refer Documentation/doc-guide/kernel-doc.rst * Enable CRTC Fixes: 110d3968fe95 ("drm/amd/display: Add DCN3.1 OPTC") Signed-off-by: Randy Dunlap <[email protected]> Cc: Alex Deucher <[email protected]> Cc: Nicholas Kazlauskas <[email protected]> Cc: [email protected] Cc: Christian König <[email protected]> Cc: "Pan, Xinhui" <[email protected]> Cc: Harry Wentland <[email protected]> Cc: Leo Li <[email protected]> Cc: Rodrigo Siqueira <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-03-31drm/amd/display: Fix pointer dereferenced before checkingHaowen Bai1-1/+1
The value actual_pix_clk_100Hz is dereferencing pointer pix_clk_params before pix_clk_params is being null checked. Fix this by assigning pix_clk_params->requested_pix_clk_100hz to actual_pix_clk_100Hz only if pix_clk_params is not NULL, otherwise just NULL. Signed-off-by: Haowen Bai <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-03-31drm/amdgpu: Add tlb_cb for unlocked updatePhilip Yang1-1/+1
Flush TLB needs wait for GPU update fence done. MMU notify callback to unmap range from GPUs uses unlocked GPU page table update, so add tlb_cb to unlocked update fence to increase vm->tlb_seq. Signed-off-by: Philip Yang <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-03-31drm/amdgpu: Correct unlocked update fence handlingPhilip Yang1-1/+1
To fix two issues with unlocked update fence: 1. vm->last_unlocked store the latest fence without taking refcount. 2. amdgpu_vm_bo_update_mapping returns old fence, not the latest fence. Signed-off-by: Philip Yang <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-03-31drm/amd/display: Fix pointer dereferenced before checkingHaowen Bai1-1/+1
The pointer edid_buf is dereferencing pointer edid before edid is being null checked. Fix this by assigning edid->raw_edid to edid_buf only if edid is not NULL, otherwise just NULL. Signed-off-by: Haowen Bai <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-03-31drm/amd/display: Fix allocate_mst_payload assert on resumeRoman Li1-1/+2
[Why] On resume we do link detection for all non-MST connectors. MST is handled separately. However the condition for telling if connector is on mst branch is not enough for mst hub case. Link detection for mst branch link leads to mst topology reset. That causes assert in dc_link_allocate_mst_payload() [How] Use link type as indicator for mst link. Reviewed-by: Wayne Lin <[email protected]> Acked-by: Alex Hung <[email protected]> Signed-off-by: Roman Li <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-03-31drm/amd/display: 3.2.179Aric Cyr1-1/+1
- [FW Promotion] Release 0.0.110.0 - Revert FEC check in validation - Update LTTPR UHBR link rate support struct - Add support for USBC connector - Add work around for AUX failure on wake - Clear optc false state when disable otg - Enable power gating before init_pipes - Remove redundant dsc power gating from init_hw - Power down hardware if timer not trigger - Correct Slice reset calculation - Enable 3-plane MPO for DCN31 - Set fec register init value - Remove SW w/a for HDCP 1.4 1A-07 failure based on ECO fix - Create underflow interrupt IRQ type Acked-by: Alex Hung <[email protected]> Signed-off-by: Aric Cyr <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-03-31drm/amd/display: [FW Promotion] Release 0.0.110.0Anthony Koo1-86/+4
- Revert save/restore PANEL_PWRSEQ_REF_DIV2 and other psr phy optimizations Reviewed-by: Aric Cyr <[email protected]> Acked-by: Alex Hung <[email protected]> Signed-off-by: Anthony Koo <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-03-31drm/amd/display: Revert FEC check in validationMartin Leung1-4/+0
why and how: causes failure on install on certain machines Reviewed-by: George Shen <[email protected]> Acked-by: Alex Hung <[email protected]> Signed-off-by: Martin Leung <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-03-31drm/amd/display: Update LTTPR UHBR link rate support structMichael Strauss1-1/+1
[WHY] Update field order to match DP2.0 spec SCR Reviewed-by: George Shen <[email protected]> Acked-by: Alex Hung <[email protected]> Signed-off-by: Michael Strauss <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-03-31drm/amd/display: Add support for USBC connectorSamson Tam4-3/+12
[Why] Add support for CONNECTOR_ID_USBC Reviewed-by: Alvin Lee <[email protected]> Acked-by: Alex Hung <[email protected]> Signed-off-by: Samson Tam <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-03-31drm/amd/display: Add work around for AUX failure on wake.Jimmy Kizito2-0/+60
[Why] When waking from low-power states, a DP sink may remain unresponsive to AUX transactions. [How] Try to toggle DPCD SET_POWER register repeatedly (up to a maximum timeout value) until DP sink becomes responsive. Reviewed-by: Mustapha Ghaddar <[email protected]> Acked-by: Alex Hung <[email protected]> Signed-off-by: Jimmy Kizito <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-03-31drm/amd/display: Clear optc false state when disable otgCharlene Liu2-8/+11
[why] when disable optc, need to clear the underflow status as well. Reviewed-by: Chris Park <[email protected]> Acked-by: Alex Hung <[email protected]> Signed-off-by: Charlene Liu <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-03-31drm/amd/display: Enable power gating before init_pipesRoman Li3-6/+9
[Why] In init_hw() we call init_pipes() before enabling power gating. init_pipes() tries to power gate dsc but it may fail because required force-ons are not released yet. As a result with dsc config the following errors observed on resume: "REG_WAIT timeout 1us * 1000 tries - dcn20_dsc_pg_control" "REG_WAIT timeout 1us * 1000 tries - dcn20_dpp_pg_control" "REG_WAIT timeout 1us * 1000 tries - dcn20_hubp_pg_control" [How] Move enable_power_gating_plane() before init_pipes() in init_hw() Reviewed-by: Anthony Koo <[email protected]> Reviewed-by: Eric Yang <[email protected]> Acked-by: Alex Hung <[email protected]> Signed-off-by: Roman Li <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-03-31drm/amd/display: Remove redundant dsc power gating from init_hwRoman Li1-7/+0
[Why] DSC Power down code has been moved from dcn31_init_hw into init_pipes() Need to remove it from dcn10_init_hw() as well to avoid duplicated action on dcn1.x/2.x [How] Remove DSC power down code from dcn10_init_hw() Fixes: 8fa6f4c5715c ("drm/amd/display: fixed the DSC power off sequence during Driver PnP") Reviewed-by: Anthony Koo <[email protected]> Reviewed-by: Eric Yang <[email protected]> Acked-by: Alex Hung <[email protected]> Signed-off-by: Roman Li <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-03-31drm/amd/display: Power down hardware if timer not triggerPaul Hsieh1-1/+25
[WHY] In headless systems, if SetMode/Power down timer is not called, hardware will not be powered down causing HW/SW discrepancies. Powering down hardware on SetPowerState to D3 will ensure SW/HW state is accurate. [HOW] If PowerDownThread timer is not trigger but OS call SetPowerState to D3, power down hardware. Reviewed-by: Eric Yang <[email protected]> Acked-by: Alex Hung <[email protected]> Signed-off-by: Paul Hsieh <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-03-31drm/amd/display: Correct Slice reset calculationChris Park1-2/+2
[Why] Once DSC slice cannot fit pixel clock, we incorrectly reset min slices to 0 and allow max slice to operate, even when max slice itself cannot fit the pixel clock properly. [How] Change the sequence such that we correctly determine DSC is not possible when both min slices and max slices cannot fit pixel clock per slice. Reviewed-by: Wenjing Liu <[email protected]> Acked-by: Alex Hung <[email protected]> Signed-off-by: Chris Park <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-03-31drm/amd/display: Enable 3-plane MPO for DCN31Krunoslav Kovac1-3/+3
[WHY&HOW] It can be enabled by users, but proper way is to report max_slave_planes in DC caps for each ASIC. Some structures use hardcoded max_plane=2, this is also addressed here. Reviewed-by: Nevenko Stupar <[email protected]> Reviewed-by: Aric Cyr <[email protected]> Acked-by: Alex Hung <[email protected]> Signed-off-by: Krunoslav Kovac <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-03-31drm/amd/display: Set fec register init valueJingwen Zhu3-16/+22
[Why] We don't include this eDP FEC init on fastboot. [How] Set the fec to init value when stopping driver &get the fec register value to check should enable FEC. Co-authored-by: Jingwen Zhu <[email protected]> Reviewed-by: Wenjing Liu <[email protected]> Acked-by: Alex Hung <[email protected]> Signed-off-by: Jingwen Zhu <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
Powered by cgit, Gruvboxed by Blaster4385.