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authorMichael Strauss <[email protected]>2022-03-17 10:17:01 -0400
committerAlex Deucher <[email protected]>2022-03-31 23:05:53 -0400
commita772105cfaca3c7b28bbe8a4e22a08efa561b603 (patch)
tree0a010acc2e6301d6dc75c2d9d2d3a74c5b7cbe55
parent8cb3c169fc7574cb889deb3b59a3c8e783fb4685 (diff)
drm/amd/display: Update LTTPR UHBR link rate support struct
[WHY] Update field order to match DP2.0 spec SCR Reviewed-by: George Shen <[email protected]> Acked-by: Alex Hung <[email protected]> Signed-off-by: Michael Strauss <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
-rw-r--r--drivers/gpu/drm/amd/display/dc/dc_dp_types.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dc_dp_types.h b/drivers/gpu/drm/amd/display/dc/dc_dp_types.h
index 36ac2a8746bd..7d4aa99525da 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_dp_types.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_dp_types.h
@@ -993,8 +993,8 @@ union dp_128b_132b_supported_link_rates {
union dp_128b_132b_supported_lttpr_link_rates {
struct {
uint8_t UHBR10 :1;
- uint8_t UHBR13_5:1;
uint8_t UHBR20 :1;
+ uint8_t UHBR13_5:1;
uint8_t RESERVED:5;
} bits;
uint8_t raw;