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2023-08-22phy: qcom-qmp-combo: fix clock probingDmitry Baryshkov1-6/+6
During rebase of qcom-qmp-combo series a call to devm_clk_bulk_get_all() got moved by git from qmp_combo_parse_dt_legacy() to phy_dp_clks_register(). This doesn't have any serious effect, since the clocks will be set in both legacy and non-legacy paths. However let's move it back to place anyway, to prevent the driver from fetching clocks twice. Fixes: 28e265bf84a8 ("phy: qcom-qmp-combo: simplify clock handling") Signed-off-by: Dmitry Baryshkov <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-08-22phy: qcom-qmp-pcie: support SM8150 PCIe QMP PHYsDmitry Baryshkov1-0/+6
Reuse sm8250 configuration to add support for both single lane and dual lane PCIe PHYs on the Qualcomm SM8150 platform. Signed-off-by: Dmitry Baryshkov <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-08-22phy: qcom-qmp-pcie: populate offsets configurationDmitry Baryshkov1-0/+74
Populate offsets configuration for the rest of UFS PHYs to make it possible to switch them to the new (single-node) bindings style. Signed-off-by: Dmitry Baryshkov <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-08-22phy: qcom-qmp-pcie: simplify clock handlingDmitry Baryshkov1-71/+7
For some of existing PHYs for new binding we are going to change refgen to more correct "rchng". Rather than introducing additional code to handle legacy vs current bindings (and clock names), use devm_clk_bulk_get_optional(). Reviewed-by: Konrad Dybcio <[email protected]> Signed-off-by: Dmitry Baryshkov <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-08-22phy: qcom-qmp-pcie: keep offset tables sortedDmitry Baryshkov1-11/+11
In order to simplify adding new PHY configurations, keep register offset structs sorted by the version. Fixes: a05b6d5135ec ("phy: qcom-qmp-pcie: add support for sa8775p") Signed-off-by: Dmitry Baryshkov <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-08-22phy: qcom-qmp-pcie: drop ln_shrd from v5_20 configDmitry Baryshkov1-1/+0
There is no shared lane config for v5.20 PHYs, it is only present on SM8550 gen4x2. Fixes: a05b6d5135ec ("phy: qcom-qmp-pcie: add support for sa8775p") Cc: Mrinmay Sarkar <[email protected]> Signed-off-by: Dmitry Baryshkov <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-08-22dt-bindings: phy: qcom,qmp-pcie: describe SM8150 PCIe PHYsDmitry Baryshkov1-0/+4
Descrbie two PCIe PHYs found on the Qualcomm SM8150 platform, single lane and two lanes Gen3 PHYs. Signed-off-by: Dmitry Baryshkov <[email protected]> Reviewed-by: Krzysztof Kozlowski <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-08-22dt-bindings: phy: migrate QMP PCIe PHY bindings to ↵Dmitry Baryshkov3-246/+161
qcom,sc8280xp-qmp-pcie-phy.yaml Migrate legacy bindings (described in qcom,ipq8074-qmp-pcie-phy.yaml) to qcom,sc8280xp-qmp-pcie-phy.yaml. This removes a need to declare the child PHY node or split resource regions. Signed-off-by: Dmitry Baryshkov <[email protected]> Reviewed-by: Krzysztof Kozlowski <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-08-22phy: fsl-imx8mq-usb: add dev_err_probe if getting vbus failedAlexander Stein1-1/+1
This adds an error message if getting vbus failed for some reason, -EPROBE_DEFER is handled appropriately as well and adds a nice information to debugfs. Signed-off-by: Alexander Stein <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-08-22phy: qcom: Introduce M31 USB PHY driverVaradarajan Narayanan3-0/+306
Add the M31 USB2 phy driver for the USB M31 PHY (https://www.m31tech.com) found in Qualcomm IPQ5018, IPQ5332 SoCs. Signed-off-by: Varadarajan Narayanan <[email protected]> Reviewed-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/c8821bb0124a54cc774a2ff7b9c40df28eb7711e.1691999761.git.quic_varada@quicinc.com Signed-off-by: Vinod Koul <[email protected]>
2023-08-22dt-bindings: phy: qcom,m31: Document qcom,m31 USB phyVaradarajan Narayanan1-0/+59
Document the M31 USB2 phy present in IPQ5332. Reviewed-by: Krzysztof Kozlowski <[email protected]> Co-developed-by: Sricharan Ramabadhran <[email protected]> Signed-off-by: Sricharan Ramabadhran <[email protected]> Signed-off-by: Varadarajan Narayanan <[email protected]> Link: https://lore.kernel.org/r/44a31cf0361df8db527684c7fb3b38e6ece950c1.1691999761.git.quic_varada@quicinc.com Signed-off-by: Vinod Koul <[email protected]>
2023-08-22phy: rockchip: inno-dsidphy: Add rv1126 supportJagan Teki1-0/+3
Add support for Rockchip RV1126 DSI-DPHY. The existing 2.5GHz phy timing table added for RK3568 is working as it is for RV1126 as well. Signed-off-by: Jagan Teki <[email protected]> Reviewed-by: Heiko Stuebner <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-08-22dt-bindings: phy: rockchip-inno-dsidphy: Document rv1126Jagan Teki1-0/+1
Document a compatible string for the rv1126 dsi-dphy. Signed-off-by: Jagan Teki <[email protected]> Acked-by: Heiko Stuebner <[email protected]> Acked-by: Rob Herring <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-08-22dt-bindings: phy: mediatek,tphy: allow simple nodename patternEugen Hristev1-1/+1
The pattern for the nodename only allows t-phy@... , however, for the case when the t-phy has no `reg` and only `ranges` (basically when the t-phy is just a parent node), dtc will throw this warning: Warning (unit_address_vs_reg): /t-phy@1a243000: node has a unit name, but no reg or ranges property For a node like this: sata_phy: t-phy@1a243000 { ranges; sata_port: sata-phy@1a243000 { reg = <0 0x1a243000 0 0x0100>; }; }; it is normal that the parent node 't-phy' would be without any address, as in: sata_phy: t-phy { ranges; sata_port: sata-phy@1a243000 { reg = <0 0x1a243000 0 0x0100>; }; }; because being just a holder it does not have its own reg. However the binding does not allow such a name for the t-phy, so with this patch, making the `@[0-9a-f]+` part optional, such node is possible. Signed-off-by: Eugen Hristev <[email protected]> Acked-by: Conor Dooley <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-08-22phy: amlogic: meson-g12a-usb2: fix Wvoid-pointer-to-enum-cast warningKrzysztof Kozlowski1-1/+1
'soc_id' is an enum, thus cast of pointer on 64-bit compile test with W=1 causes: phy-meson-g12a-usb2.c:322:17: error: cast to smaller integer type 'enum meson_soc_id' from 'const void *' [-Werror,-Wvoid-pointer-to-enum-cast] Signed-off-by: Krzysztof Kozlowski <[email protected]> Reviewed-by: Neil Armstrong <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-08-11phy: marvell pxa-usb: fix Wvoid-pointer-to-enum-cast warningKrzysztof Kozlowski1-1/+1
'version' is an enum, thus cast of pointer on 64-bit compile test with W=1 causes: phy-pxa-usb.c:299:26: error: cast to smaller integer type 'enum pxa_usb_phy_version' from 'const void *' [-Werror,-Wvoid-pointer-to-enum-cast] Signed-off-by: Krzysztof Kozlowski <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-08-11phy: broadcom: sr-usb: fix Wvoid-pointer-to-enum-cast warningKrzysztof Kozlowski1-1/+1
'version' is an enum, thus cast of pointer on 64-bit compile test with W=1 causes: phy-bcm-sr-usb.c:314:13: error: cast to smaller integer type 'enum bcm_usb_phy_version' from 'const void *' [-Werror,-Wvoid-pointer-to-enum-cast] Signed-off-by: Krzysztof Kozlowski <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-08-11phy: broadcom: ns-usb3: fix Wvoid-pointer-to-enum-cast warningKrzysztof Kozlowski1-1/+1
'family' is an enum, thus cast of pointer on 64-bit compile test with W=1 causes: drivers/phy/broadcom/phy-bcm-ns-usb3.c:209:17: error: cast to smaller integer type 'enum bcm_ns_family' from 'const void *' [-Werror,-Wvoid-pointer-to-enum-cast] Signed-off-by: Krzysztof Kozlowski <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-08-11phy: broadcom: sata: fix Wvoid-pointer-to-enum-cast warningKrzysztof Kozlowski1-1/+1
'version' is an enum, thus cast of pointer on 64-bit compile test with W=1 causes: phy-brcm-sata.c:775:19: error: cast to smaller integer type 'enum brcm_sata_phy_version' from 'const void *' [-Werror,-Wvoid-pointer-to-enum-cast] Signed-off-by: Krzysztof Kozlowski <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-08-11dt-bindings: phy: qcom,snps-eusb2-repeater: Add compatible for PM7550BARohit Agarwal1-1/+6
Add a dt-bindings compatible string for the Qualcomm's PM7550BA PMIC. Signed-off-by: Rohit Agarwal <[email protected]> Reviewed-by: Krzysztof Kozlowski <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-08-11MAINTAINERS: correct file entry in STARFIVE JH7110 DPHY RX DRIVERLukas Bulwahn1-1/+1
Commit f8aa660841bc ("phy: starfive: Add mipi dphy rx support") adds the MAINTAINERS section STARFIVE JH7110 DPHY RX DRIVER referring to 'phy-starfive-dphy-rx.c', but the file actually added in this commit is named 'phy-jh7110-dphy-rx.c'. Correct the file entry in STARFIVE JH7110 DPHY RX DRIVER. Signed-off-by: Lukas Bulwahn <[email protected]> Reviewed-by: Changhuang Liang <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-08-11phy: qcom: qmp-ufs: add missing offsets to sm8150 configurationDmitry Baryshkov1-0/+2
The conversion commit 7559e7572c03 ("phy: Explicitly include correct DT includes") misses offsets configuration for sm8150 (most likely it was developed separately from the series adding HS G4 support and was not adapted for the sm8150/sm8250 configuration split). Add missing offsets to sm8150_ufsphy_cfg. Fixes: 7559e7572c03 ("phy: Explicitly include correct DT includes") Signed-off-by: Dmitry Baryshkov <[email protected]> Reviewed-by: Konrad Dybcio <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-07-26phy: starfive: StarFive PHYs should depend on ARCH_STARFIVEGeert Uytterhoeven1-0/+4
The various StarFive PHYs are only present on StarFive SoCs. Hence add a dependency on ARCH_STARFIVE, to prevent asking the user about these drivers when configuring a kernel without StarFive SoC support. Signed-off-by: Geert Uytterhoeven <[email protected]> Acked-by: Changhuang Liang <[email protected]> Link: https://lore.kernel.org/r/12097f6107a18e2f7cfb80f47ac7b27808e062c4.1690300076.git.geert+renesas@glider.be Signed-off-by: Vinod Koul <[email protected]>
2023-07-25phy: starfive: make phys depend on HAS_IOMEMVinod Koul1-0/+1
the startfive phy drivers use devm_platform_ioremap_resource() which on some archs (s390) is not present. So make the drivers depend on HAS_IOMEM Fixes: f8aa660841bc ("phy: starfive: Add mipi dphy rx support") Reported-by: kernel test robot <[email protected]> Closes: https://lore.kernel.org/oe-kbuild-all/[email protected]/ Reviewed-by: Changhuang Liang <[email protected]> Signed-off-by: Vinod Koul <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-07-24phy: qcom-qmp-combo: add qcom,sc7280-qmp-usb3-dp-phy compat entryDmitry Baryshkov1-0/+4
Add separate device entry for Combo USB+DP QMP PHY on sc7280 platform. Reviewed-by: Neil Armstrong <[email protected]> Signed-off-by: Dmitry Baryshkov <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-07-24phy: qcom-qmp-combo: populate offsets for all combo PHYsDmitry Baryshkov1-0/+8
In order to support newer style bindings for combo PHYs, populate offsets for all Combo QMP PHY configurations. Reviewed-by: Neil Armstrong <[email protected]> Signed-off-by: Dmitry Baryshkov <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-07-24phy: qcom-qmp-combo: simplify clock handlingDmitry Baryshkov1-44/+23
For the existing PHYs for new binding we are going to drop ref_clk_src clock and always use ref clock. Rather than introducing additional code to handle legacy vs current bindings (and clock names), use devm_clk_bulk_get_optional() when new bindings are used and devm_clk_bulk_get_all() when legacy bindings are in place. Signed-off-by: Dmitry Baryshkov <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-07-24dt-bindings: phy: migrate combo QMP PHY bindings to ↵Dmitry Baryshkov2-286/+44
qcom,sc8280xp-qmp-usb43dp-phy.yaml Migrate legacy bindings (described in qcom,sc7180-qmp-usb3-dp-phy.yaml) to qcom,sc8280xp-qmp-usb43dp-phy.yaml. This removes a need to declare the child PHY node or split resource regions. Reviewed-by: Krzysztof Kozlowski <[email protected]> Signed-off-by: Dmitry Baryshkov <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-07-24phy: Remove duplicated include in xusb.cYang Li1-1/+0
./drivers/phy/tegra/xusb.c: linux/platform_device.h is included more than once. Reported-by: Abaci Robot <[email protected]> Closes: https://bugzilla.openanolis.cn/show_bug.cgi?id=5930 Signed-off-by: Yang Li <[email protected]> Acked-by: Thierry Reding <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-07-24phy: starfive: Add mipi dphy rx supportChanghuang Liang4-2/+251
Add mipi dphy rx support for the StarFive JH7110 SoC. It is used to transfer CSI camera data. Signed-off-by: Changhuang Liang <[email protected]> Reviewed-by: Minda Chen <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-07-24dt-bindings: phy: Add starfive,jh7110-dphy-rxChanghuang Liang1-0/+71
StarFive SoCs like the jh7110 use a MIPI D-PHY RX controller based on a M31 IP. Add a binding for it. Signed-off-by: Changhuang Liang <[email protected]> Reviewed-by: Rob Herring <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-07-24phy: starfive: fix error code in probeDan Carpenter1-1/+1
This is using the wrong pointer, "phy->regs" vs "phy->phy". Fixes: fd097f48eea9 ("phy: starfive: Add JH7110 PCIE 2.0 PHY driver") Signed-off-by: Dan Carpenter <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-07-18dt-bindings: phy: rockchip: add RK3588 PCIe v3 phySebastian Reichel1-5/+28
When the RK3568 PCIe v3 PHY supported has been upstreamed, RK3588 support was included, but the DT binding does not reflect this. This adds the missing bits. Reviewed-by: Conor Dooley <[email protected]> Signed-off-by: Sebastian Reichel <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-07-18phy: qcom-qmp-pcie: add support for sa8775pMrinmay Sarkar3-0/+344
Add support for dual and four lane PHY found on sa8755p platform. Signed-off-by: Mrinmay Sarkar <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-07-18dt-bindings: phy: qcom,qmp: Add sa8775p QMP PCIe PHYMrinmay Sarkar1-1/+18
Add devicetree YAML binding for Qualcomm QMP PCIe PHY for SA8775p platform. Signed-off-by: Mrinmay Sarkar <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-07-17phy: Explicitly include correct DT includesRob Herring81-65/+65
The DT of_device.h and of_platform.h date back to the separate of_platform_bus_type before it as merged into the regular platform bus. As part of that merge prepping Arm DT support 13 years ago, they "temporarily" include each other. They also include platform_device.h and of.h. As a result, there's a pretty much random mix of those include files used throughout the tree. In order to detangle these headers and replace the implicit includes with struct declarations, users need to explicitly include the correct includes. Signed-off-by: Rob Herring <[email protected]> Acked-by: Marc Kleine-Budde <[email protected]> # for drivers/phy/phy-can-transceiver.c Acked-by: Heiko Stuebner <[email protected]> Acked-by: Sergio Paracuellos <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-07-14phy: ti: gmii-sel: Allow parent to not be syscon nodeAndrew Davis1-3/+6
If the parent node is not a syscon type, then fallback and check if we can get a regmap from our own node. This no longer forces us to make the parent of this node a syscon node when that might not be appropriate. Signed-off-by: Andrew Davis <[email protected]> Reviewed-by: Roger Quadros <[email protected]> Reviewed-by: Siddharth Vadapalli <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-07-12phy: zynqmp: Allow variation in refclk rateSean Anderson1-1/+4
Due to limited available frequency ratios, the reference clock rate may not be exactly the same as the required rate. Allow a small (100 ppm) deviation. Signed-off-by: Sean Anderson <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-07-12phy: qcom-qmp-ufs: populate offsets configurationDmitry Baryshkov1-0/+10
Populate offsets configuration for the rest of UFS PHYs to make it possible to switch them to the new (single-node) bindings style. Reviewed-by: Bjorn Andersson <[email protected]> Signed-off-by: Dmitry Baryshkov <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-07-12dt-bindings: phy: migrate QMP UFS PHY bindings to qcom,sc8280xp-qmp-ufs-phy.yamlDmitry Baryshkov2-231/+45
Migrate legacy bindings (described in qcom,msm8996-qmp-ufs-phy.yaml) to qcom,sc8280xp-qmp-ufs-phy.yaml. This removes a need to declare the child PHY node or split resource regions. Reviewed-by: Krzysztof Kozlowski <[email protected]> Signed-off-by: Dmitry Baryshkov <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-07-12phy: starfive: Add JH7110 PCIE 2.0 PHY driverMinda Chen4-1/+218
Add Starfive JH7110 SoC PCIe 2.0 PHY driver support. PCIe 2.0 PHY default connect to PCIe controller. PCIe PHY can connect to USB 3.0 controller. Signed-off-by: Minda Chen <[email protected]> Reviewed-by: Roger Quadros <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-07-12phy: starfive: Add JH7110 USB 2.0 PHY driverMinda Chen6-0/+176
Add Starfive JH7110 SoC USB 2.0 PHY driver support. USB 2.0 PHY default connect to Cadence USB controller. Signed-off-by: Minda Chen <[email protected]> Reviewed-by: Roger Quadros <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-07-12dt-bindings: phy: Add StarFive JH7110 PCIe PHYMinda Chen1-0/+58
Add StarFive JH7110 SoC PCIe 2.0 PHY dt-binding. PCIe PHY0 (phy@10210000) can be used as USB 3.0 PHY. Signed-off-by: Minda Chen <[email protected]> Reviewed-by: Hal Feng <[email protected]> Reviewed-by: Rob Herring <[email protected]> Reviewed-by: Roger Quadros <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-07-12dt-bindings: phy: Add StarFive JH7110 USB PHYMinda Chen1-0/+50
Add StarFive JH7110 SoC USB 2.0 PHY dt-binding. Signed-off-by: Minda Chen <[email protected]> Reviewed-by: Hal Feng <[email protected]> Reviewed-by: Rob Herring <[email protected]> Reviewed-by: Roger Quadros <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-07-12phy: cadence: Sierra: Add single link SGMII register configurationMarcin Wierzbicki1-0/+98
Add single link SGMII register configuration for no SSC for cdns,sierra-phy-t0 compatibility string. The configuration is based on Sierra Programmer's Guide and validated in Cisco CrayAR SoC. Co-developed-by: Bartosz Wawrzyniak <[email protected]> Signed-off-by: Bartosz Wawrzyniak <[email protected]> Signed-off-by: Marcin Wierzbicki <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-07-12phy/rockchip: inno-hdmi: add more supported pre-pll ratesAlex Bee1-25/+173
This adds a bunch of new pixel clock- and tmds rates to the pre-pll table which are required to get more VESA and some DMT rates working. It has been completely re-calculated to match the min- and max-vco of (750 MHz - 3.2 GHz) requirements. If more than one configuration would have been possible the lowest fbdiv and refdiv (and therefore lowest vco rate) has been preferred. It's important to note, that RK3228 version of the phy does not support fractional dividers. To support the most possible rates for this version also in both 8-bit and 10-bit variant, some rates are not exact. The maximum deviation of the pixel clock is 0.26, which perfectly fits into VESA DMT recommendation of 0.5%. I tested all possible rates on several screens from different manufacturers with both RK3228 and RK3328. Both pre- and post-PLL locking are slighlty faster now. Signed-off-by: Alex Bee <[email protected]> Signed-off-by: Jonas Karlman <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-07-12phy/rockchip: inno-hdmi: force set_rate on power_onHuicong Xu1-0/+13
Regular 8-bit and Deep Color video formats mainly differ in TMDS rate and not in pixel clock rate. When the hdmiphy clock is configured with the same pixel clock rate using clk_set_rate() the clock framework do not signal the hdmi phy driver to set_rate when switching between 8-bit and Deep Color. This result in pre/post pll not being re-configured when switching between regular 8-bit and Deep Color video formats. Fix this by calling set_rate in power_on to force pre pll re-configuration. Signed-off-by: Huicong Xu <[email protected]> Signed-off-by: Jonas Karlman <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-07-12phy/rockchip: inno-hdmi: do not power on rk3328 post pll on reg writeJonas Karlman1-2/+4
inno_write is used to configure 0xaa reg, that also hold the POST_PLL_POWER_DOWN bit. When POST_PLL_REFCLK_SEL_TMDS is configured the power down bit is not taken into consideration. Fix this by keeping the power down bit until configuration is complete. Also reorder the reg write order for consistency. Fixes: 53706a116863 ("phy: add Rockchip Innosilicon hdmi phy") Signed-off-by: Jonas Karlman <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-07-12phy/rockchip: inno-hdmi: remove unused no_c from rk3328 recalc_rateJonas Karlman1-4/+1
no_c is not used in any calculation, lets remove it. Signed-off-by: Jonas Karlman <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2023-07-12phy/rockchip: inno-hdmi: round fractal pixclock in rk3328 recalc_rateZheng Yang1-3/+5
inno_hdmi_phy_rk3328_clk_recalc_rate() is returning a rate not found in the pre pll config table when the fractal divider is used. This can prevent proper power_on because a tmdsclock for the new rate is not found in the pre pll config table. Fix this by saving and returning a rounded pixel rate that exist in the pre pll config table. Fixes: 53706a116863 ("phy: add Rockchip Innosilicon hdmi phy") Signed-off-by: Zheng Yang <[email protected]> Signed-off-by: Jonas Karlman <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
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