diff options
| author | Sebastian Reichel <[email protected]> | 2023-07-17 19:35:11 +0200 |
|---|---|---|
| committer | Vinod Koul <[email protected]> | 2023-07-18 11:45:05 +0530 |
| commit | f66782cff479807ad7e98f0cf6a0c0babfe0159b (patch) | |
| tree | 8cf41d6260bf668707265a4b73accc666b214da7 | |
| parent | a05b6d5135ec3e65520ae0eaa1b24d4c6549424e (diff) | |
dt-bindings: phy: rockchip: add RK3588 PCIe v3 phy
When the RK3568 PCIe v3 PHY supported has been upstreamed, RK3588
support was included, but the DT binding does not reflect this.
This adds the missing bits.
Reviewed-by: Conor Dooley <[email protected]>
Signed-off-by: Sebastian Reichel <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Vinod Koul <[email protected]>
| -rw-r--r-- | Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml | 33 |
1 files changed, 28 insertions, 5 deletions
diff --git a/Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml b/Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml index 9f2d8d2cc7a5..c4fbffcde6e4 100644 --- a/Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml +++ b/Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml @@ -13,19 +13,18 @@ properties: compatible: enum: - rockchip,rk3568-pcie3-phy + - rockchip,rk3588-pcie3-phy reg: maxItems: 1 clocks: - minItems: 3 + minItems: 1 maxItems: 3 clock-names: - items: - - const: refclk_m - - const: refclk_n - - const: pclk + minItems: 1 + maxItems: 3 data-lanes: description: which lanes (by position) should be mapped to which @@ -61,6 +60,30 @@ required: - rockchip,phy-grf - "#phy-cells" +allOf: + - if: + properties: + compatible: + enum: + - rockchip,rk3588-pcie3-phy + then: + properties: + clocks: + maxItems: 1 + clock-names: + items: + - const: pclk + else: + properties: + clocks: + minItems: 3 + + clock-names: + items: + - const: refclk_m + - const: refclk_n + - const: pclk + additionalProperties: false examples: |