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Use the internal port number also as the queue number on CN68XX.
Signed-off-by: Janne Huttunen <[email protected]>
Signed-off-by: Aaro Koskinen <[email protected]>
Acked-by: David Daney <[email protected]>
Cc: David Daney <[email protected]>
Cc: [email protected]
Cc: Janne Huttunen <[email protected]>
Cc: Aaro Koskinen <[email protected]>
Cc: Greg Kroah-Hartman <[email protected]>
Cc: [email protected]
Patchwork: https://patchwork.linux-mips.org/patch/10962/
Signed-off-by: Ralf Baechle <[email protected]>
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CN68XX requires a different PKO configuration. This patch provides
just enough setup to get the XAUI interfaces on CN6880 working with
default parameters.
Signed-off-by: Janne Huttunen <[email protected]>
Signed-off-by: Aaro Koskinen <[email protected]>
Acked-by: David Daney <[email protected]>
Cc: David Daney <[email protected]>
Cc: [email protected]
Cc: Janne Huttunen <[email protected]>
Cc: Aaro Koskinen <[email protected]>
Cc: Greg Kroah-Hartman <[email protected]>
Cc: [email protected]
Patchwork: https://patchwork.linux-mips.org/patch/10974/
Signed-off-by: Ralf Baechle <[email protected]>
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CN68XX has a bit different WQE structure. This patch provides the new
definitions and converts the code to use the proper variant based on
the actual model.
Signed-off-by: Janne Huttunen <[email protected]>
Signed-off-by: Aaro Koskinen <[email protected]>
Acked-by: David Daney <[email protected]>
Cc: David Daney <[email protected]>
Cc: [email protected]
Cc: Janne Huttunen <[email protected]>
Cc: Aaro Koskinen <[email protected]>
Cc: Greg Kroah-Hartman <[email protected]>
Cc: [email protected]
Patchwork: https://patchwork.linux-mips.org/patch/10973/
Signed-off-by: Ralf Baechle <[email protected]>
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The Octeon II models have more interfaces and thus require more output
command buffers. Increase the allocation to support these models.
Signed-off-by: Janne Huttunen <[email protected]>
Signed-off-by: Aaro Koskinen <[email protected]>
Acked-by: David Daney <[email protected]>
Cc: David Daney <[email protected]>
Cc: [email protected]
Cc: Janne Huttunen <[email protected]>
Cc: Aaro Koskinen <[email protected]>
Cc: Greg Kroah-Hartman <[email protected]>
Cc: [email protected]
Patchwork: https://patchwork.linux-mips.org/patch/10965/
Signed-off-by: Ralf Baechle <[email protected]>
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CN68XX uses SSO instead of POW.
Signed-off-by: Aaro Koskinen <[email protected]>
Acked-by: David Daney <[email protected]>
Cc: David Daney <[email protected]>
Cc: [email protected]
Cc: Janne Huttunen <[email protected]>
Cc: Aaro Koskinen <[email protected]>
Cc: Greg Kroah-Hartman <[email protected]>
Cc: [email protected]
Patchwork: https://patchwork.linux-mips.org/patch/10966/
Signed-off-by: Ralf Baechle <[email protected]>
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The Octeon models with SSO instead of POW need to use a different register
for configuring the WQE interrupt thresholds.
Signed-off-by: Aaro Koskinen <[email protected]>
Acked-by: David Daney <[email protected]>
Cc: David Daney <[email protected]>
Cc: [email protected]
Cc: Janne Huttunen <[email protected]>
Cc: Aaro Koskinen <[email protected]>
Cc: Greg Kroah-Hartman <[email protected]>
Cc: [email protected]
Patchwork: https://patchwork.linux-mips.org/patch/10964/
Signed-off-by: Ralf Baechle <[email protected]>
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Some Octeon II models have SSO instead of POW and use a different register
for setting the interrupt thresholds. Add the necessary definitions for
configuring the interrupts also on those models.
Signed-off-by: Janne Huttunen <[email protected]>
Signed-off-by: Aaro Koskinen <[email protected]>
Acked-by: David Daney <[email protected]>
Cc: David Daney <[email protected]>
Cc: [email protected]
Cc: Janne Huttunen <[email protected]>
Cc: Aaro Koskinen <[email protected]>
Cc: Greg Kroah-Hartman <[email protected]>
Cc: [email protected]
Patchwork: https://patchwork.linux-mips.org/patch/10972/
Signed-off-by: Ralf Baechle <[email protected]>
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CN68XX has common minimum packet size filters that need to be configured
for the traffic to work. Just set them to a default value.
Signed-off-by: Janne Huttunen <[email protected]>
Signed-off-by: Aaro Koskinen <[email protected]>
Acked-by: David Daney <[email protected]>
Cc: David Daney <[email protected]>
Cc: [email protected]
Cc: Janne Huttunen <[email protected]>
Cc: Aaro Koskinen <[email protected]>
Cc: Greg Kroah-Hartman <[email protected]>
Cc: [email protected]
Patchwork: https://patchwork.linux-mips.org/patch/10963/
Signed-off-by: Ralf Baechle <[email protected]>
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Configure the pkinds of XAUI interfaces on Octeon models that have
them. This simple configuration uses 1:1 mapping between the PIP input
port number and the selected pkind.
Signed-off-by: Janne Huttunen <[email protected]>
Signed-off-by: Aaro Koskinen <[email protected]>
Acked-by: David Daney <[email protected]>
Cc: David Daney <[email protected]>
Cc: [email protected]
Cc: Janne Huttunen <[email protected]>
Cc: Aaro Koskinen <[email protected]>
Cc: Greg Kroah-Hartman <[email protected]>
Cc: [email protected]
Patchwork: https://patchwork.linux-mips.org/patch/10971/
Signed-off-by: Ralf Baechle <[email protected]>
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CN68XX has 48 PIP input ports.
Signed-off-by: Janne Huttunen <[email protected]>
Signed-off-by: Aaro Koskinen <[email protected]>
Acked-by: David Daney <[email protected]>
Cc: David Daney <[email protected]>
Cc: [email protected]
Cc: Janne Huttunen <[email protected]>
Cc: Aaro Koskinen <[email protected]>
Cc: Greg Kroah-Hartman <[email protected]>
Cc: [email protected]
Patchwork: https://patchwork.linux-mips.org/patch/10969/
Signed-off-by: Ralf Baechle <[email protected]>
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CN68XX has 9 interfaces.
Signed-off-by: Janne Huttunen <[email protected]>
Signed-off-by: Aaro Koskinen <[email protected]>
Acked-by: David Daney <[email protected]>
Cc: David Daney <[email protected]>
Cc: [email protected]
Cc: Janne Huttunen <[email protected]>
Cc: Aaro Koskinen <[email protected]>
Cc: Greg Kroah-Hartman <[email protected]>
Cc: [email protected]
Patchwork: https://patchwork.linux-mips.org/patch/10968/
Signed-off-by: Ralf Baechle <[email protected]>
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Some CN68XX series Octeon II chips seem to hang if a reset is issued on
XAUI initialization. Avoid the hang by disabling the reset on affected
models. Tested on Cavium EBB6800 evaluation board and Kontron S1901 board.
Signed-off-by: Janne Huttunen <[email protected]>
Signed-off-by: Aaro Koskinen <[email protected]>
Acked-by: David Daney <[email protected]>
Cc: David Daney <[email protected]>
Cc: [email protected]
Cc: Janne Huttunen <[email protected]>
Cc: Aaro Koskinen <[email protected]>
Cc: Greg Kroah-Hartman <[email protected]>
Cc: [email protected]
Patchwork: http://patchwork.linux-mips.org/patch/10970/
Signed-off-by: Ralf Baechle <[email protected]>
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This commit introduces a new config, so the user can choose to enable
the General Purpose Timer based clocksource. This option is required
to have CPUFreq support.
Signed-off-by: Ezequiel Garcia <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: Daniel Lezcano <[email protected]>
Cc: [email protected]
Cc: Thomas Gleixner <[email protected]>
Cc: Andrew Bresticker <[email protected]>
Cc: James Hartley <[email protected]>
Cc: Govindraj Raja <[email protected]>
Cc: Damien Horsley <[email protected]>
Cc: James Hogan <[email protected]>
Cc: Ezequiel Garcia <[email protected]>
Cc: Ezequiel Garcia <[email protected]>
Patchwork: http://patchwork.linux-mips.org/patch/10887/
Signed-off-by: Ralf Baechle <[email protected]>
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The Pistachio SoC provides four general purpose timers, and allow
to implement a clocksource driver.
This driver can be used as a replacement for the MIPS GIC and MIPS R4K
clocksources and sched clocks, which are clocked from the CPU clock.
Given the general purpose timers are clocked from an independent clock,
this new clocksource driver will be useful to introduce CPUFreq support
for Pistachio machines.
Signed-off-by: Ezequiel Garcia <[email protected]>
Signed-off-by: Govindraj Raja <[email protected]>
Reviewed-by: Thomas Gleixner <[email protected]>
Acked-by: Daniel Lezcano <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: Andrew Bresticker <[email protected]>
Cc: James Hartley <[email protected]>
Cc: Damien Horsley <[email protected]>
Cc: James Hogan <[email protected]>
Cc: Ezequiel Garcia <[email protected]>
Cc: Ezequiel Garcia <[email protected]>
Patchwork: https://patchwork.linux-mips.org/patch/10899/
Signed-off-by: Ralf Baechle <[email protected]>
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Add a device-tree binding document for the clocksource driver provided
by Pistachio SoC general purpose timers.
Signed-off-by: Ezequiel Garcia <[email protected]>
Reviewed-by: Andrew Bresticker <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: Daniel Lezcano <[email protected]>
Cc: [email protected]
Cc: Thomas Gleixner <[email protected]>
Cc: James Hartley <[email protected]>
Cc: Govindraj Raja <[email protected]>
Cc: Damien Horsley <[email protected]>
Cc: James Hogan <[email protected]>
Cc: Ezequiel Garcia <[email protected]>
Patchwork: https://patchwork.linux-mips.org/patch/10783/
Signed-off-by: Ralf Baechle <[email protected]>
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This commit introduces the clockevent frequency update, using
a clock notifier. It will be used to support CPUFreq on platforms
using MIPS GIC based clockevents.
Signed-off-by: Ezequiel Garcia <[email protected]>
Acked-by: Daniel Lezcano <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: Thomas Gleixner <[email protected]>
Cc: Andrew Bresticker <[email protected]>
Cc: James Hartley <[email protected]>
Cc: Govindraj Raja <[email protected]>
Cc: Damien Horsley <[email protected]>
Cc: James Hogan <[email protected]>
Cc: Ezequiel Garcia <[email protected]>
Patchwork: https://patchwork.linux-mips.org/patch/10782/
Signed-off-by: Ralf Baechle <[email protected]>
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Now that we're ready to enable COMMON_CLK for GIC platforms do so for
Malta and SEAD3. The only other user of the GIC Pistachio does already
do so.
[[email protected]: Rewrite the commit message because applied in the
right order there is no breakage thus no fix required.]
Signed-off-by: Guenter Roeck <[email protected]>
Cc: Ezequiel Garcia <[email protected]>
Cc: Daniel Lezcano <[email protected]>
Cc: [email protected]
Cc: [email protected]
Patchwork: https://patchwork.linux-mips.org/patch/11038/
Signed-off-by: Ralf Baechle <[email protected]>
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This is preparation work for the introduction of clockevent frequency
update with a clock notifier. This is only possible when the device
is passed a clk struct, so let's split the legacy and devicetree
initialization.
Reviewed-by: Andrew Bresticker <[email protected]>
Signed-off-by: Ezequiel Garcia <[email protected]>
Acked-by: Daniel Lezcano <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: Thomas Gleixner <[email protected]>
Cc: James Hartley <[email protected]>
Cc: Govindraj Raja <[email protected]>
Cc: Damien Horsley <[email protected]>
Cc: James Hogan <[email protected]>
Cc: Ezequiel Garcia <[email protected]>
Patchwork: https://patchwork.linux-mips.org/patch/10781/
Signed-off-by: Ralf Baechle <[email protected]>
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This commit adds the required checks on the functions that return
an error. Some of them are not critical, so only a warning is
printed.
Signed-off-by: Ezequiel Garcia <[email protected]>
Reviewed-by: Andrew Bresticker <[email protected]>
Acked-by: Daniel Lezcano <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: Thomas Gleixner <[email protected]>
Cc: James Hartley <[email protected]>
Cc: Govindraj Raja <[email protected]>
Cc: Damien Horsley <[email protected]>
Cc: James Hogan <[email protected]>
Cc: Ezequiel Garcia <[email protected]>
Patchwork: https://patchwork.linux-mips.org/patch/10780/
Signed-off-by: Ralf Baechle <[email protected]>
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For the clock to be used (e.g. get its rate through clk_get_rate)
it should be prepared and enabled first.
Also, while the clock is enabled the driver must hold a reference to it,
so let's remove the call to clk_put.
Reviewed-by: Andrew Bresticker <[email protected]>
Signed-off-by: Ezequiel Garcia <[email protected]>
Acked-by: Daniel Lezcano <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: Thomas Gleixner <[email protected]>
Cc: James Hartley <[email protected]>
Cc: Govindraj Raja <[email protected]>
Cc: Damien Horsley <[email protected]>
Cc: James Hogan <[email protected]>
Cc: Ezequiel Garcia <[email protected]>
Patchwork: https://patchwork.linux-mips.org/patch/10779/
Signed-off-by: Ralf Baechle <[email protected]>
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Rather than saving the scalar FP or vector context in the assembly
resume function, reuse the existing C code we have in fpu.h to do
exactly that. This reduces duplication, results in a much easier to read
resume function & should allow the compiler to optimise out more MSA
code due to is_msa_enabled()/cpu_has_msa being known-zero at compile
time for kernels without MSA support.
Signed-off-by: Paul Burton <[email protected]>
Cc: [email protected]
Cc: Leonid Yegoshin <[email protected]>
Cc: Maciej W. Rozycki <[email protected]>
Cc: [email protected]
Cc: James Hogan <[email protected]>
Cc: Markos Chandras <[email protected]>
Cc: Manuel Lauss <[email protected]>
Patchwork: https://patchwork.linux-mips.org/patch/10830/
Signed-off-by: Ralf Baechle <[email protected]>
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Fix the 0x0x prefix in integer constants, in this case the registers
interval is actually 0x8065 .. 0x80A4 as confirmed some lines above in
the code.
Signed-off-by: Antonio Ospite <[email protected]>
Cc: [email protected]
Cc: Jiri Kosina <[email protected]>
Patchwork: https://patchwork.linux-mips.org/patch/9908/
Signed-off-by: Ralf Baechle <[email protected]>
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Signed-off-by: Ralf Baechle <[email protected]>
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Signed-off-by: Ralf Baechle <[email protected]>
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This reverts commit 7281cd22973008a782860e48ed8d85d00204168c and adds
actual functionality to use the field.
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Add NAND IRQ mapping for XLP9xx processor.
Signed-off-by: Subhendu Sekhar Behera <[email protected]>
Signed-off-by: Jayachandran C <[email protected]>
Cc: [email protected]
Patchwork: https://patchwork.linux-mips.org/patch/10820/
Signed-off-by: Ralf Baechle <[email protected]>
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This is needed to enable GPIO framework support for Netlogic XLP platform.
Signed-off-by: Kamlakant Patel <[email protected]>
Signed-off-by: Jayachandran C <[email protected]>
Cc: [email protected]
Patchwork: https://patchwork.linux-mips.org/patch/10818/
Signed-off-by: Ralf Baechle <[email protected]>
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Add GPIO entries to the Netlogic XLP device tree files.
Signed-off-by: Kamlakant Patel <[email protected]>
Signed-off-by: Jayachandran C <[email protected]>
Cc: [email protected]
Patchwork: https://patchwork.linux-mips.org/patch/10819/
Signed-off-by: Ralf Baechle <[email protected]>
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Update mips/netlogic/common/irq.c and mips/pci/msi-xlp.c to use chip_data
to store interrupt controller data pointer. It uses handler_data now,
and that causes errors when an API (like the GPIO subsystem) tries to
use the handler data.
Signed-off-by: Kamlakant Patel <[email protected]>
Signed-off-by: Jayachandran C <[email protected]>
Cc: [email protected]
Patchwork: https://patchwork.linux-mips.org/patch/10817/
Signed-off-by: Ralf Baechle <[email protected]>
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Currently CONFIG_ARCH_HAVE_CUSTOM_GPIO_H is defined for all MIPS
machines, and each machine type provides its own gpio.h. However
only a handful really implement the GPIO API, most just forward
everythings to gpiolib.
The Alchemy machine is notable as it provides a system to allow
implementing the GPIO API at the board level. But it is not used by
any board currently supported, so it can also be removed.
For most machine types we can just remove the custom gpio.h, as well
as the custom wrappers if some exists. Some of the code found in
the wrappers must be moved to the respective GPIO driver.
A few more fixes are need in some drivers as they rely on linux/gpio.h
to provides some machine specific definitions, or used asm/gpio.h
instead of linux/gpio.h for the gpio API.
Signed-off-by: Alban Bedel <[email protected]>
Reviewed-by: Linus Walleij <[email protected]>
Cc: [email protected]
Cc: Hauke Mehrtens <[email protected]>
Cc: Rafał Miłecki <[email protected]>
Cc: Bartlomiej Zolnierkiewicz <[email protected]>
Cc: Tejun Heo <[email protected]>
Cc: Alexandre Courbot <[email protected]>
Cc: Dmitry Torokhov <[email protected]>
Cc: Florian Fainelli <[email protected]>
Cc: Manuel Lauss <[email protected]>
Cc: Joe Perches <[email protected]>
Cc: Daniel Walter <[email protected]>
Cc: Sergey Ryazanov <[email protected]>
Cc: Huacai Chen <[email protected]>
Cc: James Hartley <[email protected]>
Cc: Andrew Bresticker <[email protected]>
Cc: Paul Burton <[email protected]>
Cc: Jiri Kosina <[email protected]>
Cc: Bjorn Helgaas <[email protected]>
Cc: Wolfram Sang <[email protected]>
Cc: Randy Dunlap <[email protected]>
Cc: Varka Bhadram <[email protected]>
Cc: Masanari Iida <[email protected]>
Cc: Tomi Valkeinen <[email protected]>
Cc: Michael Buesch <[email protected]>
Cc: abdoulaye berthe <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Patchwork: https://patchwork.linux-mips.org/patch/10828/
Signed-off-by: Ralf Baechle <[email protected]>
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GPIO drivers should be in drivers/gpio
Signed-off-by: Alban Bedel <[email protected]>
Acked-by: Linus Walleij <[email protected]>
Cc: [email protected]
Cc: Alexandre Courbot <[email protected]>
Cc: Gabor Juhos <[email protected]>
Cc: [email protected]
Cc: [email protected]
Patchwork: https://patchwork.linux-mips.org/patch/10597/
Signed-off-by: Ralf Baechle <[email protected]>
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To prepare moving the GPIO driver to drivers/gpio remove the
platform specific pinmux API. As it is not used by any board,
and such functionality should better be implemented using the
pinmux subsystem just removing it seems to be the best option.
Signed-off-by: Alban Bedel <[email protected]>
Acked-by: Linus Walleij <[email protected]>
Cc: [email protected]
Cc: Alexandre Courbot <[email protected]>
Cc: Gabor Juhos <[email protected]>
Cc: [email protected]
Cc: [email protected]
Patchwork: https://patchwork.linux-mips.org/patch/10596/
Signed-off-by: Ralf Baechle <[email protected]>
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On MIPS64 we have spinlocks that are 32b in size and an efficient
cmpxchg64 implementation, so we qualify to make use of cmpxchg backed
lockrefs. Select the ARCH_USE_CMPXCHG_LOCKREF Kconfig symbol and provide
a trivial implementation of arch_spin_value_unlocked to satisfy the
lockref code.
Using Linus' simple testcase from
http://article.gmane.org/gmane.linux.file-systems/77466 on a dual core
system with an in-development MIPS64 CPU running on FPGA I see around an
8% gain:
Pre-patch:
Total loops: 252698
Total loops: 251482
Total loops: 250806
Total loops: 252885
Total loops: 251666
Post-patch:
Total loops: 273728
Total loops: 269932
Total loops: 269341
Total loops: 275004
Total loops: 270208
[[email protected]: Fixed conflict.]
Signed-off-by: Paul Burton <[email protected]>
Cc: [email protected]
Cc: Steven J. Hill <[email protected]>
Cc: [email protected]
Cc: Maciej W. Rozycki <[email protected]>
Cc: Markos Chandras <[email protected]>
Patchwork: https://patchwork.linux-mips.org/patch/10810/
Signed-off-by: Ralf Baechle <[email protected]>
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MIPS was using finish_arch_switch() as a hook to restore and initialize
CPU context for all threads, even newly created kernel and user threads.
This is however entirely solvable within switch_to() so get rid of
finish_arch_switch() which is in the way of scheduler cleanups.
Signed-off-by: Ralf Baechle <[email protected]>
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The Ingenic-specific write combining cache attribute was defined based
on CONFIG_MACH_JZ4740 and therefore not used on JZ4780. Change this to
CONFIG_MACH_INGENIC so that it gets used on all Ingenic platforms.
Signed-off-by: Alex Smith <[email protected]>
Cc: [email protected]
Patchwork: https://patchwork.linux-mips.org/patch/10769/
Signed-off-by: Ralf Baechle <[email protected]>
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The generic implementation of dma_map_ops.mmap(), dma_common_mmap(),
is not correct for non-coherent devices. It expects to be passed a
virtual address previously returned by dma_alloc_coherent(), which for
a non-coherent device will return a KSEG1 address. It then attempts to
convert that virtual address to a physical address using virt_to_page()
which will yield an incorrect address.
Also, dma_common_mmap() does not handle the DMA_ATTR_WRITE_COMBINE
attribute, and therefore dma_mmap_writecombine() will not actually set
the appropriate pgprot_t flags for write combining.
This patch adds an implementation of dma_map_ops.mmap() that correctly
handles KSEG1 addresses, and enables write combining when requested.
Signed-off-by: Alex Smith <[email protected]>
Cc: Sadegh Abbasi <[email protected]>
Cc: [email protected]
Patchwork: https://patchwork.linux-mips.org/patch/10808/
Signed-off-by: Ralf Baechle <[email protected]>
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If pgprot_writecombine is not #defined, asm-generic/pgtable.h will try
to provide a default implementation by #defining it to pgprot_noncached.
However our implementation is an inline function rather than a #define,
so it was never actually used because of the #define in generic code.
Add "#define pgprot_writecombine pgprot_writecombine" to prevent generic
code from re-defining it.
Signed-off-by: Alex Smith <[email protected]>
Cc: [email protected]
Patchwork: https://patchwork.linux-mips.org/patch/10767/
Signed-off-by: Ralf Baechle <[email protected]>
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CONFIG_MIPS_O32_FP64_SUPPORT and CONFIG_CPU_HAS_MSA are in pretty good
shape these days, and in much wider use than they once were. Stop
referring to them as EXPERIMENTAL.
Signed-off-by: Paul Burton <[email protected]>
Cc: [email protected]
Cc: Guenter Roeck <[email protected]>
Cc: Matthew Fortune <[email protected]>
Cc: [email protected]
Patchwork: https://patchwork.linux-mips.org/patch/10801/
Signed-off-by: Ralf Baechle <[email protected]>
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If MSA is supported by both the hardware & the kernel then advertise
that support to userland via the AT_HWCAP aux vector.
Signed-off-by: Paul Burton <[email protected]>
Cc: [email protected]
Cc: Guenter Roeck <[email protected]>
Cc: Matthew Fortune <[email protected]>
Cc: Leonid Yegoshin <[email protected]>
Cc: Maciej W. Rozycki <[email protected]>
Cc: [email protected]
Cc: Huacai Chen <[email protected]>
Cc: Markos Chandras <[email protected]>
Patchwork: https://patchwork.linux-mips.org/patch/10799/
Signed-off-by: Ralf Baechle <[email protected]>
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When running on a CPU implementing the release 6 of the MIPS32 or MIPS64
ISA, advertise that to userland via the appropriate HWCAP bit.
Signed-off-by: Paul Burton <[email protected]>
Cc: [email protected]
Cc: Guenter Roeck <[email protected]>
Cc: Matthew Fortune <[email protected]>
Cc: Leonid Yegoshin <[email protected]>
Cc: Maciej W. Rozycki <[email protected]>
Cc: [email protected]
Cc: Huacai Chen <[email protected]>
Cc: Markos Chandras <[email protected]>
Patchwork: https://patchwork.linux-mips.org/patch/10798/
Signed-off-by: Ralf Baechle <[email protected]>
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In order for userland to determine whether various features are safe to
use, it will need to know both that the hardware supports those features
and that the kernel is recent enough & configured appropriately to
support them. For example under the O32 modeless FP proposal the dynamic
linker & ifunc resolvers will need this information. The kernel is the
only thing in a position to know availability accurately, so the kernel
needs to provide the information to userland. This patch introduces the
infrastructure to provide the AT_HWCAP aux vector to userland in order
to provide that information. It also defines the 2 currently specified
flags, which indicate MIPSr6 & MSA support.
Signed-off-by: Paul Burton <[email protected]>
Cc: [email protected]
Cc: Guenter Roeck <[email protected]>
Cc: Matthew Fortune <[email protected]>
Cc: Kees Cook <[email protected]>
Cc: Huacai Chen <[email protected]>
Cc: Maciej W. Rozycki <[email protected]>
Cc: Alex Smith <[email protected]>
Cc: [email protected]
Cc: Leonid Yegoshin <[email protected]>
Cc: Markos Chandras <[email protected]>
Cc: Ingo Molnar <[email protected]>
Patchwork: https://patchwork.linux-mips.org/patch/10797/
Signed-off-by: Ralf Baechle <[email protected]>
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It is desirable for signal handlers to be allowed to make use of MSA,
particularly if auto vectorisation is used when compiling a program.
The MSA context must therefore be saved & restored before & after
invoking the signal handler. Make use of the extended context structs
defined in the preceding patch to save MSA context after the sigframe
when appropriate.
[[email protected]: Fixed conflicts.]
Signed-off-by: Paul Burton <[email protected]>
Cc: [email protected]
Cc: Guenter Roeck <[email protected]>
Cc: Matthew Fortune <[email protected]>
Cc: Leonid Yegoshin <[email protected]>
Cc: [email protected]
Cc: Richard Weinberger <[email protected]>
Cc: James Hogan <[email protected]>
Cc: Andrew Morton <[email protected]>
Cc: Andy Lutomirski <[email protected]>
Cc: Markos Chandras <[email protected]>
Cc: Manuel Lauss <[email protected]>
Cc: Maciej W. Rozycki <[email protected]>
Patchwork: https://patchwork.linux-mips.org/patch/10796/
Signed-off-by: Ralf Baechle <[email protected]>
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The context introduced by MSA needs to be saved around signals. However,
we can't increase the size of struct sigcontext because that will change
the offset of the signal mask in struct sigframe or struct ucontext.
This patch instead places the new context immediately after the struct
sigframe for traditional signals, or similarly after struct ucontext for
RT signals. The layout of struct sigframe & struct ucontext is identical
from their sigcontext fields onwards, so the offset from the sigcontext
to the extended context will always be the same regardless of the type
of signal.
Userland will be able to search through the extended context by using
the magic values to detect which types of context are present. Any
unrecognised context can be skipped over using the size field of struct
extcontext. Once the magic value END_EXTCONTEXT_MAGIC is seen it is
known that there are no further extended context structures to examine.
This approach is somewhat similar to that taken by ARM to save VFP &
other context at the end of struct ucontext.
Userland can determine whether extended context is present by checking
for the USED_EXTCONTEXT bit in the sc_used_math field of struct
sigcontext. Whilst this could potentially change the historic semantics
of sc_used_math if further extended context which does not imply FP
context were to be introduced in the future, I have been unable to find
any userland code making use of sc_used_math at all. Using one of the
fields described as unused in struct sigcontext was considered, but the
kernel does not already write to those fields so there would be no
guarantee of the field being clear on older kernels. Other alternatives
would be to have userland check the kernel version, or to have a HWCAP
bit indicating presence of extended context. However there is a desire
to have the context & information required to decode it be self
contained such that, for example, debuggers could decode the saved
context easily.
[[email protected]: Fixed conflict.]
Signed-off-by: Paul Burton <[email protected]>
Cc: [email protected]
Cc: Guenter Roeck <[email protected]>
Cc: Matthew Fortune <[email protected]>
Cc: Peter Zijlstra <[email protected]>
Cc: Zubair Lutfullah Kakakhel <[email protected]>
Cc: Alex Smith <[email protected]>
Cc: [email protected]
Cc: Richard Weinberger <[email protected]>
Cc: Andrew Morton <[email protected]>
Cc: Andy Lutomirski <[email protected]>
Cc: Michael Ellerman <[email protected]>
Cc: Markos Chandras <[email protected]>
Cc: Daniel Borkmann <[email protected]>
Cc: Maciej W. Rozycki <[email protected]>
Patchwork: https://patchwork.linux-mips.org/patch/10795/
Signed-off-by: Ralf Baechle <[email protected]>
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The sc_used_math field of struct sigcontext & its variants has
traditionally been used as a boolean value indicating only whether or
not floating point context is saved within the sigcontext. With various
supported FP modes & the ability to switch between them this information
will no longer be enough to decode the meaning of the data stored in the
sc_fpregs fields of struct sigcontext.
To make that possible 3 bits are defined within sc_used_math:
- Bit 0 (USED_FP) represents whether FP was used, essentially
providing the boolean flag which sc_used_math as a whole provided
previously.
- Bit 1 (USED_FR1) provides the value of the Status.FR bit at the time
the FP context was saved.
- Bit 2 (USED_HYBRID_FPRS) indicates whether the FP context was saved
under the hybrid FPR scheme. Essentially, when set the odd singles
are located in bits 63:32 of the preceding even indexed sc_fpregs
element.
Any userland that tests whether the sc_used_math field is zero or
non-zero will continue to function as expected. Having said that, I
could not find any userland which uses the sc_used_math field at all.
[[email protected]: Fixed rejects.]
Signed-off-by: Paul Burton <[email protected]>
Cc: [email protected]
Cc: Guenter Roeck <[email protected]>
Cc: Matthew Fortune <[email protected]>
Cc: Michael Ellerman <[email protected]>
Cc: [email protected]
Cc: Richard Weinberger <[email protected]>
Cc: Andy Lutomirski <[email protected]>
Cc: Maciej W. Rozycki <[email protected]>
Patchwork: https://patchwork.linux-mips.org/patch/10794/
Signed-off-by: Ralf Baechle <[email protected]>
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These functions are never called & thus dead code. Remove them.
Signed-off-by: Paul Burton <[email protected]>
Cc: [email protected]
Cc: Guenter Roeck <[email protected]>
Cc: Matthew Fortune <[email protected]>
Cc: Michael Ellerman <[email protected]>
Cc: [email protected]
Cc: Richard Weinberger <[email protected]>
Cc: Andy Lutomirski <[email protected]>
Cc: Andrew Morton <[email protected]>
Patchwork: https://patchwork.linux-mips.org/patch/10793/
Signed-off-by: Ralf Baechle <[email protected]>
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Make use of the common FP sigcontext code for O32 binaries running on
MIPS64 kernels now that it is taking appropriate offsets into struct
sigcontext(32) from struct mips_abi.
[[email protected]: Fixed reject.]
Signed-off-by: Paul Burton <[email protected]>
Cc: [email protected]
Cc: Guenter Roeck <[email protected]>
Cc: Matthew Fortune <[email protected]>
Cc: Leonid Yegoshin <[email protected]>
Cc: Michael Ellerman <[email protected]>
Cc: [email protected]
Cc: Richard Weinberger <[email protected]>
Cc: James Hogan <[email protected]>
Cc: Andrew Morton <[email protected]>
Cc: Andy Lutomirski <[email protected]>
Cc: Markos Chandras <[email protected]>
Cc: Manuel Lauss <[email protected]>
Cc: Maciej W. Rozycki <[email protected]>
Patchwork: https://patchwork.linux-mips.org/patch/10792/
Signed-off-by: Ralf Baechle <[email protected]>
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When a task uses 32 bit floating point, the odd indexed 32b register
values are stored in bits 63:32 of the preceding even indexed 64b
FP register field in saved context. Thus there is no point in
preserving the odd indexed 64b register fields since they hold no
valid context. This patch will cause them to be skipped, as is
already done in arch/mips/kernel/signal32.c.
[[email protected]: Fixed reject.]
Signed-off-by: Paul Burton <[email protected]>
Cc: [email protected]
Cc: Guenter Roeck <[email protected]>
Cc: Matthew Fortune <[email protected]>
Cc: Michael Ellerman <[email protected]>
Cc: [email protected]
Cc: Richard Weinberger <[email protected]>
Cc: Andy Lutomirski <[email protected]>
Cc: Maciej W. Rozycki <[email protected]>
Cc: Andrew Morton <[email protected]>
Patchwork: https://patchwork.linux-mips.org/patch/10791/
Signed-off-by: Ralf Baechle <[email protected]>
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In preparation for sharing protected_{save,restore}_fp_context with
compat ABIs, move the FP usage checks into said functions. This will
both enable that code to be shared, and allow for extensions of it in
further patches to also be shared.
Signed-off-by: Paul Burton <[email protected]>
Cc: [email protected]
Cc: Guenter Roeck <[email protected]>
Cc: Matthew Fortune <[email protected]>
Cc: Michael Ellerman <[email protected]>
Cc: [email protected]
Cc: Richard Weinberger <[email protected]>
Cc: Andy Lutomirski <[email protected]>
Cc: Maciej W. Rozycki <[email protected]>
Patchwork: https://patchwork.linux-mips.org/patch/10790/
Signed-off-by: Ralf Baechle <[email protected]>
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When saving FP state to struct sigcontext, make use of the offsets
provided by struct mips_abi to obtain appropriate addresses for the
sc_fpregs & sc_fpc_csr fields of the sigcontext. This is done only for
the native struct sigcontext in this patch (ie. for O32 in CONFIG_32BIT
kernels or for N64 in CONFIG_64BIT kernels) but is done in preparation
for sharing this code with compat ABIs in further patches.
Signed-off-by: Paul Burton <[email protected]>
Cc: [email protected]
Cc: Guenter Roeck <[email protected]>
Cc: Matthew Fortune <[email protected]>
Cc: Leonid Yegoshin <[email protected]>
Cc: [email protected]
Cc: Richard Weinberger <[email protected]>
Cc: James Hogan <[email protected]>
Cc: Andy Lutomirski <[email protected]>
Cc: Markos Chandras <[email protected]>
Cc: Manuel Lauss <[email protected]>
Cc: Maciej W. Rozycki <[email protected]>
Patchwork: https://patchwork.linux-mips.org/patch/10789/
Signed-off-by: Ralf Baechle <[email protected]>
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Add fields to struct mips_abi, which holds information regarding the
kernel-userland ABI regarding signals, to specify the offsets to the FP
related fields within the appropriate variant of struct sigcontext.
Signed-off-by: Paul Burton <[email protected]>
Cc: [email protected]
Cc: Guenter Roeck <[email protected]>
Cc: Matthew Fortune <[email protected]>
Cc: Michael Ellerman <[email protected]>
Cc: [email protected]
Cc: Richard Weinberger <[email protected]>
Cc: James Hogan <[email protected]>
Cc: Andy Lutomirski <[email protected]>
Cc: Maciej W. Rozycki <[email protected]>
Patchwork: https://patchwork.linux-mips.org/patch/10788/
Signed-off-by: Ralf Baechle <[email protected]>
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