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Probing all the available clocks from the PM firmware takes quite a lot
of time, increasing boot time. Instead, implement functionality that
parses only the used clocks from DT, and registers these to clock core.
This way, the boot time is greatly improved.
Additionally, provide a Kconfig option for parsing all the clocks from
firmware, if someone requires this. It is mostly useful as a debugging
functionality if we want to inspect the whole clock tree.
Acked-by: Santosh Shilimkar <[email protected]>
Signed-off-by: Tero Kristo <[email protected]>
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This makes it both easier to see what the probe does, and also makes it
possible to add alternative implementations for the clock data source.
Acked-by: Santosh Shilimkar <[email protected]>
Signed-off-by: Tero Kristo <[email protected]>
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There is no need to store the full node name to the individual clocks,
as this will just consome memory and make the clock debug entries
unnecessary long. Just shorten this to "clk" for now.
Acked-by: Santosh Shilimkar <[email protected]>
Signed-off-by: Tero Kristo <[email protected]>
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Switch the entire clk-imx6sll driver to clk_hw based API.
This allows us to move closer to a clear split between
consumer and provider clk APIs.
Signed-off-by: Abel Vesa <[email protected]>
Reviewed-by: Stephen Boyd <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>
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Switch the entire clk-imx7d driver to clk_hw based API. This allows us
to move closer to a clear split between consumer and provider clk APIs.
Signed-off-by: Abel Vesa <[email protected]>
Reviewed-by: Stephen Boyd <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>
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Switch the entire clk-imx6ul driver to clk_hw based API. This allows us
to move closer to a clear split between consumer and provider clk APIs.
Signed-off-by: Abel Vesa <[email protected]>
Reviewed-by: Stephen Boyd <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>
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Switch the entire clk-imx6sx driver to clk_hw based API. This allows us
to move closer to a clear split between consumer and provider clk APIs.
Signed-off-by: Abel Vesa <[email protected]>
Reviewed-by: Stephen Boyd <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>
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Switch the entire clk-imx6q driver to clk_hw based API.
Add imx6q_obtain_fixed_clk_hw helper to clean up the registration
of the clocks that are either found in device tree or are assigned
a fixed zero rate. This switch allows us to move closer to a clear
split between consumer and provider clk APIs.
Signed-off-by: Abel Vesa <[email protected]>
Reviewed-by: Stephen Boyd <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>
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Switch the entire clk-imx6sl driver to clk_hw based API.
This allows us to move closer to a clear split between
consumer and provider clk APIs.
Signed-off-by: Abel Vesa <[email protected]>
Reviewed-by: Stephen Boyd <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>
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Switch all the wrappers to clk_hw based API and rename them to indicate
that. Add macros for clk based legacy users. This allows us to move
closer to a clear split between consumer and provider clk APIs.
Signed-off-by: Abel Vesa <[email protected]>
Reviewed-by: Stephen Boyd <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>
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Switch the imx_clk_fixup_mux function to clk_hw based API, rename
accordingly and add a macro for clk based legacy. a macro for clk
based legacy. This allows us to move closer to a clear split between
consumer and provider clk APIs.
Signed-off-by: Abel Vesa <[email protected]>
Reviewed-by: Stephen Boyd <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>
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Switch the imx_clk_fixup_divider function to clk_hw based API, rename
accordingly and add a macro for clk based legacy. This allows us to
move closer to a clear split between consumer and provider clk APIs.
Signed-off-by: Abel Vesa <[email protected]>
Reviewed-by: Stephen Boyd <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>
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Switch the imx_clk_gate_exclusive function to clk_hw based API, rename
accordingly and add a macro for clk based legacy. This allows us to move
closer to a clear split between consumer and provider clk APIs.
Signed-off-by: Abel Vesa <[email protected]>
Reviewed-by: Stephen Boyd <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>
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Switch the imx_clk_pfd function to clk_hw based API, rename accordingly
and add a macro for clk based legacy. This allows us to move closer to
a clear split between consumer and provider clk APIs.
Signed-off-by: Abel Vesa <[email protected]>
Reviewed-by: Stephen Boyd <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>
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Switch the imx_clk_hw_pllv3 function to clk_hw based API, rename
accordingly and add a macro for clk based legacy. This allows us
to move closer to a clear split between consumer and provider clk
APIs.
Signed-off-by: Abel Vesa <[email protected]>
Reviewed-by: Stephen Boyd <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>
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Switch the clk_register_gate2 function to clk_hw based API, rename
accordingly and add a macro for clk based legacy. This allows us to
move closer to a clear split between consumer and provider clk APIs.
Signed-off-by: Abel Vesa <[email protected]>
Reviewed-by: Stephen Boyd <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>
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Switch the clk_cpu clock registering function to clk_hw based API and add
a macro for clk based legacy. This allows us to move closer to a clear
split between consumer and provider clk APIs.
Signed-off-by: Abel Vesa <[email protected]>
Reviewed-by: Stephen Boyd <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>
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Switch all the clk_busy clock registering functions to clk_hw based API.
Keep around some clk based wrappers to be used by older imx platforms.
This allows us to move closer to a clear split of consumer and provider
clk APIs.
Signed-off-by: Abel Vesa <[email protected]>
Reviewed-by: Stephen Boyd <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>
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The clock is registered later than these two re-parentings.
Signed-off-by: Abel Vesa <[email protected]>
Reviewed-by: Stephen Boyd <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>
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The clock IMX6SX_CLK_AXI is not registered at all.
Signed-off-by: Abel Vesa <[email protected]>
Reviewed-by: Stephen Boyd <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>
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In order to move to clk_hw based API, imx_obtain_fixed_clock_hw
is added. The end goal here is to have all the clk providers use
the clk_hw based API.
Signed-off-by: Abel Vesa <[email protected]>
Reviewed-by: Stephen Boyd <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>
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There is no audio_pll2_clk registered, it should be audio_pll2_out.
Cc: <[email protected]>
Fixes: ba5625c3e272 ("clk: imx: Add clock driver support for imx8mm")
Signed-off-by: Peng Fan <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>
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The GPU for msm8998 has its own clock controller. Document it.
Signed-off-by: Jeffrey Hugo <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
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Remove MT8183 sspm clock
Signed-off-by: Erin Lo <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
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Add audsys clock driver for MediaTek MT8516 SoC.
Signed-off-by: Fabien Parent <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
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Add AUDSYS device tree bindings documentation for MediaTek MT8516 SoC.
Signed-off-by: Fabien Parent <[email protected]>
Reviewed-by: Rob Herring <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
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ARCH_BRCMSTB needs to use the BCM2835 clock driver for chips like
BCM7211 which adopted that clock controller, make that possible and the
driver default to be enabled for ARCH_BRCMSTB.
Signed-off-by: Florian Fainelli <[email protected]>
Reviewed-by: Eric Anholt <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
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Make the BCM2835 clock driver selectable by other
architectures/platforms. ARCH_BRCMSTB will be selecting that driver in
the next commit since new chips like 7211 use the same CPRMAN clock
controller that this driver supports.
Signed-off-by: Florian Fainelli <[email protected]>
Reviewed-by: Eric Anholt <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
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Commit 9fba738a53dda2 ("clk: add duty cycle support") added support for
getting and setting the duty cycle of a clock. This implements the
get_duty_cycle callback for PWM based clocks so the duty cycle is shown
in the debugfs output (/sys/kernel/debug/clk/clk_summary).
Signed-off-by: Martin Blumenstingl <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
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This patch provides support for clocks needed for Dynamic Memory Controller
in Exynos5422 SoC. It adds CDREX base register addresses, new DIV, MUX and
GATE entries.
Acked-by: Chanwoo Choi <[email protected]>
Acked-by: Krzysztof Kozlowski <[email protected]>
Signed-off-by: Lukasz Luba <[email protected]>
Signed-off-by: Sylwester Nawrocki <[email protected]>
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Add new table rate for BPLL for Exynos5422 SoC supporting Dynamic Memory
Controller frequencies for driver's DRAM timings.
Acked-by: Chanwoo Choi <[email protected]>
Acked-by: Krzysztof Kozlowski <[email protected]>
Signed-off-by: Lukasz Luba <[email protected]>
Signed-off-by: Sylwester Nawrocki <[email protected]>
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Define new IDs for clocks used by Dynamic Memory Controller in
Exynos5422 SoC.
Acked-by: Rob Herring <[email protected]>
Acked-by: Chanwoo Choi <[email protected]>
Acked-by: Krzysztof Kozlowski <[email protected]>
Signed-off-by: Lukasz Luba <[email protected]>
Signed-off-by: Sylwester Nawrocki <[email protected]>
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The Allwinner SoCs have a clocks controller supported in Linux, with a
matching Device Tree binding.
Now that we have the DT validation in place, let's convert the device tree
bindings for that controller over to a YAML schemas.
Signed-off-by: Maxime Ripard <[email protected]>
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The current code defines W1 clock gate to be at 0x1cc, overlaying it
with the IR gate.
Clock gate for r-apb1-w1 is at 0x1ec. This fixes issues with IR receiver
causing interrupt floods on H6 (because interrupt flags can't be cleared,
due to IR module's bus being disabled).
Fixes: b7c7b05065aa77ae ("clk: sunxi-ng: add support for H6 PRCM CCU")
Signed-off-by: Ondrej Jirman <[email protected]>
Acked-by: Clément Péron <[email protected]>
Signed-off-by: Maxime Ripard <[email protected]>
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There are several clocks on the r9a06g032 which are currently not
enabled in their drivers that can be delegated to clock domain system
for power management. Therefore add support for clock domain
functionality to the r9a06g032 clock driver.
Signed-off-by: Gareth Williams <[email protected]>
Signed-off-by: Geert Uytterhoeven <[email protected]>
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The driver is gaining power domain support, so add the new property
to the DT binding and update the examples.
Signed-off-by: Gareth Williams <[email protected]>
Signed-off-by: Geert Uytterhoeven <[email protected]>
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pm_clk_create() and pm_clk_add_clk() can fail only when running out of
memory. Hence there is no need to print error messages on failure, as
the memory allocation core already takes care of that.
Signed-off-by: Geert Uytterhoeven <[email protected]>
Reviewed-by: Simon Horman <[email protected]>
Reviewed-by: Niklas Söderlund <[email protected]>
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pm_clk_create() and pm_clk_add_clk() can fail only when running out of
memory. Hence there is no need to print error messages on failure, as
the memory allocation core already takes care of that.
Signed-off-by: Geert Uytterhoeven <[email protected]>
Reviewed-by: Simon Horman <[email protected]>
Reviewed-by: Niklas Söderlund <[email protected]>
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Since commit 6a0ae73d95956f7e ("PM / Domain: Add support to parse
domain's OPP table"), of_genpd_add_provider_simple() fills in
the dev.of_node field in the generic_pm_domain structure.
Hence cpg_mssr_is_pm_clk() can use that instead of its own copy in the
driver-private cpg_mssr_clk_domain structure.
Signed-off-by: Geert Uytterhoeven <[email protected]>
Reviewed-by: Simon Horman <[email protected]>
Reviewed-by: Niklas Söderlund <[email protected]>
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Use of_clk_get_parent_count() instead of open coding.
Reviewed-by: Andrzej Hajda <[email protected]>
Acked-by: Chanwoo Choi <[email protected]>
Signed-off-by: Kefeng Wang <[email protected]>
Signed-off-by: Sylwester Nawrocki <[email protected]>
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In sunxi_divs_clk_setup(), 'derived_name' is allocated by kstrndup().
It returns NULL when fails. 'derived_name' should be checked.
Signed-off-by: Gen Zhang <[email protected]>
Signed-off-by: Maxime Ripard <[email protected]>
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The MMDC_P1_IPG clock need to be on always on to make sure
the MMDC register can be accessed successfully.
Signed-off-by: Jacky Bai <[email protected]>
Reviewed-by: Dong Aisheng <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>
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This clock is used for dram operations inside TF-A and must be kept
enabled for features such as suspend/resume dram retention and busfreq
to work.
This is required for imx8mm suspend to work with NXP branch of TF-A.
There is an equivalent clk on imx8mq and it's always been marked as
critical in upstream.
Signed-off-by: Leonard Crestez <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>
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Since i.MX7ULP B0 chip, nic1_bus_clk's parent is changed to
from nic0_clk directly, update it accordingly.
Signed-off-by: Anson Huang <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>
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Use imx_mmdc_mask_handshake() API instead of programming CCM
register directly in each platform to mask unused MMDC channel's
handshake.
Signed-off-by: Anson Huang <[email protected]>
Reviewed-by: Dong Aisheng <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>
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All i.MX6 SoCs need to mask unused MMDC channel's handshake
for low power modes, this patch provides common API for masking
the MMDC channel passed from caller.
Signed-off-by: Anson Huang <[email protected]>
Reviewed-by: Dong Aisheng <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>
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This is documented in the reference manuals as GIC_CLK_ROOT.
In some out-of-tree DVFS scenarios the gic clock can end up as the only
user of sys_pll2 so if we don't define the gic clk explicitly it might
be turned off.
This applies to both 8mq and 8mm: same clk register but diffferent
parents.
Signed-off-by: Leonard Crestez <[email protected]>
Reviewed-by: Abel Vesa <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>
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This should be defined in the clock tree so that parents are not
shutdown by accident
Signed-off-by: Leonard Crestez <[email protected]>
Reviewed-by: Abel Vesa <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>
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i.MX8MM has clock gate for SNVS module, add it into clock tree
for SNVS RTC driver to manage.
Signed-off-by: Anson Huang <[email protected]>
Reviewed-by: Leonard Crestez <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>
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Add macro for the SNVS clock of the i.MX8MM.
Signed-off-by: Anson Huang <[email protected]>
Reviewed-by: Leonard Crestez <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>
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