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authorAbel Vesa <[email protected]>2019-05-29 12:26:40 +0000
committerShawn Guo <[email protected]>2019-06-07 08:36:15 +0800
commitf5697226f90ecbb05640ecef8d0daaf2cc04c127 (patch)
tree0f7755a1b05e20ec64f748feee55f9d7892bdfe2
parentfa7574740cdfef5b4d65a48bab04cef5637827f8 (diff)
clk: imx6q: Do not reparent uninitialized IMX6QDL_CLK_PERIPH2 clock
The clock is registered later than these two re-parentings. Signed-off-by: Abel Vesa <[email protected]> Reviewed-by: Stephen Boyd <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
-rw-r--r--drivers/clk/imx/clk-imx6q.c8
1 files changed, 0 insertions, 8 deletions
diff --git a/drivers/clk/imx/clk-imx6q.c b/drivers/clk/imx/clk-imx6q.c
index 077276b09338..d90d54bf78fe 100644
--- a/drivers/clk/imx/clk-imx6q.c
+++ b/drivers/clk/imx/clk-imx6q.c
@@ -280,12 +280,6 @@ static void mmdc_ch1_disable(void __iomem *ccm_base)
clk_set_parent(clk[IMX6QDL_CLK_PERIPH2_CLK2_SEL],
clk[IMX6QDL_CLK_PLL3_USB_OTG]);
- /*
- * Handshake with mmdc_ch1 module must be masked when changing
- * periph2_clk_sel.
- */
- clk_set_parent(clk[IMX6QDL_CLK_PERIPH2], clk[IMX6QDL_CLK_PERIPH2_CLK2]);
-
/* Disable pll3_sw_clk by selecting the bypass clock source */
reg = readl_relaxed(ccm_base + CCM_CCSR);
reg |= CCSR_PLL3_SW_CLK_SEL;
@@ -300,8 +294,6 @@ static void mmdc_ch1_reenable(void __iomem *ccm_base)
reg = readl_relaxed(ccm_base + CCM_CCSR);
reg &= ~CCSR_PLL3_SW_CLK_SEL;
writel_relaxed(reg, ccm_base + CCM_CCSR);
-
- clk_set_parent(clk[IMX6QDL_CLK_PERIPH2], clk[IMX6QDL_CLK_PERIPH2_PRE]);
}
/*