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2022-09-30clk: baikal-t1: Add shared xGMAC ref/ptp clocks internal parentSerge Semin3-3/+12
Baikal-T1 CCU reference manual says that both xGMAC reference and xGMAC PTP clocks are generated by two different wrappers with the same constant divider thus each producing a 156.25 MHz signal. But for some reason both of these clock sources are gated by a single switch-flag in the CCU registers space - CCU_SYS_XGMAC_BASE.BIT(0). In order to make the clocks handled independently we need to define a shared parental gate so the base clock signal would be switched off only if both of the child-clocks are disabled. Note the ID is intentionally set to -2 since we are going to add a one more internal clock identifier in the next commit. Fixes: 353afa3a8d2e ("clk: Add Baikal-T1 CCU Dividers driver") Signed-off-by: Serge Semin <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
2022-09-30clk: baikal-t1: Fix invalid xGMAC PTP clock dividerSerge Semin1-1/+1
Most likely due to copy-paste mistake the divider has been set to 10 while according to the SoC reference manual it's supposed to be 8 thus having PTP clock frequency of 156.25 MHz. Fixes: 353afa3a8d2e ("clk: Add Baikal-T1 CCU Dividers driver") Signed-off-by: Serge Semin <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
2022-09-30clk: vc5: Fix 5P49V6901 outputs disabling when enabling FODSerge Semin1-1/+1
We have discovered random glitches during the system boot up procedure. The problem investigation led us to the weird outcomes: when none of the Renesas 5P49V6901 ports are explicitly enabled by the kernel driver, the glitches disappeared. It was a mystery since the SoC external clock domains were fed with different 5P49V6901 outputs. The driver code didn't seem like bogus either. We almost despaired to find out a root cause when the solution has been found for a more modern revision of the chip. It turned out the 5P49V6901 clock generator stopped its output for a short period of time during the VC5_OUT_DIV_CONTROL register writing. The same problem was found for the 5P49V6965 revision of the chip and was successfully fixed in commit fc336ae622df ("clk: vc5: fix output disabling when enabling a FOD") by enabling the "bypass_sync" flag hidden inside "Unused Factory Reserved Register". Even though the 5P49V6901 registers description and programming guide doesn't provide any intel regarding that flag, setting it up anyway in the officially unused register completely eliminated the denoted glitches. Thus let's activate the functionality submitted in commit fc336ae622df ("clk: vc5: fix output disabling when enabling a FOD") for the Renesas 5P49V6901 chip too in order to remove the ports implicit inter-dependency. Fixes: dbf6b16f5683 ("clk: vc5: Add support for IDT VersaClock 5P49V6901") Signed-off-by: Serge Semin <[email protected]> Reviewed-by: Luca Ceresoli <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
2022-09-30Merge tag 'amd-drm-fixes-6.0-2022-09-30-1' of ↵Daniel Vetter7-149/+281
https://gitlab.freedesktop.org/agd5f/linux into drm-fixes amd-drm-fixes-6.0-2022-09-30-1: amdgpu: - VCN 4.x fixes - RLC fixes for GC 11.x Signed-off-by: Daniel Vetter <[email protected]> From: Alex Deucher <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2022-09-30Merge branch 'tools: bpftool: Remove unused struct'Andrii Nakryiko2-12/+0
Yuan Can says: ==================== This series contains two cleanup patches, remove unused struct. ==================== Signed-off-by: Andrii Nakryiko <[email protected]>
2022-09-30bpftool: Remove unused struct event_ring_infoYuan Can1-7/+0
After commit 9b190f185d2f ("tools/bpftool: switch map event_pipe to libbpf's perf_buffer"), struct event_ring_info is not used any more and can be removed as well. Signed-off-by: Yuan Can <[email protected]> Signed-off-by: Andrii Nakryiko <[email protected]> Link: https://lore.kernel.org/bpf/[email protected]
2022-09-30bpftool: Remove unused struct btf_attach_pointYuan Can1-5/+0
After commit 2828d0d75b73 ("bpftool: Switch to libbpf's hashmap for programs/maps in BTF listing"), struct btf_attach_point is not used anymore and can be removed as well. Signed-off-by: Yuan Can <[email protected]> Signed-off-by: Andrii Nakryiko <[email protected]> Link: https://lore.kernel.org/bpf/[email protected]
2022-09-30drm/amdgpu/gfx11: switch to amdgpu_gfx_rlc_init_microcodeHawking Zhang1-152/+4
switch to common helper to initialize rlc firmware for gfx11 Signed-off-by: Hawking Zhang <[email protected]> Acked-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-09-30drm/amdgpu: add helper to init rlc firmwareHawking Zhang2-1/+38
To initialzie rlc firmware according to rlc firmware header version v2: squash in backwards compat fix Signed-off-by: Hawking Zhang <[email protected]> Acked-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-09-30drm/amdgpu: add helper to init rlc fw in header v2_4Hawking Zhang1-0/+60
To initialize rlc firmware in header v2_4 Signed-off-by: Hawking Zhang <[email protected]> Acked-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-09-30drm/amdgpu: add helper to init rlc fw in header v2_3Hawking Zhang1-0/+35
To initialize rlc firmware in header v2_3 Signed-off-by: Hawking Zhang <[email protected]> Acked-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-09-30drm/amdgpu: add helper to init rlc fw in header v2_2Hawking Zhang1-0/+30
To initialize rlc firmware in header v2_2 Signed-off-by: Hawking Zhang <[email protected]> Acked-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-09-30drm/amdgpu: add helper to init rlc fw in header v2_1Hawking Zhang1-0/+40
To initialize rlc firmware in header v2_1 Signed-off-by: Hawking Zhang <[email protected]> Acked-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-09-30drm/amdgpu: add helper to init rlc fw in header v2_0Hawking Zhang1-0/+64
To initialize rlc firmware in header v2_0 Signed-off-by: Hawking Zhang <[email protected]> Acked-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-09-30drm/amdgpu: save rlcv/rlcp ucode version in amdgpu_gfxHawking Zhang3-0/+13
cache rlcv/rlcvp ucode version info in amdgpu_gfx structure Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: Likun Gao <[email protected]> Reviewed-by: Feifei Xu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-09-30clk: davinci: cfgchip: Use dev_err_probe() helperYang Yingliang1-2/+1
dev_err() can be replace with dev_err_probe() which will check if error code is -EPROBE_DEFER. Signed-off-by: Yang Yingliang <[email protected]> Link: https://lore.kernel.org/r/[email protected] Reviewed-by: David Lechner <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2022-09-30clk: davinci: pll: fix spelling typo in commentJiangshan Yi1-1/+1
Fix spelling typo in comment. Reported-by: k2ci <[email protected]> Signed-off-by: Jiangshan Yi <[email protected]> Link: https://lore.kernel.org/r/[email protected] Reviewed-by: David Lechner <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2022-09-30MAINTAINERS: add header file to TI DAVINCI SERIES CLOCK DRIVERLukas Bulwahn1-0/+1
While creating a patch submission on the davinci clock drivers, I noticed that the header file include/linux/clk/davinci.h belongs to the section TI DAVINCI SERIES CLOCK DRIVER. Add a file entry for this header file in TI DAVINCI SERIES CLOCK DRIVER. Signed-off-by: Lukas Bulwahn <[email protected]> Link: https://lore.kernel.org/r/[email protected] Reviewed-by: David Lechner <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2022-09-30bpf, docs: Add TOC and fix formatting.Dave Thaler1-132/+136
Add TOC and fix formatting. Signed-off-by: Dave Thaler <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Alexei Starovoitov <[email protected]>
2022-09-30bpf, docs: Add Clang note about BPF_ALUDave Thaler1-0/+6
Add Clang note about BPF_ALU. Signed-off-by: Dave Thaler <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Alexei Starovoitov <[email protected]>
2022-09-30bpf, docs: Move Clang notes to a separate fileDave Thaler2-6/+24
Move Clang notes to a separate file. Signed-off-by: Dave Thaler <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Alexei Starovoitov <[email protected]>
2022-09-30bpf, docs: Linux byteswap noteDave Thaler2-4/+5
Add Linux byteswap note. Signed-off-by: Dave Thaler <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Alexei Starovoitov <[email protected]>
2022-09-30bpf, docs: Move legacy packet instructions to a separate fileDave Thaler2-35/+68
Move legacy packet instructions to a separate file. Signed-off-by: Dave Thaler <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Alexei Starovoitov <[email protected]>
2022-09-30clk: mmp: pxa168: control shared SDH bits with separate clockDoug Brown1-4/+7
The PXA168 has a peculiar setup with the AXI clock enable control for the SDHC controllers. The bits in the SDH0 register control the AXI clock enable for both SDH0 and SDH1. Likewise, the bits in the SDH2 register control both SDH2 and SDH3. This is modeled with two new parentless clocks that control the shared bits. Previously, SDH0 had to be enabled in order for SDH1 to be used, and when SDH1 was enabled, unused bits in the SDH1 register were being controlled. This fixes those issues. A future commit will add support for these new shared clocks to be enabled by the PXA168 SDHC driver. Signed-off-by: Doug Brown <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
2022-09-30dt-bindings: marvell,pxa168: add clock ids for SDH AXI clocksDoug Brown1-0/+2
These are clocks shared by SDH0/1 and SDH2/3, respectively. Signed-off-by: Doug Brown <[email protected]> Link: https://lore.kernel.org/r/[email protected] Acked-by: Rob Herring <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2022-09-30clk: mmp: pxa168: add clocks for SDH2 and SDH3Doug Brown1-0/+6
The PXA168 has four SDHC peripherals. This commit adds the last two. Signed-off-by: Doug Brown <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
2022-09-30dt-bindings: marvell,pxa168: add clock id for SDH3Doug Brown1-0/+1
There are four SDHC peripherals on the PXA168, but only three of them were present in the DT bindings. This commit adds the fourth. Signed-off-by: Doug Brown <[email protected]> Link: https://lore.kernel.org/r/[email protected] Acked-by: Rob Herring <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2022-09-30clk: mmp: pxa168: fix GPIO clock enable bitsDoug Brown1-1/+1
According to the datasheet, only bit 0 of APBC_GPIO should be controlled for the clock enable. Bit 1 is marked as reserved (always write 0). Signed-off-by: Doug Brown <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
2022-09-30clk: mmp: pxa168: add muxes for more peripheralsDoug Brown1-10/+32
The TWSI, KPC, PWM, and DFC peripherals didn't have their muxes modeled in the code, but the PXA168 datasheet shows that they are indeed muxed: - TWSI can be 31.2 MHz or 62.4 MHz - KPC can be 32 kHz, 16 kHz, or 26 MHz - PWM can be 13 MHz or 32 kHz - DFC can be 156 MHz or 78 MHz Signed-off-by: Doug Brown <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
2022-09-30clk: mmp: pxa168: fix incorrect parent clocksDoug Brown1-6/+6
The UART, SDHC, LCD, and CCIC peripherals' muxed parent clocks didn't match the information provided by the PXA168 datasheet: - The UART clocks can be 58.5 MHz or the UART PLL. Previously, the first mux option was being calculated as 117 MHz, confirmed on hardware to be incorrect. - The SDHC clocks can be 48 MHz, 52 MHz, or 78 MHz. Previously, 48 MHz and 52 MHz were swapped. 78 MHz wasn't listed as an option. - The LCD clock can be 624 MHz or 312 Mhz. Previously, it was being calculated as 312 MHz or 52 MHz. - The CCIC clock can be 156 MHz or 78 MHz. Previously, it was being calculated as 312 MHz or 52 MHz. Signed-off-by: Doug Brown <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
2022-09-30clk: mmp: pxa168: fix const-correctnessDoug Brown1-7/+7
While working on this series of patches, checkpatch recommended that an extra const should be added to the mux parent arrays. Signed-off-by: Doug Brown <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
2022-09-30clk: mmp: pxa168: add new clocks for peripheralsDoug Brown1-0/+3
This commit adds three new clocks that previously didn't exist, but are needed in order to match the clock parenting as described in the PXA168 datasheet. Signed-off-by: Doug Brown <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
2022-09-30dt-bindings: marvell,pxa168: add clock ids for additional dividersDoug Brown1-0/+3
This adds a few new clocks divided from PLL1 and CLK32 that are potentially used by a few peripherals with muxed clocks. Signed-off-by: Doug Brown <[email protected]> Link: https://lore.kernel.org/r/[email protected] Acked-by: Rob Herring <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2022-09-30clk: mmp: pxa168: fix incorrect dividersDoug Brown1-2/+2
These two clocks had multipliers and dividers that didn't match their names. A subsequent commit goes through all of the existing peripherals and ensure the correct clocks are being used everywhere. Signed-off-by: Doug Brown <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
2022-09-30clk: mmp: pxa168: add additional register definesDoug Brown1-7/+24
In preparation for adding additional peripherals over time, this commit adds a bunch of extra APBC_* defines based on information from the datasheet. It also reorganizes the list of defines to be ordered sequentially by address (grouped by type). Signed-off-by: Doug Brown <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
2022-09-30Documentation: Kunit: Use full path to .kunitconfigKhalid Masum1-1/+1
The numbered list contains full path to every files that need to be modified or created in order to implement misc-example kunit test. Except for .kunitconfig. Which might make a newcommer confused about where the file exists. Since there are multiple .kunitconfig files. Fix this by using the full path to .kunitconfig. Signed-off-by: Khalid Masum <[email protected]> Reviewed-by: David Gow <[email protected]> Signed-off-by: Shuah Khan <[email protected]>
2022-09-30kunit: tool: rename all_test_uml.config, use it for --alltestsDaniel Latypov5-90/+33
Context: 1. all_tests_uml.config used to be UML specific back when users to manually specify CONFIG_VIRTIO_UML=y to enable CONFIG_PCI=y. 2. --alltests used allyesconfig along with a curated list of options to disable. It's only ever worked for brief periods of time and has perennially been broken due to compile issues. Now all_tests_uml.config should work across ~all architectures. Let's instead use this to implement --alltests. Note: if anyone was using all_tests_uml.config, this change breaks them. I think that's unlikely since it was added in 5.19 and was a lot to type: --kunitconfig=tools/testing/kunit/configs/all_tests_uml.config. We could make it a symlink to the new name, but I don't think the caution is warranted here. Signed-off-by: Daniel Latypov <[email protected]> Reviewed-by: David Gow <[email protected]> Signed-off-by: Shuah Khan <[email protected]>
2022-09-30kunit: tool: remove UML specific options from all_tests_uml.configDaniel Latypov1-2/+0
Commit 6fc3a8636a7b ("kunit: tool: Enable virtio/PCI by default on UML") made it so we enable these options by default for UML. Specifying them here is now redundant. Signed-off-by: Daniel Latypov <[email protected]> Reviewed-by: David Gow <[email protected]> Signed-off-by: Shuah Khan <[email protected]>
2022-09-30clk: sprd: Add clocks support for UMS512Cixi Geng3-0/+2209
Add the list of clocks for the Unisoc UMS512, along with clock initialization. Signed-off-by: Cixi Geng <[email protected]> Link: https://lore.kernel.org/r/[email protected] Reviewed-by: Baolin Wang <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2022-09-30lib: stackinit: update reference to kunit-toolTales Aparecida1-1/+1
Replace URL with an updated path to the full Documentation page Signed-off-by: Tales Aparecida <[email protected]> Reviewed-by: David Gow <[email protected]> Signed-off-by: Shuah Khan <[email protected]>
2022-09-30lib: overflow: update reference to kunit-toolTales Aparecida1-1/+1
Replace URL with an updated path to the full Documentation page Signed-off-by: Tales Aparecida <[email protected]> Reviewed-by: Kees Cook <[email protected]> Reviewed-by: David Gow <[email protected]> Signed-off-by: Shuah Khan <[email protected]>
2022-09-30Documentation: KUnit: update links in the index pageTales Aparecida1-6/+7
Replace out-of-date external links with references to the kernel documentation, replacing TAP webpage for the more appropriate KTAP documentation and the UML webpage by its documentation. Signed-off-by: Tales Aparecida <[email protected]> Reviewed-by: David Gow <[email protected]> Signed-off-by: Shuah Khan <[email protected]>
2022-09-30Documentation: KUnit: add intro to the getting-started pageTales Aparecida1-0/+4
Describe the objective of the Getting Started page, which should be a brief and beginner-friendly walkthrough for running and writing tests, showing the reader where to find detailed instructions in other pages. Signed-off-by: Tales Aparecida <[email protected]> Reviewed-by: Maíra Canal <[email protected]> Reviewed-by:Sadiya Kazi<[email protected]> Reviewed-by: David Gow <[email protected]> Signed-off-by: Shuah Khan <[email protected]>
2022-09-30Documentation: KUnit: Reword start guide for selecting testsTales Aparecida1-27/+63
Reword "Creating a ``.kunitconfig``" into "Selecting which tests to run" covering the current alternatives for editing configs and glob-filtering Signed-off-by: Tales Aparecida <[email protected]> Reviewed-by: Maíra Canal <[email protected]> Reviewed-by:Sadiya Kazi <[email protected]> Reviewed-by: David Gow <[email protected]> Signed-off-by: Shuah Khan <[email protected]>
2022-09-30Documentation: KUnit: add note about mrproper in start.rstTales Aparecida1-0/+16
The "Getting Started" guide should be beginner-friendly, therefore add a note about the requirement of a clean source tree when running kunit_tool for the first time, and its related error. Signed-off-by: Tales Aparecida <[email protected]> Reviewed-by: David Gow <[email protected]> Signed-off-by: Shuah Khan <[email protected]>
2022-09-30Documentation: KUnit: avoid repeating "kunit.py run" in start.rstTales Aparecida2-24/+16
Combine two sections mentioning "kunit.py run" to streamline the getting-started guide. Update "kunit.py run" expected output in the guide and run_wrapper. Signed-off-by: Tales Aparecida <[email protected]> Reviewed-by: Maíra Canal <[email protected]> Reviewed-by: Sadiya Kazi<[email protected]> Reviewed-by: David Gow <[email protected]> Signed-off-by: Shuah Khan <[email protected]>
2022-09-30Documentation: KUnit: remove duplicated docs for kunit_toolTales Aparecida4-253/+16
Delete "kunit-tool.rst" to remove repeated info from KUnit docs. "What is kunit_tool?" was integrated into index.rst, the remaining sections were moved into run_wrapper.rst and renamed as follows: "What is a .kunitconfig?" -> "Creating a ``.kunitconfig`` file" "Getting Started with kunit_tool" -> "Running tests with kunit_tool" "Configuring, Building, and Running Tests" -> "Configuring, building, and running tests" "Running Tests on QEMU" -> "Running tests on QEMU" "Parsing Test Results" -> "Parsing test results" "Filtering Tests" -> "Filtering tests" "Other Useful Options" -> "Running command-line arguments" Signed-off-by: Tales Aparecida <[email protected]> Reviewed-by: Sadiya Kazi <[email protected]> Reviewed-by: David Gow <[email protected]> Signed-off-by: Shuah Khan <[email protected]>
2022-09-30Documentation: Kunit: Add ref for other kinds of testsTales Aparecida2-0/+4
Add an organic link to the "other kinds of tests" in the index page Signed-off-by: Tales Aparecida <[email protected]> Reviewed-by: David Gow <[email protected]> Signed-off-by: Shuah Khan <[email protected]>
2022-09-30Documentation: KUnit: Fix non-uml anchorTales Aparecida3-5/+7
The section was rewritten but its anchor got left behind. Fix the anchor and add some references to running on QEMU. Signed-off-by: Tales Aparecida <[email protected]> Reviewed-by: David Gow <[email protected]> Signed-off-by: Shuah Khan <[email protected]>
2022-09-30Documentation: Kunit: Fix inconsistent titlesTales Aparecida1-2/+2
Use the same wording when citing and describing Kunit parts. Signed-off-by: Tales Aparecida <[email protected]> Reviewed-by: David Gow <[email protected]> Reviewed-by: Sadiya Kazi <[email protected]> Signed-off-by: Shuah Khan <[email protected]>
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