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2021-10-06dt-bindings: arm: bcm2835: Add Raspberry Pi Compute Module 4Stefan Wahren1-0/+1
Add the Raspberry Pi Compute Module 4 to DT schema. Signed-off-by: Stefan Wahren <[email protected]> Acked-by: Rob Herring <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Nicolas Saenz Julienne <[email protected]>
2021-10-06ARM: dts: bcm283x-rpi: Move Wifi/BT into separate dtsiStefan Wahren6-137/+74
A Wifi/BT chip is quite common for the Raspberry Pi boards. So move those definitions into a separate dtsi in order to avoid copy & paste. This change was inspired by a vendor tree patch from Phil Elwell. Signed-off-by: Stefan Wahren <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Nicolas Saenz Julienne <[email protected]>
2021-10-06dt-bindings: display: bcm2835: add optional property power-domainsStefan Wahren4-0/+12
The Raspberry Pi boards with BCM283x needs control of the power domains to get display components running. DT schema warns us that it's used, but not documented as a optional property: hdmi@7e902000: 'power-domains' does not match any of the regexes: ... Signed-off-by: Stefan Wahren <[email protected]> Acked-by: Rob Herring <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Nicolas Saenz Julienne <[email protected]>
2021-10-06ARM: dts: bcm2711-rpi-4-b: fix sd_io_1v8_reg regulator statesStefan Wahren1-2/+2
DT schema check complains at sd_io_1v8_reg about the following: [1800000, 1, 3300000, 0] is too long Additional items are not allowed (3300000, 0 were unexpected) So fix the states definition. Fixes: 7dbe8c62ceeb ("ARM: dts: Add minimal Raspberry Pi 4 support") Signed-off-by: Stefan Wahren <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Nicolas Saenz Julienne <[email protected]>
2021-10-06ARM: dts: bcm2711: fix MDIO #address- and #size-cellsStefan Wahren1-2/+2
The values of #address-cells and #size-cells are swapped. Fix this and avoid the following DT schema warnings for mdio@e14: #address-cells:0:0: 1 was expected #size-cells:0:0: 0 was expected Fixes: be8af7a9e3cc ("ARM: dts: bcm2711-rpi-4: Enable GENET support") Signed-off-by: Stefan Wahren <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Nicolas Saenz Julienne <[email protected]>
2021-10-06ARM: dts: bcm283x: Fix VEC address for BCM2711Mateusz Kwiatkowski3-8/+16
The VEC has a different address (0x7ec13000) on the BCM2711 (used in e.g. Raspberry Pi 4) compared to BCM283x (e.g. Pi 3 and earlier). This was erroneously not taken account for. Definition of the VEC in the devicetrees had to be moved from bcm283x.dtsi to bcm2711.dtsi and bcm2835-common.dtsi to allow for this differentiation. Fixes: 7894bdc6228f ("ARM: boot: dts: bcm2711: Add BCM2711 VEC compatible") Signed-off-by: Mateusz Kwiatkowski <[email protected]> Signed-off-by: Stefan Wahren <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Nicolas Saenz Julienne <[email protected]>
2021-10-06ARM: dts: dra7: add entry for bb2d moduleGowtham Tammana1-0/+19
BB2D is a Vivante GC 2D Accelerator. This adds the node to the dts file within a target module node. Crossbar index number is used for interrupt mapping. Signed-off-by: Gowtham Tammana <[email protected]> Signed-off-by: Jyri Sarha <[email protected]> Signed-off-by: Neil Armstrong <[email protected]> Signed-off-by: Tony Lindgren <[email protected]>
2021-10-06arm: dts: omap3-gta04: cleanup led node namesAndreas Kemnade1-5/+6
Change led node names to match schema. Signed-off-by: Andreas Kemnade <[email protected]> Signed-off-by: Tony Lindgren <[email protected]>
2021-10-06arm: dts: omap3-gta04a4: accelerometer irq fixAndreas Kemnade1-1/+1
Fix typo in pinctrl. It did only work because the bootloader seems to have initialized it. Fixes: ee327111953b ("ARM: dts: omap3-gta04: Define and use bma180 irq pin") Signed-off-by: Andreas Kemnade <[email protected]> Signed-off-by: Tony Lindgren <[email protected]>
2021-10-06arm: dts: omap3-gta04a5: fix missing sensor supplyAndreas Kemnade1-0/+2
Add mandatory supply properties. The supply is always on, so it is just a syntax issue, no functional change. Signed-off-by: Andreas Kemnade <[email protected]> Signed-off-by: Tony Lindgren <[email protected]>
2021-10-06arm: dts: omap3-gta04: fix missing sensor supplyAndreas Kemnade1-0/+2
Add mandatory supply properties. The supply is always on, so it is just a syntax issue, no functional change. Signed-off-by: Andreas Kemnade <[email protected]> Signed-off-by: Tony Lindgren <[email protected]>
2021-10-06arm: dts: omap3-gta04: cleanup LCD definitionAndreas Kemnade1-4/+4
Replace depreciated nodenames, fix label name to match scheme. Signed-off-by: Andreas Kemnade <[email protected]> Signed-off-by: Tony Lindgren <[email protected]>
2021-10-06ARM: dts: omap3: fix cpu thermal label nameAndreas Kemnade1-1/+1
Hyphens should be used in label names. make dtbs_check complains about that since it does not match the corresponding pattern Signed-off-by: Andreas Kemnade <[email protected]> Signed-off-by: Tony Lindgren <[email protected]>
2021-10-06ARM: dts: am335x-pocketbeagle: switch to pinconf-singleDrew Fustini1-0/+1
Switch the compatible for the am33xx_pinmux pin controller node from pinctrl-single to pinconf-single. The only change between these two compatibles is that PCS_HAS_PINCONF will be true. This then allows pinconf properties to be utilized. The purpose of this change is to allow the PocketBeagle to use: pinctrl-single,bias-pullup pinctrl-single,bias-pulldown This dts already defines these properites for gpio pins in the default pinctrl state but it has no effect unless PCS_HAS_PINCONF is set. The bias properties can then be modified on the corresponding gpio lines through the gpiod uapi. The mapping between the pins and gpio lines is defined by gpio-ranges under the gpio controller nodes in am33xx-l4.dtsi Signed-off-by: Drew Fustini <[email protected]> Signed-off-by: Tony Lindgren <[email protected]>
2021-10-05arm64: dts: ti: k3-j721e-sk: Add DDR carveout memory nodesSinthu Raja1-0/+144
Two carveout reserved memory nodes each have been added for each of the other remote processors devices within the MAIN domain on the TI J721E SK boards. These nodes are assigned to the respective rproc device nodes as well. The first region will be used as the DMA pool for the rproc devices, and the second region will furnish the static carveout regions for the firmware memory. An additional reserved memory node is also added to reserve a portion of the DDR memory to be used for performing inter-processor communication between all the remote processors running RTOS or baremetal firmwares. 8 MB of memory is reserved for this purpose, and this accounts for all the vrings and vring buffers between all the possible pairs of remote processors. The current carveout addresses and sizes are defined statically for each rproc device. The R5F processors do not have an MMU, and as such require the exact memory used by the firmwares to be set-aside. The C71x DSP processor does support a MMU called CMMU, but is not currently supported and as such requires the exact memory used by the firmware to be set-aside. The firmware images do not require any RSC_CARVEOUT entries in their resource tables to allocate the memory for firmware memory segments Signed-off-by: Sinthu Raja <[email protected]> Signed-off-by: Nishanth Menon <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2021-10-05arm64: dts: ti: k3-j721e-sk: Add IPC sub-mailbox nodesSinthu Raja1-0/+129
Add the sub-mailbox nodes that are used to communicate between MPU and various remote processors present in the J721E SoCs to the J721E EAIK board. These include the R5F remote processors in the dual-R5F cluster (MCU_R5FSS0) in the MCU domain and the two dual-R5F clusters (MAIN_R5FSS0 & MAIN_R5FSS1) in the MAIN domain; the two C66x DSP remote processors and the single C71x DSP remote processor in the MAIN domain. These sub-mailbox nodes utilize the System Mailbox clusters 0 through 4. All the remaining mailbox clusters are currently not used on A72 core, and are hence disabled. The sub-mailbox nodes added match the hard-coded mailbox configuration used within the TI RTOS IPC software packages. The R5F processor sub-systems are assumed to be running in Split mode, so a sub-mailbox node is used by each of the R5F cores. Only the sub-mailbox node for the first R5F core in each cluster is used in case of a Lockstep mode for that R5F cluster. Signed-off-by: Sinthu Raja <[email protected]> Signed-off-by: Nishanth Menon <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2021-10-05arm64: dts: ti: Add support for J721E SKSinthu Raja2-0/+730
J721E Starter Kit (SK)[1] is a low cost, small form factor board designed for TI’s J721E SoC. TI’s J721E SoC comprises of dual core A72, high performance vision accelerators, video codec accelerators, latest C71x and C66x DSP, high bandwidth real-time IPs for capture and display, GPU, dedicated safety island and security accelerators. The SoC is power optimized to provide best in class performance for industrial and automotive applications. J721E SK supports the following interfaces: * 4 GB LPDDR4 RAM * x1 Gigabit Ethernet interface * x1 USB 3.0 Type-C port * x3 USB 3.0 Type-A ports * x1 PCIe M.2 E Key * x1 PCIe M.2 M Key * 512 Mbit OSPI flash * x2 CSI2 Camera interface (RPi and TI Camera connector) * 40-pin Raspberry Pi GPIO header Add basic support for J721E-SK. [1] https://www.ti.com/tool/SK-TDA4VM Signed-off-by: Sinthu Raja <[email protected]> Signed-off-by: Nishanth Menon <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2021-10-05dt-bindings: arm: ti: Add compatible for J721E SKSinthu Raja1-0/+1
J721E Starter Kit (SK)[1] is a low cost, small form factor board designed for TI’s J721E SoC. Add j721e-sk into compatible enum. [1]https://www.ti.com/tool/SK-TDA4VM Signed-off-by: Sinthu Raja <[email protected]> Acked-by: Rob Herring <[email protected]> Signed-off-by: Nishanth Menon <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2021-10-05arm64: dts: ti: iot2050: Add support for product generation 2 boardsJan Kiszka4-0/+106
This adds the devices trees for IOT2050 Product Generation 2 (PG2) boards. We have Basic and an Advanced variants again, differing in number of cores, RAM size, availability of eMMC and further details. The major difference to PG1 is the used silicon revision (SR2.x on PG2). Signed-off-by: Jan Kiszka <[email protected]> Signed-off-by: Nishanth Menon <[email protected]> Link: https://lore.kernel.org/r/cc868da8264324bde2c87d0c01d4763e3678c706.1632657917.git.jan.kiszka@web.de
2021-10-05arm64: dts: ti: iot2050: Prepare for adding 2nd-generation boardsJan Kiszka6-125/+178
The current IOT2050 devices are Product Generation 1 (PG1), using SR1.0 AM65x silicon. Upcoming PG2 devices will use SR2.x SoCs and will therefore need separate device trees. Prepare for that by factoring out common bits that will be shared across both generations. At this chance, drop a link to the product homepage to in the top-level dts files. Also fix a typo in my email address in some headers. Signed-off-by: Jan Kiszka <[email protected]> Signed-off-by: Nishanth Menon <[email protected]> Link: https://lore.kernel.org/r/31fece05f9728a852c0632985c4fa537cced4ece.1632657917.git.jan.kiszka@web.de
2021-10-05dt-bindings: arm: ti: Add bindings for Siemens IOT2050 PG2 boardsJan Kiszka1-0/+2
Product Generation 2 (PG2) boards are based on SR2.x SoCs and will be released soon. Signed-off-by: Jan Kiszka <[email protected]> Acked-by: Rob Herring <[email protected]> Signed-off-by: Nishanth Menon <[email protected]> Link: https://lore.kernel.org/r/5d99e69ff1e2fb78f51f03c351eff1fe1f6c3a71.1632657917.git.jan.kiszka@web.de
2021-10-05arm64: dts: ti: iot2050: Add/enabled mailboxes and carve-outs for R5F coresJan Kiszka1-2/+24
Analogously to the am654-base-board, configure the mailboxes for the two R5F cores, add them and the already existing memory carve-outs to the related MCU nodes. Allows to load applications under Linux onto the cores, e.g. the RTI watchdog firmware. Signed-off-by: Jan Kiszka <[email protected]> Reviewed-by: Suman Anna <[email protected]> Signed-off-by: Nishanth Menon <[email protected]> Link: https://lore.kernel.org/r/1776f8be19b39a938d9248fcfc5332b753783c3e.1632657917.git.jan.kiszka@web.de
2021-10-05arm64: dts: ti: iot2050: Disable SR2.0-only PRUsJan Kiszka1-0/+24
The IOT2050 devices described so far are using SR1.0 silicon, thus do not have the additional PRUs of the ICSSG of the SR2.0. Disable them. Signed-off-by: Jan Kiszka <[email protected]> Acked-by: Aswath Govindraju <[email protected]> Acked-by: Suman Anna <[email protected]> Signed-off-by: Nishanth Menon <[email protected]> Link: https://lore.kernel.org/r/189a91866fb1af02e4fd2345dc56774aa069d5ba.1632657917.git.jan.kiszka@web.de
2021-10-05arm64: dts: ti: iot2050: Flip mmc device ordering on Advanced devicesJan Kiszka1-0/+2
This ensures that the SD card will remain mmc0 across Basic and Advanced devices, also avoiding surprises for users coming from the downstream kernels. Signed-off-by: Jan Kiszka <[email protected]> Acked-by: Aswath Govindraju <[email protected]> Signed-off-by: Nishanth Menon <[email protected]> Link: https://lore.kernel.org/r/fe20d6346f119a28e47d129b616682001299cf0e.1632657917.git.jan.kiszka@web.de
2021-10-05arm64: dts: ti: k3-j7200-common-proc-board: Add j7200-evm compatibleNishanth Menon1-0/+3
Add j7200-evm compatible to the board to allow the board to distinguish itself from other platforms that may be added in the future. Signed-off-by: Nishanth Menon <[email protected]> Acked-by: Suman Anna <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2021-10-05arm64: dts: ti: k3-j721e-common-proc-board: Add j721e-evm compatibleNishanth Menon1-0/+3
Add j721e-evm compatible to the board to allow the board to distinguish itself from other platforms that are pending to be added. Signed-off-by: Nishanth Menon <[email protected]> Acked-by: Suman Anna <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2021-10-05dt-bindings: arm: ti: Add missing compatibles for j721e/j7200 evmsNishanth Menon1-2/+10
Add compatibles for j721e and j7200 evms to allow for newer platforms to distinguish themselves. While doing this, maintain support for older style of description where the board compatibility was not required. Signed-off-by: Nishanth Menon <[email protected]> Acked-by: Rob Herring <[email protected]> Acked-by: Suman Anna <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2021-10-05arm64: dts: ti: Makefile: Collate AM64 platforms togetherNishanth Menon1-1/+0
Make sure that the platforms are grouped together per SoC. This helps keep the Makefile readable as newer platforms get added to the list. Signed-off-by: Nishanth Menon <[email protected]> Acked-by: Suman Anna <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2021-10-05arm64: dts: ti: k3-am64-main: Add ICSSG nodesSuman Anna3-0/+296
Add the DT nodes for the ICSSG0 and ICSSG1 processor subsystems that are present on the K3 AM64x SoCs. The two ICSSGs are identical to each other for the most part, with some of the peripheral pins from ICSSG1 not pinned out. Each ICSSG instance is represented by a PRUSS subsystem node and other child nodes. The nodes are all added and enabled in the common k3-am64-main.dtsi file by default. The MDIO nodes need pinctrl lines, and so should be enabled only on boards where they are actually wired and pinned out for ICSSG Ethernet. Any new board dts file should disable these if they are not sure. These are disabled in the existing AM64x board dts files to begin with. The ICSSGs on K3 AM64x SoCs are very similar to the versions of the ICSSG on K3 J721E and AM65x SR2.0 SoCs. The IRAM and BroadSize RAM sizes are all identical to those on J721E SoCs. All The ICSSG host interrupts intended towards the main Arm core are also shared with other processors on the SoC, and can be partitioned as per system integration needs. The ICSSG subsystem node contains the entire address space. The various sub-modules of the ICSSG are represented as individual child nodes (so platform devices themselves) of the PRUSS subsystem node. These include: - two Programmable Real-Time Units (PRUs) - two auxiliary PRU cores called RTUs - two Transmit Programmable Real-Time Units (Tx_PRUs) - Interrupt controller (INTC) - a 'memories' node containing all the ICSSG level Data RAMs - Real Time Media Independent Interface controller (MII_RT) - Gigabit capable MII_G_RT - ICSSG CFG sub-module providing two internal clock muxes, with the default clock parents also assigned using the assigned-clock-parents property. The default names for the firmware images for each PRU, RTU and Tx_PRU cores are defined as follows using the 'firmware-name' property (these can be adjusted either in derivative board dts files or through sysfs at runtime if required): ICSSG0 PRU0 Core : am64x-pru0_0-fw ; PRU1 Core : am64x-pru0_1-fw ICSSG0 RTU0 Core : am64x-rtu0_0-fw ; RTU1 Core : am64x-rtu0_1-fw ICSSG0 Tx_PRU0 Core : am64x-txpru0_0-fw ; Tx_PRU1 Core : am64x-txpru0_1-fw ICSSG1 PRU0 Core : am64x-pru1_0-fw ; PRU1 Core : am64x-pru1_1-fw ICSSG1 RTU0 Core : am64x-rtu1_0-fw ; RTU1 Core : am64x-rtu1_1-fw ICSSG1 Tx_PRU0 Core : am64x-txpru1_0-fw ; Tx_PRU1 Core : am64x-txpru1_1-fw Note: 1. The ICSSG INTC on AM64x SoCs share all the host interrupts with other processors, so use the 'ti,irqs-reserved' property in derivative board dts files _if_ any of them should not be handled by the host OS. 2. There are few more sub-modules like the Industrial Ethernet Peripherals (IEPs), eCAP, PWM, UART that do not have bindings and so will be added in the future. Signed-off-by: Suman Anna <[email protected]> Signed-off-by: Vignesh Raghavendra <[email protected]> Signed-off-by: Grygorii Strashko <[email protected]> Reviewed-by: Kishon Vijay Abraham I <[email protected]> Signed-off-by: Nishanth Menon <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2021-10-05Merge tag 'renesas-dt-bindings-for-v5.16-tag1' of ↵Arnd Bergmann1-0/+61
git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into arm/dt Renesas DT binding updates for v5.16 - Document support for the new R-Car H3e, M3e, M3Ne(-2G), D3e, E3e, and H3Ne SoCs and boards. * tag 'renesas-dt-bindings-for-v5.16-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel: dt-bindings: arm: renesas: Document more R-Car Gen3e Socs and boards Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Arnd Bergmann <[email protected]>
2021-10-05Merge tag 'renesas-arm-dt-for-v5.16-tag1' of ↵Arnd Bergmann54-1469/+2375
git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into arm/dt Renesas ARM DT updates for v5.16 - I2C EEPROM support on the RZA2MEVB development board, - DMA, USB2.0, and audio support for the RZ/G2L SoC, - USB2.0, I2C, audio, ADC, and CANFD support for the RZ/G2L SMARC EVK development board, - Support for more R-Car Gen3e SoCs (H3e, M3e, M3Ne(-2G), D3e, E3e, H3Ne), - PWM support for the R-Car M3-W+ and V3U SoCs, - IPMMU support for SDHI on the R-Car V3U SoC, - Switches support for the Falcon development board, - Improve Ethernet PHY descriptions to fix reset handling after kexec, - Miscellaneous fixes and improvements. * tag 'renesas-arm-dt-for-v5.16-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel: (45 commits) arm64: dts: renesas: rcar-gen3: Add missing Ethernet PHY resets ARM: dts: rzg1: Add missing Ethernet PHY resets ARM: dts: r-mobile: Add missing Ethernet PHY resets arm64: dts: renesas: Add compatible properties to RTL8211E Ethernet PHYs arm64: dts: renesas: Add compatible properties to KSZ9031 Ethernet PHYs arm64: dts: renesas: Add compatible properties to AR8031 Ethernet PHYs ARM: dts: renesas: Add compatible properties to uPD6061x Ethernet PHYs ARM: dts: renesas: Add compatible properties to RTL8201FL Ethernet PHYs ARM: dts: renesas: Add compatible properties to LAN8710A Ethernet PHYs ARM: dts: renesas: Add compatible properties to KSZ9031 Ethernet PHYs ARM: dts: renesas: Add compatible properties to KSZ8081 Ethernet PHYs ARM: dts: renesas: Add compatible properties to KSZ8041 Ethernet PHYs arm64: dts: renesas: beacon: Fix Ethernet PHY mode ARM: dts: renesas: Fix SMSC Ethernet compatible values arm64: dts: renesas: rzg2l-smarc: Enable CANFD arm64: dts: renesas: rzg2l-smarc-som: Enable ADC on SMARC platform arm64: dts: renesas: rzg2l-smarc-som: Move extal and memory nodes to SOM DTSI arm64: dts: renesas: r8a779a0: falcon-cpu: Add SW47-SW49 support arm64: dts: renesas: rzg2l-smarc: Add Mic routing arm64: dts: renesas: rzg2l-smarc: Enable audio ... Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Arnd Bergmann <[email protected]>
2021-10-05Merge tag 'v5.16-rockchip-dts32-1' of ↵Arnd Bergmann8-22/+48
git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into arm/dt ADC-keys for the mk808 board and a number of further cleanups to make dt-schema happier. * tag 'v5.16-rockchip-dts32-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: ARM: dts: rockchip: swap timer clock-names ARM: dts: rockchip: add more angle brackets to operating-points property on rk3066a ARM: dts: rockchip: rename opp-table node names ARM: dts: rockchip: change rv1108 gmac nodename ARM: dts: rockchip: add adc-keys node to rk3066a-mk808 Link: https://lore.kernel.org/r/5121280.Lt9SDvczpP@phil Signed-off-by: Arnd Bergmann <[email protected]>
2021-10-05Merge tag 'v5.16-rockchip-dts64-1' of ↵Arnd Bergmann33-625/+3169
git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into arm/dt This contains the parts that were originally meant for 5.15 + some new thing: New boards: Firefly roc-rk3399-pc-pls and rk3328-pc; Scarlet-Dumo tablet variant; Rock Pi 4 A+, B+; Pine64 Quartz64-A (rk3566-based) Big additions for the rk3568: tsadc; saradc; gpio-support; gmac 1+2; watchdog; pmu; io-domains and enabling these new things on the rk3568-evb. Addition of the rk3566 - a variant of the rk3568 with slightly less peripherals. SFC (serial flash controller) for rk3308 and px30 (including the Odroid Go2) Support for the rk3399's second image signal processor and its coresight component. And camera + vpu support on px30. A number of smaller additions to multiple boards (Rock Pi 4, Pinebook Pro and helios64, lion-haikou, Odroid-Go2) and cleanups in some parts. * tag 'v5.16-rockchip-dts64-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: (65 commits) arm64: dts: rockchip: add phandles to muxed i2c buses on rk3368-lion arm64: dts: rockchip: define iodomains for rk3368-lion arm64: dts: rockchip: fix LDO_REG4 / LDO_REG7 confusion on rk3368-lion arm64: dts: rockchip: align operating-points table name with dtschema arm64: dts: rockchip: hook up camera on px30-evb arm64: dts: rockchip: add isp node for px30 arm64: dts: rockchip: add Coresight debug range for RK3399 arm64: dts: rockchip: Correct regulator for USB host on Odroid-Go2 arm64: dts: rockchip: fix PCI reg address warning on rk3399-gru arm64: dts: rockchip: add saradc to rk3568-evb1-v10 arm64: dts: rockchip: Fix GPU register width for RK3328 arm64: dts: rockchip: Re-add interrupt-names for RK3399's vpu arm64: dts: rockchip: add missing rockchip,grf property to rk356x arm64: dts: rockchip: add RK3399 Gru gpio-line-names arm64: dts: rockchip: Enable SFC for Odroid Go Advance arm64: dts: rockchip: Add SFC to RK3308 arm64: dts: rockchip: Add SFC to PX30 arm64: dts: rockchip: add thermal support to Quartz64 Model A arm64: dts: rockchip: add rk3568 tsadc nodes arm64: dts: rockchip: add rk356x gpio debounce clocks ... Link: https://lore.kernel.org/r/4439872.CQOukoFCf9@phil Signed-off-by: Arnd Bergmann <[email protected]>
2021-10-05Merge tag 'zynqmp-dt-for-v5.16' of https://github.com/Xilinx/linux-xlnx into ↵Arnd Bergmann20-98/+2861
arm/dt arm64: dts: ZynqMP DT changes for v5.16 - Fix issues reported by dtbs_check - Enable DMAs, DP, USB, NAND on various boards - Add description for irps5401 - Add pinctrl description - Add psgtr description for usb3, sata and DP - Start to use nvmem alias for eeprom reference - Clean up aliases list - Wire qspi and usb3.0 - Add support for zcu102-rev1.1 - Couple of minor fixes and sync patches * tag 'zynqmp-dt-for-v5.16' of https://github.com/Xilinx/linux-xlnx: (36 commits) arm64: zynqmp: Wire psgtr for zc1751-xm013 arm64: zynqmp: Enable xlnx,zynqmp-dwc3 driver for xilinx boards arm64: zynqmp: Enable gpio and qspi for zc1275-revA arm64: zynqmp: Fix serial compatible string arm64: zynqmp: Remove not documented is-dual property arm64: zynqmp: Add psgtr description to zc1751 dc1 board arm64: zynqmp: Add support for zcu102-rev1.1 board arm64: zynqmp: Remove description for 8T49N287 and si5382 chips arm64: zynqmp: Sync psgtr node location with zcu104-revA arm64: zynqmp: Add reset description for sata arm64: zynqmp: Move rtc to different location on zcu104-revA arm64: zynqmp: Wire qspi on multiple boards arm64: zynqmp: Remove information about dma clock on zcu106 arm64: zynqmp: Update rtc calibration value arm64: zynqmp: Add note about UHS mode on some boards arm64: zynqmp: Move DP nodes to the end of file on zcu106 arm64: zynqmp: Remove can aliases from zc1751 arm64: zynqmp: Add reset-on-timeout to all boards and modify default timeout value arm64: zynqmp: List reset property for ethernet phy arm64: zynqmp: Add nvmem alises for eeproms ... Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Arnd Bergmann <[email protected]>
2021-10-05arm64: dts: imx8mm-kontron: Fix reset delays for ethernet PHYFrieder Schrempf1-2/+2
According to the datasheet the VSC8531 PHY expects a reset pulse of 100 ns and a delay of 15 ms after the reset has been deasserted. Set the matching values in the devicetree. Reported-by: Heiko Thiery <[email protected]> Signed-off-by: Frieder Schrempf <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2021-10-05arm64: dts: imx8mm: add DISP blk-ctrlLucas Stach1-0/+27
Add the DT node for the DISP blk-ctrl. With this in place the display/mipi power domains are fully functional. Signed-off-by: Lucas Stach <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2021-10-05arm64: dts: imx8mm: add VPU blk-ctrlLucas Stach1-0/+13
Add the DT node for the VPU blk-ctrl. With this in place the VPU power domains are fully functional. Signed-off-by: Lucas Stach <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2021-10-05arm64: dts: imx8mm: Add GPU nodes for 2D and 3D coreFrieder Schrempf1-0/+31
According to the documents, the i.MX8M-Mini features a GC320 and a GCNanoUltra GPU core. Etnaviv detects them as: etnaviv-gpu 38000000.gpu: model: GC600, revision: 4653 etnaviv-gpu 38008000.gpu: model: GC520, revision: 5341 This seems to work fine more or less without any changes to the HWDB, which still might be needed in the future to correct some features, etc. [lst]: Added power domains and switched clock assignments to the new clock defines used for the composite clocks, instead of relying on the backwards compat defines. Signed-off-by: Frieder Schrempf <[email protected]> Signed-off-by: Lucas Stach <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2021-10-05arm64: dts: imx8mm: put USB controllers into power-domainsLucas Stach1-0/+2
Now that we have support for the power domain controller on the i.MX8MM we can put the USB controllers in their respective power domains to allow them to power down the PHY when possible. Signed-off-by: Lucas Stach <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2021-10-05arm64: dts: imx8mm: add GPC nodeLucas Stach1-0/+107
Add the DT node for the GPC, including all the PGC power domains, some of them are not fully functional yet, as they require interaction with the blk-ctrls to properly power up/down the peripherals. Signed-off-by: Lucas Stach <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2021-10-05dt-bindings: power: imx8mm: add defines for DISP blk-ctrl domainsLucas Stach1-0/+5
This adds the defines for the power domains provided by the DISP blk-ctrl. Signed-off-by: Lucas Stach <[email protected]> Acked-by: Rob Herring <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2021-10-05dt-bindings: soc: add binding for i.MX8MM DISP blk-ctrlLucas Stach1-0/+94
This adds the DT binding for the i.MX8MM VPU blk-ctrl. Signed-off-by: Lucas Stach <[email protected]> Reviewed-by: Rob Herring <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2021-10-05dt-bindings: power: imx8mm: add defines for VPU blk-ctrl domainsLucas Stach1-0/+4
This adds the defines for the power domains provided by the VPU blk-ctrl. Signed-off-by: Lucas Stach <[email protected]> Acked-by: Rob Herring <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2021-10-05dt-bindings: soc: add binding for i.MX8MM VPU blk-ctrlLucas Stach1-0/+76
This adds the DT binding for the i.MX8MM VPU blk-ctrl. Signed-off-by: Lucas Stach <[email protected]> Reviewed-by: Rob Herring <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2021-10-05ARM: dts: imx6: skov: provide panel support for lt2 variantsOleksij Rempel3-0/+101
Add support for the Logic Technologies LTTD800x480 L2RT 7" 800x480 TFT Resistive Touch Module. Signed-off-by: Oleksij Rempel <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2021-10-05arm64: dts: ls1028a: mark internal links between Felix and ENETC as capable ↵Vladimir Oltean1-0/+4
of flow control The internal Ethernet switch suffers from erratum A-050484 ("Ethernet flow control not functional on L2 switch NPI port when XFH is used"). XFH stands for "Extraction Frame Header" - which basically means the default "ocelot" DSA tagging protocol. However, the switch supports one other tagging protocol - "ocelot-8021q", and this is not subject to the erratum above. So describe the hardware ability to pass PAUSE frames in the device tree, and let the driver figure out whether it should use flow control on the CPU port or not, depending on whether the "ocelot" or "ocelot-8021q" tagging protocol is being used. Signed-off-by: Vladimir Oltean <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2021-10-05arm64: dts: freescale: Fix 'interrupt-map' parent address cellsRob Herring3-36/+36
The 'interrupt-map' in several Layerscape SoCs is malformed. The '#address-cells' size of the parent interrupt controller (the GIC) is not accounted for. Cc: Shawn Guo <[email protected]> Cc: Li Yang <[email protected]> Cc: [email protected] Signed-off-by: Rob Herring <[email protected]> Acked-by: Li Yang <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2021-10-05ARM: dts: imx6qdl-apalis: Fix typo in ADC commentFabio Estevam1-1/+1
Fix the spelling of 'conversion'. Signed-off-by: Fabio Estevam <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2021-10-05ARM: dts: imx6qdl-apalis: Add a label for the touchscreenFabio Estevam1-1/+1
Add a label for the touchscreen to allow a custom baseboard to disable this node if needed. Signed-off-by: Fabio Estevam <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2021-10-05ARM: dts: imx6qdl-apalis: Pass 'io-channel-cells' to the ADCFabio Estevam1-1/+2
The STMPE811 ADC on the Apalis SoM board can be used as a provider of ADC capabilities to other devices, for example, when a custom baseboard has an SN74LV4051 analog mux. Pass the 'io-channel-cells' parameter to indicate such possibility. While at it, also pass a label for the adc device, so that it can be referenced in the custom baseboard. Signed-off-by: Fabio Estevam <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
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