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2023-10-13drm/amdgpu: enable GFX IP v11.5.0 CG and PG supportLi Ma3-3/+23
Add CG support for GFX/MC/HDP/ATHUB/IH/BIF. Add PG support for GFX. Signed-off-by: Li Ma <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-10-13drm/amdgpu: add support to power up/down UMSCH by SMULang Yu2-0/+27
Power up/down UMSCH by SMU. Signed-off-by: Lang Yu <[email protected]> Acked-by: Leo Liu <[email protected]> Acked-by: Veerabadhran Gopalakrishnan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-10-13drm/amdgpu: add power up/down UMSCH ppt callbackLang Yu3-1/+24
Add ppt callback to power up/down UMSCH. v2: squash in updates (Alex) Signed-off-by: Lang Yu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-10-13drm/amdgpu: add support to powerup VPE by SMULang Yu3-0/+31
Powerup VPE by SMU. Signed-off-by: Lang Yu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-10-13drm/amdgpu/discovery: add SMU 14 supportLi Ma3-0/+12
add smu 14 into the IP discovery list. Signed-off-by: Li Ma <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-10-13drm/amd/swsmu: add smu14 ip supportKenneth Feng10-3/+3110
Add initial swSMU support for smu 14 series ASIC. v2: squash in build fixes and updates (Li Ma) fix warnings (Alex) v3: squash in updates (Alex) v4: squash in updates (Alex) v5: squash in avg/current power updates (Alex) Signed-off-by: Li Ma <[email protected]> Signed-off-by: Kenneth Feng <[email protected]> Signed-off-by: Likun Gao <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-10-13drm/amd/swsmu: add smu v14_0_0 pmfw if fileLi Ma1-0/+156
Add initial smu v14_0_0 pmfw if file v2: squash in updates (Alex) Signed-off-by: Li Ma <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-10-13drm/amd/swsmu: add smu v14_0_0 ppsmc fileLi Ma1-0/+142
Add initial smu v14_0_0 ppsmc file v2: squash in updates (Alex) v3: squash in updates (Alex) Signed-off-by: Li Ma <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-10-13drm/amdgpu/swsmu: add smu v14_0_0 driver if fileLi Ma1-0/+281
Add initial smu v14_0_0 driver if file v2: squash in updates (Alex) v3: update interface (Alex) Signed-off-by: Li Ma <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-10-13drm/amdgpu/umsch: power on/off UMSCH by DLDOLang Yu1-0/+26
VCN 4.0.5 uses DLDO. Signed-off-by: Lang Yu <[email protected]> Reviewed-by: Veerabadhran Gopalakrishnan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-10-13drm/amdgpu/umsch: fix psp frontdoor loadingLang Yu3-88/+72
These changes are missed in rebase. Signed-off-by: Lang Yu <[email protected]> Reviewed-by: Veerabadhran Gopalakrishnan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-10-13drm/amdgpu: Increase IP discovery region sizeLijo Lazar1-1/+1
IP discovery region has increased to > 8K on some SOCs.Maximum reserve size is upto 12K, but not used. For now increase to 10K. Signed-off-by: Lijo Lazar <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-10-13drm/amd/pm: Use gpu_metrics_v1_4 for SMUv13.0.6Asad Kamal1-24/+41
Use gpu_metrics_v1_4 for SMUv13.0.6 to fill gpu metric info v3: Removed filling gpu metric instantaneous pcie bw Signed-off-by: Asad Kamal <[email protected]> Reviewed-by: Lijo Lazar <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-10-13drm/amd/pm: Add gpu_metrics_v1_4Asad Kamal2-0/+79
Add new gpu_metrics_v1_4 to acquire XGMI data transfer, pcie bandwidth & Clock lock status v2: Add pcie error counter to gpu metric table v1_4 Signed-off-by: Asad Kamal <[email protected]> Reviewed-by: Lijo Lazar <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-10-13drm/amd/pm: Update metric table for smu v13_0_6Asad Kamal1-1/+5
Update pmfw metric table to include xgmi transfer data and pci instantaneous bandwidth for smu v13_0_6 v2: Updated metric table version v3: Removed inst pcie bw with alignment to metrics table version 8 Signed-off-by: Asad Kamal <[email protected]> Reviewed-by: Lijo Lazar <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-10-13drm/amdgpu: Return -EINVAL when MMSCH init status incorrectLin.Cao1-1/+4
Return -EINVAL when MMSCH init fail which can be handle by function amdgpu_device_reset_sriov correctly. Signed-off-by: Lin.Cao <[email protected]> Reviewed-by: Jingwen Chen <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-10-13drm/amd/pm: wait for completion of the EnableGfxImu commandTim Huang1-2/+10
Wait for completion of sending the EnableGfxImu message when using the PSP FW loading. Signed-off-by: Tim Huang <[email protected]> Reviewed-by: Yifan Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-10-13drm/amdgpu/vpe: fix insert_nop opsLang Yu1-4/+5
Avoid infinite loop when count is 0. This is missed in rebase. Signed-off-by: Lang Yu <[email protected]> Reviewed-by: Yifan Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-10-13drm/amdgpu: Address member 'gart_placement' not described in ↵Srinivasan Shanmugam1-0/+1
'amdgpu_gmc_gart_location' Fixes the below: drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c:274: warning: Function parameter or member 'gart_placement' not described in 'amdgpu_gmc_gart_location' Cc: Christian König <[email protected]> Cc: Alex Deucher <[email protected]> Cc: "Pan, Xinhui" <[email protected]> Signed-off-by: Srinivasan Shanmugam <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-10-13drm/amdgpu/vpe: align with mcbp changesLang Yu1-1/+1
MCBP is decided by adev->gfx.mcbp now. This is missed in rebase. Signed-off-by: Lang Yu <[email protected]> Reviewed-by: Yifan Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-10-13drm/amdgpu/vpe: remove IB end boundary requirementLang Yu1-19/+1
Remove IB end boundary requirement, VPE has no such limitions, use existing amdgpu_ring_generic_pad_ib() instead. This is missed in rebase. Signed-off-by: Lang Yu <[email protected]> Reviewed-by: Yifan Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-10-13drm/amdgpu: Improve MES responsiveness during oversubscriptionJay Cornwall1-0/+1
When MES is oversubscribed it may not frequently check for new command submissions from driver if the scheduling load is high. Response latency as high as 5 seconds has been observed. Enable a flag which adds a check for new commands between scheduling quantums. Signed-off-by: Jay Cornwall <[email protected]> Cc: Alexandru Tudor <[email protected]> Reviewed-by: Harish Kasiviswanathan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-10-09drm/amdgpu: fix SI failure due to doorbells allocationIcenowy Zheng1-0/+4
SI hardware does not have doorbells at all, however currently the code will try to do the allocation and thus fail, makes SI AMDGPU not usable. Fix this failure by skipping doorbells allocation when doorbells count is zero. Fixes: 54c30d2a8def ("drm/amdgpu: create kernel doorbell pages") Reviewed-by: Shashank Sharma <[email protected]> Signed-off-by: Icenowy Zheng <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-10-09drm/amdgpu/discovery: enable DCN 3.5.0 supportAaron Liu1-0/+1
Enable DCN 3.5.0 support. Signed-off-by: Aaron Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-10-09drm/amdkfd: get doorbell's absolute offset based on the db_sizeArvind Yadav5-10/+24
Here, Adding db_size in byte to find the doorbell's absolute offset for both 32-bit and 64-bit doorbell sizes. So that doorbell offset will be aligned based on the doorbell size. v2: - Addressed the review comment from Felix. v3: - Adding doorbell_size as parameter to get db absolute offset. v4: Squash the two patches into one. Cc: Christian Koenig <[email protected]> Cc: Alex Deucher <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Shashank Sharma <[email protected]> Signed-off-by: Arvind Yadav <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-10-09drm/amdgpu: add missing NULL checkChristian König1-1/+1
bo->tbo.resource can easily be NULL here. Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2902 Signed-off-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]> CC: [email protected]
2023-10-09drm/amd/display: 3.2.255Aric Cyr1-1/+1
This version brings along following fixes: - Refactor DPG test pattern logic for ODM cases - Refactor HWSS into component folder - Revert "drm/amd/display: Add a check for idle power optimization" - Revert "drm/amd/display: remove duplicated edp relink to fastboot - Update cursor limits based on SW cursor fallback limits - Update stream mask - Update pmfw_driver_if new structure - Modify SMU message logs - Don't set dpms_off for seamless boot Known issue: DWB (Writeback functionality) is broken. Fix will be available in DC 3.2.256 Acked-by: Tom Chung <[email protected]> Signed-off-by: Aric Cyr <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-10-09drm/amd/display: Disable virtual linksStylon Wang1-1/+1
[Why] This could work around the issue with DP tunneling producing a NULL pointer dereference. [How] Disable the virtual links. Reviewed-by: Tom Chung <[email protected]> Acked-by: Tom Chung <[email protected]> Signed-off-by: Stylon Wang <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-10-09drm/amd/display: Disable SubVP if test pattern is enabledGeorge Shen1-1/+14
[Why] Enabling DPG causes HUBP to stay in blank constantly. If DPG is enabled while an MCLK switch is taking place with SubVP, it will cause the MCLK to never complete. This is because SubVP MCLK switch relies a HUBP VLine interrupt, which will never occur when HUBP is constantly in blank. [How] Disable SubVP when test pattern is enabled. Reviewed-by: Alvin Lee <[email protected]> Reviewed-by: Nevenko Stupar <[email protected]> Acked-by: Tom Chung <[email protected]> Signed-off-by: George Shen <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-10-09drm/amd/display: Refactor DPG test pattern logic for ODM casesGeorge Shen6-93/+175
[Why] Current DPG test pattern logic does not account for ODM configuration changes after test pattern has already been programmed. For example, if ODM2:1 is enabled after test pattern is already being output, the second pipe is not programmed to output test pattern, causing half the screen to be black. [How] Move DPG test pattern parameter calculations into separate function. Whenever ODM pipe configuration changes, re-calculate DPG test pattern parameters and program DPG if test pattern is currently enabled. Reviewed-by: Wenjing Liu <[email protected]> Acked-by: Tom Chung <[email protected]> Signed-off-by: George Shen <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-10-09drm/amd/display: Don't set dpms_off for seamless bootDaniel Miess1-0/+3
[Why] eDPs fail to light up with seamless boot enabled [How] When seamless boot is enabled don't configure dpms_off in disable_vbios_mode_if_required. Reviewed-by: Charlene Liu <[email protected]> Cc: Mario Limonciello <[email protected]> Cc: Alex Deucher <[email protected]> Cc: [email protected] Acked-by: Tom Chung <[email protected]> Signed-off-by: Daniel Miess <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-10-09drm/amd/display: Refactor HWSS into component folderMounika Adhuri94-116/+300
[why] Rename hw_sequencer to hwseq. Move all hwseq files to unique folder hwss. [how] creating hwss repo in dc, and moved the dcnxx_hwseq.c and .h files into corresponding new folders inside the hwss and cleared the linkage errors by adding relative paths in the Makefile.template. Reviewed-by: Martin Leung <[email protected]> Acked-by: Tom Chung <[email protected]> Signed-off-by: Mounika Adhuri <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-10-09drm/amd/display: Revert "drm/amd/display: Add a check for idle power ↵Sung Joon Kim3-21/+1
optimization" Revert commit 434cf7af492f ("drm/amd/display: Add a check for idle power optimization") Because it cause Freesync and S4 regression Reviewed-by: Aric Cyr <[email protected]> Acked-by: Tom Chung <[email protected]> Signed-off-by: Sung Joon Kim <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-10-09drm/amdgpu: add hub->ctx_distance in setup_vmid_configYifan Zhang17-17/+18
add hub->ctx_distance when read CONTEXT1_CNTL, align w/ write back operation. v2: fix coding style errors reported by checkpatch.pl (Christian) Signed-off-by: Yifan Zhang <[email protected]> Acked-by: Christian König <[email protected]> Reviewed-by: Lang Yu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-10-09drm/amd/display: Don't use fsleep for PSR exit waitsNicholas Kazlauskas2-2/+4
[Why] These functions can be called from high IRQ levels and the OS will hang if it tries to use a usleep_highres or a msleep. [How] Replace the fsleep with a udelay. Reviewed-by: Aric Cyr <[email protected]> Acked-by: Tom Chung <[email protected]> Signed-off-by: Nicholas Kazlauskas <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-10-09drm/amd/display: Update cursor limits based on SW cursor fallback limitsAlvin Lee4-37/+47
[Why&How] For determining the cursor size limit, use the same checks that are used for determining SW cursor fallback instead of only using SubVP Reviewed-by: Aric Cyr <[email protected]> Acked-by: Tom Chung <[email protected]> Signed-off-by: Alvin Lee <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-10-09drm/amd/display: Update dml ssb from pmfw clock tableMuhammad Ahmed3-27/+3
[why] Need to use real clock table [How] Update the clock table Reviewed-by: Charlene Liu <[email protected]> Acked-by: Tom Chung <[email protected]> Signed-off-by: Muhammad Ahmed <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-10-09drm/amd/display: Update stream maskDuncan Ma1-0/+7
[Why] Whenever stream changes because of new pipe arrangements such as ODM. The new stream mask is not reflected in DMCUB. The mismatch in stream mask is blocking ips entry in some scenarios. [How] Whenever stream arrangement changes, update stream mask and notify DMCUB. Reviewed-by: Charlene Liu <[email protected]> Acked-by: Tom Chung <[email protected]> Signed-off-by: Duncan Ma <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-10-09drm/amd/display: Revert "drm/amd/display: remove duplicated edp relink to ↵Aric Cyr1-0/+59
fastboot" Revert commit 984abb5384b0 ("drm/amd/display: remove duplicated edp relink to fastboot") Because it cause 4k EDP not light up on boot Reviewed-by: Tom Chung <[email protected]> Cc: Mario Limonciello <[email protected]> Cc: Alex Deucher <[email protected]> Acked-by: Tom Chung <[email protected]> Signed-off-by: Aric Cyr <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-10-09drm/amd/display: Modify Vmin default valueMax Tseng2-2/+8
Fine tune the Vmin clock value Reviewed-by: Robin Chen <[email protected]> Acked-by: Tom Chung <[email protected]> Signed-off-by: Max Tseng <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-10-09drm/amd/display: Update pmfw_driver_if new structureCharlene Liu2-76/+174
[why] pmfw header file updated, need align with data structure. [How] Update the data structure. Reviewed-by: Sung joon Kim <[email protected]> Acked-by: Tom Chung <[email protected]> Signed-off-by: Charlene Liu <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-10-09drm/amd/display: VSIF v3 set Max Refresh RateMuhammad Ansari1-7/+2
[WHY] FreeSync spec requires PB8 and PB12 to be set to nominal refresh rate regardless of fixed rate or variable [HOW] Removed the condition that checks and overwrites max refresh rate and set PB8/PB12 to be set to max refresh rate always Reviewed-by: Anthony Koo <[email protected]> Acked-by: Tom Chung <[email protected]> Signed-off-by: Muhammad Ansari <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-10-09drm/amd/display: Modify SMU message logsSung Joon Kim4-6/+9
[why] It's important to make sure SMU messages are logged by default to improve debugging for power optimization use cases. [how] Change logs to warnings when SMU message returns non-success id. Reviewed-by: Charlene Liu <[email protected]> Acked-by: Tom Chung <[email protected]> Signed-off-by: Sung Joon Kim <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-10-09drm/amdgpu: Fix potential null pointer derefernceStanley.Yang1-1/+2
The amdgpu_ras_get_context may return NULL if device not support ras feature, so add check before using. Signed-off-by: Stanley.Yang <[email protected]> Reviewed-by: Tao Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-10-09drm/amd/display: enable S/G display for for recent APUs by defaultYifan Zhang1-33/+15
With S/G display becomes stable, enable S/G display for recent APUs by default rather than white list. v2: explicitly disable sg on pre-CZ chips (Alex) v3: add parens for every clause (Alex) Co-authored-by: Alex Deucher <[email protected]> Signed-off-by: Yifan Zhang <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-10-09Documentation/amdgpu: Add FRU attribute detailsLijo Lazar2-0/+31
Add documentation for the newly added manufacturer and fru_id attributes in sysfs. Signed-off-by: Lijo Lazar <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-10-09drm/amdgpu: Add more FRU field informationLijo Lazar2-3/+51
Add support to read Manufacturer Name and FRU File Id fields. Also add sysfs device attributes for external usage. Signed-off-by: Lijo Lazar <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-10-09drm/amdgpu: Refactor FRU product informationLijo Lazar9-36/+42
Keep FRU related information together in a separate structure. Signed-off-by: Lijo Lazar <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-10-09drm/amdgpu: enable FRU device for SMU v13.0.6Yang Wang1-19/+29
v1: enable GFX v9.4.3 FRU device to query board information. v2: use MP1 version to identify different asic Signed-off-by: Yang Wang <[email protected]> Reviewed-by: Lijo Lazar <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-10-09drm/amdgpu: update ib start and size alignmentBoyuan Zhang2-12/+13
Update IB starting address alignment and size alignment with correct values for decode and encode IPs. Decode IB starting address alignment: 256 bytes Decode IB size alignment: 64 bytes Encode IB starting address alignment: 256 bytes Encode IB size alignment: 4 bytes Also bump amdgpu driver version for this update. Signed-off-by: Boyuan Zhang <[email protected]> Reviewed-by: Christian König <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
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