diff options
| author | Max Tseng <[email protected]> | 2023-09-22 16:50:53 +0800 |
|---|---|---|
| committer | Alex Deucher <[email protected]> | 2023-10-09 16:53:17 -0400 |
| commit | 3557db425dd9e6d806617326bf71d1c8da2a707f (patch) | |
| tree | b6df3638575c94f6692105be111799a737cc4bef | |
| parent | 776ecb46ff2a6763038fe744f5be5bac08b36003 (diff) | |
drm/amd/display: Modify Vmin default value
Fine tune the Vmin clock value
Reviewed-by: Robin Chen <[email protected]>
Acked-by: Tom Chung <[email protected]>
Signed-off-by: Max Tseng <[email protected]>
Tested-by: Daniel Wheeler <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dcn314/dcn314_resource.c | 2 | ||||
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dcn35/dcn35_resource.c | 8 |
2 files changed, 8 insertions, 2 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_resource.c b/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_resource.c index d8fa229d78ce..64a2692fd4f6 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_resource.c @@ -1914,7 +1914,7 @@ static bool dcn314_resource_construct( dc->caps.color.mpc.ogam_rom_caps.hlg = 0; dc->caps.color.mpc.ocsc = 1; - dc->caps.max_disp_clock_khz_at_vmin = 694000; + dc->caps.max_disp_clock_khz_at_vmin = 650000; /* Use pipe context based otg sync logic */ dc->config.use_pipe_ctx_sync_logic = true; diff --git a/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_resource.c b/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_resource.c index 828846538a92..f1d776f39543 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_resource.c @@ -1830,7 +1830,13 @@ static bool dcn35_resource_construct( dc->caps.color.mpc.ogam_rom_caps.hlg = 0; dc->caps.color.mpc.ocsc = 1; - dc->caps.max_disp_clock_khz_at_vmin = 669154; + /* max_disp_clock_khz_at_vmin is slightly lower than the STA value in order + * to provide some margin. + * It's expected for furture ASIC to have equal or higher value, in order to + * have determinstic power improvement from generate to genration. + * (i.e., we should not expect new ASIC generation with lower vmin rate) + */ + dc->caps.max_disp_clock_khz_at_vmin = 650000; /* Use pipe context based otg sync logic */ dc->config.use_pipe_ctx_sync_logic = true; |