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2021-06-12arm64: dts: imx8mm-evk: disable over current for usb1Li Jun1-0/+1
imx8mm evk board usb1 port does not support over current detection, so disable it. Signed-off-by: Li Jun <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2021-06-12dt-bindings: arm: fsl: add GE B1x5pv2 boardsSebastian Reichel1-0/+11
Document the compatible for GE B1x5pv2 boards. Acked-by: Rob Herring <[email protected]> Signed-off-by: Sebastian Reichel <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2021-06-12dt-bindings: vendor-prefixes: add congatecSebastian Reichel1-0/+2
Document binding for congatec. Acked-by: Rob Herring <[email protected]> Signed-off-by: Sebastian Reichel <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2021-06-12arm64: dts: freescale: Separate each group of data in the property 'reg'Zhen Lei8-69/+69
Do not write the 'reg' of multiple groups of data into a uint32 array, use <> to separate them. Otherwise, the errors similar to the following will be reported by reg.yaml. arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dt.yaml: soc: pcie@3400000:reg:0: \ [0, 54525952, 0, 1048576, 64, 0, 0, 8192] is too long Signed-off-by: Zhen Lei <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2021-06-12arm64: dts: imx8: conn: fix enet clock settingDong Aisheng1-18/+32
enet_clk_ref actually is sourced from internal gpr clocks which needs a default rate. Also update enet lpcg clock output names to be more straightforward. Cc: Abel Vesa <[email protected]> Cc: Stephen Boyd <[email protected]> Signed-off-by: Dong Aisheng <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2021-06-12arm64: dts: imx8mq: assign PCIe clocksLucas Stach1-0/+16
This fixes multiple issues with the current non-existent PCIe clock setup: The controller can run at up to 250MHz, so use a parent that provides this clock. The PHY needs an exact 100MHz reference clock to function if the PCIe refclock is not fed in via the refclock pads. While this mode is not supported (yet) in the driver it doesn't hurt to make sure we are providing a clock with the right rate. The AUX clock is specified to have a maximum clock rate of 10MHz. So the current setup, which drives it straight from the 25MHz oscillator is actually overclocking the AUX input. Signed-off-by: Lucas Stach <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2021-06-12arm64: dts: imx8mn: specify dma-rangesLucas Stach1-0/+1
DMA addressing capabilities on i.MX8MN are limited by the interconnect, same as on i.MX8MQ. Add dma-ranges to the the peripheral bus to let the kernel know about this. Signed-off-by: Lucas Stach <[email protected]> Reviewed-by: Frieder Schrempf <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2021-06-12arm64: dts: imx8mm: specify dma-rangesLucas Stach1-0/+1
DMA addressing capabilities on i.MX8MM are limited by the interconnect, same as on i.MX8MQ. Add dma-ranges to the the peripheral bus to let the kernel know about this. Signed-off-by: Lucas Stach <[email protected]> Reviewed-by: Frieder Schrempf <[email protected]> Tested-by: Frieder Schrempf <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2021-06-12arm64: dts: fsl-ls1028a: Correct ECAM PCIE window rangesKornel Duleba1-7/+7
Currently all PCIE windows point to bus address 0x0, which does not match the values obtained from hardware during EA. Replace those values with CPU addresses, since in reality we have a 1:1 mapping between the two. Signed-off-by: Kornel Duleba <[email protected]> Acked-by: Claudiu Manoil <[email protected]> Reviewed-by: Vladimir Oltean <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2021-06-12arm64: dts: imx8mn-beacon-som: Assign PMIC clockAdam Ford1-0/+3
The PMIC throws an errors because the clock isn't assigned to it. Fix this by assigning the clocks info. Signed-off-by: Adam Ford <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2021-06-12arm64: dts: ls208xa: remove bus-num from dspi nodeMian Yousaf Kaukab1-1/+0
On LS2088A-RDB board, if the spi-fsl-dspi driver is built as module then its probe fails with the following warning: [ 10.471363] couldn't get idr [ 10.471381] WARNING: CPU: 4 PID: 488 at drivers/spi/spi.c:2689 spi_register_controller+0x73c/0x8d0 ... [ 10.471651] fsl-dspi 2100000.spi: Problem registering DSPI ctlr [ 10.471708] fsl-dspi: probe of 2100000.spi failed with error -16 Reason for the failure is that bus-num property is set for dspi node. However, bus-num property is not set for the qspi node. If probe for spi-fsl-qspi happens first then id 0 is dynamically allocated to it. Call to spi_register_controller() from spi-fsl-dspi driver then fails. Since commit 29d2daf2c33c ("spi: spi-fsl-dspi: Make bus-num property optional") bus-num property is optional. Remove bus-num property from dspi node to fix the issue. Signed-off-by: Mian Yousaf Kaukab <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2021-06-12arm64: dts: ls1012a: enable PCIe on freeway boardMian Yousaf Kaukab1-0/+4
ls1012a-freeway board contains a M.2 2230 slot. Update the status of pcei1 node to okay so that the pcie controller can be probed. Signed-off-by: Mian Yousaf Kaukab <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2021-06-12arm64: dts: imx8mp-evk: enable EQOS ethernetJoakim Zhang1-0/+40
Enable EQOS ethernet on i.MX8MP EVK board. Signed-off-by: Joakim Zhang <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2021-06-12arm64: dts: imx8mp: Remove the reference to audio ipg clock on imx8mpJacky Bai1-2/+0
On i.MX8MP, there is no audio ipg clock, so remove the wrong reference to this clock in dts file. Signed-off-by: Jacky Bai <[email protected]> Reviewed-by: Abel Vesa <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2021-06-12arm64: dts: imx8mq-evk: add one regulator used to power up pcie phyRichard Zhu1-0/+1
Both 1.8v and 3.3v power supplies can be used by i.MX8MQ PCIe PHY. In default, the PCIE_VPH voltage is suggested to be 1.8v refer to data sheet. When PCIE_VPH is supplied by 3.3v in the HW schematic design, the VREG_BYPASS bits of GPR registers should be cleared from default value 1b'1 to 1b'0. Thus, the internal 3v3 to 1v8 translator would be turned on. Signed-off-by: Richard Zhu <[email protected]> Reviewed-by: Lucas Stach <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2021-06-12arm64: dts: imx8mm: Add spba1 and spba2 busesAdam Ford1-173/+189
The i.MX8MM reference manual shows there are two spba busses. SPBA1 handles much of the serial interfaces, and SPBA2 covers much of the audio. Add both of them. Signed-off-by: Adam Ford <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2021-06-12arm64: dts: imx8mn: Add spba1 busAdam Ford1-69/+77
The i.MX8MN has an SPBA bus which covers much of the audio, but there is a second SPBA bus which covers many of the serial interfaces like SPI and UARTs currently missing from the device tree. The reference manual calls the bus handling the audio peripherals SPBA2, and the bus handling the serial peripherals is called SPBA1. Rename the existing spba bus to spba2 and add spba1. Signed-off-by: Adam Ford <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2021-06-12arm64: dts: imx8mq-nitrogen: add lt8912 MIPI-DSI to HDMIAdrien Grassein1-0/+121
Add support of the lt8912b in the DTB. This adds the support of the DB_DSIHD daugther board from Boundary Devices. Signed-off-by: Adrien Grassein <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2021-06-12arm64: dts: imx8mq-nitrogen: add USB HOST supportAdrien Grassein1-0/+26
Add the description for the USB host port. This port is linked to a resettable USB HUB so handle this reset signal with a GPIO hog. Signed-off-by: Adrien Grassein <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2021-06-12arm64: dts: imx8mq-nitrogen: add USB OTG supportAdrien Grassein1-0/+35
Add the description for the USB OTG port. The OTG port uses a dedicated regulator for vbus. Signed-off-by: Adrien Grassein <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2021-06-12arm64: dts: imx8mp-phycore-som: enable spi norHeiko Schocher1-0/+25
enable the mt25qu256aba spi nor on the imx8mp-phycore-som. Signed-off-by: Heiko Schocher <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2021-06-12ARM: dts: imx6: Add GE B1x5v2Sebastian Reichel9-0/+1244
This adds device tree files for the General Electric Healthcare (GEHC) B1x5v2 series. All models make use of Congatec's QMX6 system on module, which is described in its own device tree include, so that it can also be used by other boards. Signed-off-by: Sebastian Reichel <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2021-06-12ARM: dts: imx6q-dhcom: Add ethernet VIO regulatorChristoph Niedermaier1-0/+18
Add VIO regulator that supplies multiple ethernet magnetics and currently there is no upstream support for that in the networking, so just keep the regulator enabled always to emulate what other boards, which have this hard-wired, do. Until there is support. Signed-off-by: Christoph Niedermaier <[email protected]> Cc: Shawn Guo <[email protected]> Cc: Fabio Estevam <[email protected]> Cc: Marek Vasut <[email protected]> Cc: NXP Linux Team <[email protected]> Cc: [email protected] To: [email protected] Signed-off-by: Shawn Guo <[email protected]>
2021-06-12ARM: dts: imx6q-dhcom: Add aliases for i2c, serial and rtcChristoph Niedermaier1-1/+11
Add aliases for i2c and serial to match the order of the DHCOM standard [1]. Also add aliases for the two rtcs. The i2c rtc is the primary one. [1] https://wiki.dh-electronics.com/images/2/2e/DOC_DHCOM-Standard-Specification_R01_2016-11-17.pdf Signed-off-by: Christoph Niedermaier <[email protected]> Cc: Shawn Guo <[email protected]> Cc: Fabio Estevam <[email protected]> Cc: Marek Vasut <[email protected]> Cc: NXP Linux Team <[email protected]> Cc: [email protected] To: [email protected] Signed-off-by: Shawn Guo <[email protected]>
2021-06-12ARM: dts: imx6q-dhcom: Add gpios pinctrl for i2c bus recoveryChristoph Niedermaier1-3/+33
The i2c bus can freeze at the end of transaction so the bus can no longer work. This scenario is improved by adding scl/sda gpios definitions to implement the i2c bus recovery mechanism. Fixes: 52c7a088badd ("ARM: dts: imx6q: Add support for the DHCOM iMX6 SoM and PDK2") Signed-off-by: Christoph Niedermaier <[email protected]> Cc: Shawn Guo <[email protected]> Cc: Fabio Estevam <[email protected]> Cc: Marek Vasut <[email protected]> Cc: NXP Linux Team <[email protected]> Cc: [email protected] To: [email protected] Signed-off-by: Shawn Guo <[email protected]>
2021-06-12ARM: dts: imx6q-dhcom: Fix ethernet plugin detection problemsChristoph Niedermaier1-0/+1
To make the ethernet cable plugin detection reliable the power detection of the smsc phy has been disabled. Fixes: 52c7a088badd ("ARM: dts: imx6q: Add support for the DHCOM iMX6 SoM and PDK2") Signed-off-by: Christoph Niedermaier <[email protected]> Cc: Shawn Guo <[email protected]> Cc: Fabio Estevam <[email protected]> Cc: Marek Vasut <[email protected]> Cc: NXP Linux Team <[email protected]> Cc: [email protected] To: [email protected] Signed-off-by: Shawn Guo <[email protected]>
2021-06-12ARM: dts: imx6q-dhcom: Fix ethernet reset time propertiesChristoph Niedermaier1-2/+2
Fix ethernet reset time properties as described in Documentation/devicetree/bindings/net/ethernet-phy.yaml Fixes: 52c7a088badd ("ARM: dts: imx6q: Add support for the DHCOM iMX6 SoM and PDK2") Signed-off-by: Christoph Niedermaier <[email protected]> Cc: Shawn Guo <[email protected]> Cc: Fabio Estevam <[email protected]> Cc: Marek Vasut <[email protected]> Cc: NXP Linux Team <[email protected]> Cc: [email protected] To: [email protected] Signed-off-by: Shawn Guo <[email protected]>
2021-06-11arm64: tegra: Enable SMMU support on Tegra194Thierry Reding1-0/+86
Add the device tree node for the dual-SMMU found on Tegra194 and hook up peripherals such as host1x, BPMP, HDA, SDMMC, EQOS and VIC. Signed-off-by: Thierry Reding <[email protected]>
2021-06-11arm64: tegra: Hook up memory controller to SMMU on Tegra186Thierry Reding1-0/+2
On Tegra186 and later, the memory controller needs to be programmed in coordination with any of the ARM SMMU instances to configure the stream ID used for each memory client. To support this, add a phandle reference to the memory controller to the SMMU device tree node. Signed-off-by: Thierry Reding <[email protected]>
2021-06-11arm64: tegra: Use correct compatible string for Tegra186 SMMUThierry Reding1-1/+1
The SMMU found on Tegra186 requires interoperation with the memory controller in order to program stream ID overrides. The generic ARM SMMU 500 compatible is therefore inaccurate. Replace it with a more correct, SoC-specific compatible string. Signed-off-by: Thierry Reding <[email protected]>
2021-06-10arm64: dts: sc7280: Add interconnect provider DT nodesOdelu Kukatla1-0/+87
Add the DT nodes for the network-on-chip interconnect buses found on sc7280-based platforms. Signed-off-by: Odelu Kukatla <[email protected]> Link: https://lore.kernel.org/r/[email protected] [bjorn: Sorted nodes and dropped include] Signed-off-by: Bjorn Andersson <[email protected]>
2021-06-10arm64: dts: qcom: msm8916-huawei-g7: Add NFCStephan Gerhold1-0/+26
The Huawei Ascend G7 supports NFC using the NXP PN547, which is supported by the nxp-nci-i2c driver in mainline. It seems to detect NFC tags using "nfctool" just fine, although it seems like there are not really any useful applications making use of the Linux NFC subsystem. :( Signed-off-by: Stephan Gerhold <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2021-06-10arm64: dts: qcom: msm8916-huawei-g7: Add display regulatorStephan Gerhold1-0/+32
The display on the Huawei Ascend G7 is supplied by a TI TPS65132 regulator. The panel needs a driver in mainline first, but the TPS65132 is already supported in mainline by the tps65132 driver. Signed-off-by: Stephan Gerhold <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2021-06-10arm64: dts: qcom: msm8916-huawei-g7: Add sensorsStephan Gerhold1-0/+76
The Huawei Ascend G7 has 3 sensors, all supported by existing kernel drivers: 1. Kionix KX023-1025 accelerometer (kxcjk-1023) 2. Asahi Kasei AK09911 magnetometer (ak8975) 3. Avago APDS9930 proximity/light sensor (tsl2772) Add them to the huawei-g7 device tree. Signed-off-by: Stephan Gerhold <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2021-06-10arm64: dts: qcom: msm8916-huawei-g7: Add touchscreenStephan Gerhold1-1/+42
The Huawei Ascend G7 has a Synaptics "C199HW-006" touchscreen, supplied by pm8916_l17 and pm8916_l16. Add it to the device tree and reduce the maximum allowed voltage for pm8916_l16 to 1.8V since we really should not use more for an I/O supply. Signed-off-by: Stephan Gerhold <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2021-06-10arm64: dts: qcom: msm8916: Add device tree for Huawei Ascend G7Stephan Gerhold2-0/+280
The Huawei Ascend G7 is a smartphone from Huawei based on MSM8916. It's fairly similar to the other MSM8916 devices, the only notable exception are the "cd-gpios" for detecting if a SD card was inserted: It looks like Huawei forgot to re-route this to gpio38, so the correct GPIO seems to be gpio56 on this device. Note: The original firmware from Huawei can only boot 32-bit kernels. To boot arm64 kernels it is necessary to flash 64-bit TZ/HYP firmware with EDL, e.g. taken from the DragonBoard 410c. This works because Huawei forgot to set up (firmware) secure boot for some reason. Also note that Huawei no longer provides bootloader unlock codes. This can be bypassed by patching the bootloader from a custom HYP firmware, making it think the bootloader is unlocked. I use a modified version of qhypstub [1], that patches a single instruction in the Huawei bootloader. The device tree contains initial support for the Huawei Ascend G7 with: - UART (untested, probably available via some test points) - eMMC/SD card - Buttons - Notification LED (combination of 3 GPIO LEDs) - Vibrator - WiFi/Bluetooth (WCNSS) - USB [1]: https://github.com/msm8916-mainline/qhypstub Signed-off-by: Stephan Gerhold <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2021-06-10arm64: dts: qcom: sc7180-trogdor: Update flash freq to match realityStephen Boyd1-2/+1
This spi flash part is actually being clocked at 37.5MHz, not 25MHz, because of the way the clk driver is rounding up the rate that is requested to the nearest supported frequency. Let's update the frequency here, and remove the TODO because this is the fastest frequency we're going to be able to use here. Reviewed-by: Douglas Anderson <[email protected]> Cc: Douglas Anderson <[email protected]> Signed-off-by: Stephen Boyd <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2021-06-10arm64: dts: qcom: sc7180: Add wakeup delay for adau codecSrinivasa Rao Mandadapu1-0/+1
Add wakeup delay for fixing PoP noise during capture begin. Reviewed-by: Douglas Anderson <[email protected]> Signed-off-by: Judy Hsiao <[email protected]> Signed-off-by: Srinivasa Rao Mandadapu <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2021-06-10arm64: dts: qcom: sdm845: Remove cros-pd-update on ChezaStephen Boyd1-4/+0
This compatible string isn't present upstream. Let's drop the node as it isn't used. Reviewed-by: Douglas Anderson <[email protected]> Cc: Douglas Anderson <[email protected]> Signed-off-by: Stephen Boyd <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2021-06-10arm64: dts: qcom: sc7180: Remove cros-pd-update on TrogdorStephen Boyd1-4/+0
This compatible string isn't present upstream. Let's drop the node as it isn't used. Reviewed-by: Douglas Anderson <[email protected]> Cc: Douglas Anderson <[email protected]> Signed-off-by: Stephen Boyd <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2021-06-10arm64: dts: qcom: sc7180: Disable PON on TrogdorStephen Boyd1-1/+1
We don't use the PON module on Trogdor devices. Instead the reboot reason is sort of stored in the 'eventlog' and the bootloader figures out if the boot is abnormal and records that there. Disable the PON node and then drop the power key disabling because that's a child node that will no longer be enabled if the PON node is disabled. Reviewed-by: Douglas Anderson <[email protected]> Cc: Douglas Anderson <[email protected]> Signed-off-by: Stephen Boyd <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2021-06-10arm64: dts: qcom: sc7180: Modify SPI_CLK voltage level for trogdorWenchao Han1-0/+1
On coachz it could be observed that SPI_CLK voltage level was only 1.4V during active transfers because the drive strength was too weak. The line hadn't finished slewing up by the time we started driving it down again. Using a drive strength of 8 lets us achieve the correct voltage level of 1.8V. Though the worst problems were observed on coachz hardware, let's do this across the board for trogdor devices. Scoping other boards shows that this makes the clk line look nicer on them too and doesn't introduce any problems. Only the clk line is adjusted, not any data lines. Because SPI isn't a DDR protocol we only sample the data lines on either rising or falling edges, not both. That means the clk line needs to toggle twice as fast as data lines so having the higher drive strength is more important there. Signed-off-by: Wenchao Han <[email protected]> [dianders: Adjust author real name; adjust commit message] Signed-off-by: Douglas Anderson <[email protected]> Link: https://lore.kernel.org/r/20210510075253.1.Ib4c296d6ff9819f26bcaf91e8a08729cc203fed0@changeid Signed-off-by: Bjorn Andersson <[email protected]>
2021-06-10ARM: dts: stm32: fix stpmic node for stm32mp1 boardsAlexandre Torgue4-18/+6
On some STM32 MP15 boards, stpmic node is not correct which generates warnings running "make dtbs_check W=1" command. Issues are: -"regulator-active-discharge" is not a boolean but an uint32. -"regulator-over-current-protection" is not a valid entry for vref_ddr. -LDO4 has a fixed voltage (3v3) so min/max entries are not allowed. Signed-off-by: Alexandre Torgue <[email protected]>
2021-06-10ARM: dts: stm32: Rename spi-flash/mx66l51235l@N to flash@N on DHCOM SoMMarek Vasut2-2/+2
Fix the following dtbs_check warning: spi-flash@0: $nodename:0: 'spi-flash@0' does not match '^flash(@.*)?$' Signed-off-by: Marek Vasut <[email protected]> Cc: Alexandre Torgue <[email protected]> Cc: Patrice Chotard <[email protected]> Cc: Patrick Delaunay <[email protected]> Cc: [email protected] Cc: [email protected] To: [email protected] Signed-off-by: Alexandre Torgue <[email protected]>
2021-06-10ARM: dts: stm32: Rename eth@N to ethernet@N on DHCOM SoMMarek Vasut1-1/+1
Fix the following dtbs_check warning: eth@1,0: $nodename:0: 'eth@1,0' does not match '^ethernet(@.*)?$' Signed-off-by: Marek Vasut <[email protected]> Cc: Alexandre Torgue <[email protected]> Cc: Patrice Chotard <[email protected]> Cc: Patrick Delaunay <[email protected]> Cc: [email protected] Cc: [email protected] To: [email protected] Signed-off-by: Alexandre Torgue <[email protected]>
2021-06-10ARM: dts: stm32: Drop unused linux,wakeup from touchscreen node on DHCOM SoMMarek Vasut1-1/+0
Fix the following dtbs_check warning: touchscreen@38: 'linux,wakeup' does not match any of the regexes: 'pinctrl-[0-9]+' Signed-off-by: Marek Vasut <[email protected]> Cc: Alexandre Torgue <[email protected]> Cc: Patrice Chotard <[email protected]> Cc: Patrick Delaunay <[email protected]> Cc: [email protected] Cc: [email protected] To: [email protected] Signed-off-by: Alexandre Torgue <[email protected]>
2021-06-10ARM: dts: stm32: fix the Odyssey SoM eMMC VQMMC supplyGrzegorz Szymaszek1-1/+1
The Seeed SoM-STM32MP157C device tree had the eMMC’s (SDMMC2) VQMMC supply set to v3v3 (buck4), the same as the VMMC supply. That was incorrect, as on the SoM, the VQMMC supply is provided from vdd (buck3) instead. Signed-off-by: Grzegorz Szymaszek <[email protected]> Signed-off-by: Alexandre Torgue <[email protected]>
2021-06-10arm64: dts: renesas: r9a07g044: Add SYSC nodeLad Prabhakar1-0/+12
Add SYSC node to RZ/G2L (R9A07G044) SoC .dtsi. Signed-off-by: Lad Prabhakar <[email protected]> Reviewed-by: Biju Das <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Geert Uytterhoeven <[email protected]>
2021-06-10arm64: dts: renesas: Add initial device tree for RZ/G2L SMARC EVKLad Prabhakar3-0/+50
Add basic support for RZ/G2L SMARC EVK (based on R9A07G044L2): - memory - External input clock - SCIF Signed-off-by: Lad Prabhakar <[email protected]> Signed-off-by: Biju Das <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Geert Uytterhoeven <[email protected]>
2021-06-10arm64: dts: renesas: Add initial DTSI for RZ/G2{L,LC} SoC'sLad Prabhakar3-0/+158
Add initial DTSI for RZ/G2{L,LC} SoC's. File structure: r9a07g044.dtsi => RZ/G2L family SoC common parts r9a07g044l1.dtsi => RZ/G2L R9A07G044L1 SoC specific parts r9a07g044l2.dtsi => RZ/G2L R9A07G044L2 SoC specific parts Signed-off-by: Lad Prabhakar <[email protected]> Signed-off-by: Biju Das <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Geert Uytterhoeven <[email protected]>
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