diff options
| author | Lad Prabhakar <[email protected]> | 2021-06-09 17:37:17 +0100 |
|---|---|---|
| committer | Geert Uytterhoeven <[email protected]> | 2021-06-10 15:36:41 +0200 |
| commit | 42bbd003910906229cb1dc0eaa812d9cc59e4c77 (patch) | |
| tree | 0fc94012ab208d83ec66b95a2a7bc0792eb73770 | |
| parent | 690ea5d394eb370973ffcb9ecda6a1855fe87d01 (diff) | |
arm64: dts: renesas: r9a07g044: Add SYSC node
Add SYSC node to RZ/G2L (R9A07G044) SoC .dtsi.
Signed-off-by: Lad Prabhakar <[email protected]>
Reviewed-by: Biju Das <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Geert Uytterhoeven <[email protected]>
| -rw-r--r-- | arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi index 6a103a62eccb..734c8adeceba 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi @@ -99,6 +99,18 @@ #power-domain-cells = <0>; }; + sysc: system-controller@11020000 { + compatible = "renesas,r9a07g044-sysc"; + reg = <0 0x11020000 0 0x10000>; + interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "lpm_int", "ca55stbydone_int", + "cm33stbyr_int", "ca55_deny"; + status = "disabled"; + }; + gic: interrupt-controller@11900000 { compatible = "arm,gic-v3"; #interrupt-cells = <3>; |