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2019-02-06drm/amd/display: add seamless boot flag to streamAnthony Koo5-6/+75
[Why] If we determine the stream we are trying to commit matches HW, we want to try to optimize. [How] Try to acquire the HW resources that are already enabled and optimize. Also skip backend reprogramming Signed-off-by: Anthony Koo <[email protected]> Reviewed-by: Aric Cyr <[email protected]> Acked-by: Bhawanpreet Lakha <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-02-06drm/amd/display: add way to determine if link is activeAnthony Koo3-0/+10
[Why] Need to understand whether link is active aside from stream state. This could be used to check what links are enabled by GOP. [How] Store link_active state in link status and initialize it by checking if the DIG is enabled. Keep it updated on every link enable and disable Signed-off-by: Anthony Koo <[email protected]> Reviewed-by: Aric Cyr <[email protected]> Acked-by: Bhawanpreet Lakha <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-02-06drm/amd/display: refactor out programming of vupdate interruptAnthony Koo3-11/+48
[Why] More clearly isolate the code that is involved in programming of vupdate interrupt [How] Add function for programming of vupdate interrupt. Call it after timing is programmed. Signed-off-by: Anthony Koo <[email protected]> Reviewed-by: Aric Cyr <[email protected]> Acked-by: Bhawanpreet Lakha <[email protected]> Acked-by: Tony Cheng <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-02-06drm/amd/display: interface to check if timing can be seamlessAnthony Koo9-2/+154
[Why] Need to figure out whether a timing we want to commit matches something that GOP already programmed, in which case we can decide to some optimizations [How] 1. Add way to check for DIG FE 2. Add way to check for matching OTG timing 3. Add way to check for matching pixel clock (if possible) - Currently only support DP for pixel clock, since it is easy to calc Signed-off-by: Anthony Koo <[email protected]> Reviewed-by: Aric Cyr <[email protected]> Acked-by: Bhawanpreet Lakha <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-02-06drm/amd/display: 3.2.17mark mcgarrity1-1/+1
Signed-off-by: mark mcgarrity <[email protected]> Reviewed-by: Aric Cyr <[email protected]> Acked-by: Bhawanpreet Lakha <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-02-06drm/amd/display: PIP overlay corruptionMurton Liu2-2/+24
[Why] When moving mouse onto or off of pip plane, screen would flash briefly due to garbage negative pos values being programmed for cursor. Also, text flashes due to PIP flips taking too long. [How] When negative pos value seen, default to 0 and adjust by modifying cursor hotspot. For flip issue, only do post update when optimize required vs all the time. Signed-off-by: Murton Liu <[email protected]> Reviewed-by: Aric Cyr <[email protected]> Acked-by: Bhawanpreet Lakha <[email protected]> Acked-by: Sivapiriyan Kumarasamy <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-02-06drm/amd/display: link_rate_set should index into tableAnthony Koo1-34/+1
[Why] Current implementation that maps link_rate_set value to actual link rate is incorrect. [How] Fix this implementation, such that link_rate_set indexes into the supported_link_rate table. Signed-off-by: Anthony Koo <[email protected]> Reviewed-by: Harry Wentland <[email protected]> Acked-by: Aric Cyr <[email protected]> Acked-by: Bhawanpreet Lakha <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-02-06drm/amd/display: DC VM FixesEryk Brol4-16/+11
[Why] VM_helper needs to be intialized with the dc struct in order to fix an unallocated memory issue. System aperture settings should be initialized to 0 and guarded with a check to make sure vm_config is valid. [How] Allocate and free memory for vm_helper with other dc members. Check whether the vm_config valid bit is set before initializing aperture settings. Signed-off-by: Eryk Brol <[email protected]> Reviewed-by: Jun Lei <[email protected]> Acked-by: Bhawanpreet Lakha <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-02-06drm/amd/display: Disable Stutter for Stereo 3DWesley Chalmers3-10/+31
[WHY] Bandwidth calculation formulas currently do not take Stereo 3D + Stutter properly into account. Disable stutter feature when we detect a Stereo 3D mode as a temporary workaround. Signed-off-by: Wesley Chalmers <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Bhawanpreet Lakha <[email protected]> Acked-by: Martin Leung <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-02-06drm/amd/display: Calc vline position in dc.Yongqiang Sun5-20/+97
We need to calcualte vline position in DC for DCN. Signed-off-by: Yongqiang Sun <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Bhawanpreet Lakha <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-02-06drm/amd/display: Clear dc_sink after it gets releasedJerry (Fangzhi) Zuo1-1/+3
[Why] The dc_sink was released but the pointer on the aconnector was not cleared. [How] Clear it. Signed-off-by: Jerry (Fangzhi) Zuo <[email protected]> Reviewed-by: Nicholas Kazlauskas <[email protected]> Acked-by: Bhawanpreet Lakha <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-02-06drm/amd/display: Don't re-program planes for DPMS changesNicholas Kazlauskas1-1/+2
[Why] There are opt1c lock warnings and CRTC read timeouts when running the "igt@kms_plane@plane-position-hole-dpms-pipe-*" tests. These are caused by trying to reprogram planes that are not in the current context. DPMS off removes the stream from the context. In this case: new_crtc_state->active_changed = true new_crtc_state->mode_changed = false The planes are reprogrammed before the stream is removed from the context because stream_state->mode_changed = false. For DPMS adds the stream and planes back to the context: new_crtc_state->active_changed = true new_crtc_state->mode_changed = false The planes are also reprogrammed here before the stream is added to the context because stream_state->mode_changed = true. They were not previously in the current context so warnings occur here. [How] Set stream_state->mode_changed = true when new_crtc_state->active_changed = true too. This prevents reprogramming before the context is applied in DC. The programming will be done after the context is applied. Signed-off-by: Nicholas Kazlauskas <[email protected]> Reviewed-by: Sun peng Li <[email protected]> Acked-by: Bhawanpreet Lakha <[email protected]> Acked-by: Tony Cheng <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-02-06drm/amdgpu/display: fix compiler errors [-Werror,-Wparentheses-equality]Pratik Vishwakarma1-1/+1
Remove extraneous parentheses around the comparison to silence this warning Signed-off-by: Pratik Vishwakarma <[email protected]> Reviewed-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-02-06drm/i915: Just use icl+ definition for PLANE_WM blocks fieldVille Syrjälä2-9/+3
The unused bits on PLANE_WM & co. are hardwired to zero. So no need to worry about reading the extra bit on pre-icl. Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Reviewed-by: José Roberto de Souza <[email protected]>
2019-02-06drm/i915: Bump skl+ wm blocks to 11 bitsVille Syrjälä1-1/+1
On icl the plane watermark blocks field is 11 bits. Bump our define to match so that readout won't ignore the extra bit. We can safely do this for older platforms too since the unused bits are hardwired to zero. Cc: José Roberto de Souza <[email protected]> Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Reviewed-by: José Roberto de Souza <[email protected]>
2019-02-06drm/i915/pmu: Fix enable count array size and bounds checkingTvrtko Ursulin3-11/+22
Enable count array is supposed to have one counter for each possible engine sampler. As such, array sizing and bounds checking is not correct and would blow up the asserts if more samplers were added. No ill-effect in the current code base but lets fix it for correctness. At the same time tidy the assert for readability and robustness. v2: * One check per assert. (Chris Wilson) Signed-off-by: Tvrtko Ursulin <[email protected]> Fixes: b46a33e271ed ("drm/i915/pmu: Expose a PMU interface for perf queries") Reviewed-by: Chris Wilson <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-02-05drm/amd/display: Disconnect mpcc when changing tgNicholas Kazlauskas1-3/+4
[Why] This fixes an mpc programming error for the following sequence of atomic commits when pipe split is enabled: Commit 1: CRTC0 (plane 4, plane 3) Pipe 0: old_plane_state = A0, new_plane_state = A1, new_tg = T0 Pipe 1: old_plane_state = B0, new_plane_state = B1, new_tg = T0 Pipe 2: old_plane_state = A0, new_plane_state = A1, new_tg = T0 Pipe 3: old_plane_state = B0, new_plane_state = B1, new_tg = T0 Commit 2: CRTC0 (plane 3), CRTC1 (plane 2) Pipe 0: old_plane_state = A1, new_plane_state = A2, new_tg = T0 Pipe 1: old_plane_state = B1, new_plane_state = B2, new_tg = T1 Pipe 2: old_plane_state = A1, new_plane_state = NULL, new_tg = NULL Pipe 3: old_plane_state = B1, new_plane_state = NULL, new_tg = NULL In the second commit the assertion for mpcc in use is hit because mpcc disconnect never occurs for pipe 1. This is because the stream changes for pipe 1 and the opp_list is empty. This sequence occurs when running the "igt@kms_plane_multiple@atomic-pipe-A-tiling-none" test with two displays connected. [How] Expand the reset condition to include: "old_pipe_ctx->stream_res.tg != new_pipe_ctx->stream_res.tg" ...but only when the plane state is non-NULL for both old and new. Signed-off-by: Nicholas Kazlauskas <[email protected]> Reviewed-by: Dmytro Laktyushkin <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Bhawanpreet Lakha <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-02-05drm/amd/display: Apply fake sink back to MST sequenceJerry (Fangzhi) Zuo2-5/+6
[Why] It fixes the failure to create stream for sink in the scenario when hotplug SST and MST in sequence, and disconnect MST. [How] Add the fake sink back after the majority of MST rework is done. Signed-off-by: Jerry (Fangzhi) Zuo <[email protected]> Reviewed-by: Nicholas Kazlauskas <[email protected]> Acked-by: Bhawanpreet Lakha <[email protected]> Acked-by: Tony Cheng <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-02-05drm/amd/display: add a debug flag to force odm combineDmytro Laktyushkin1-0/+1
Adding a bit vector to allow forcing odm on specific otgs Signed-off-by: Dmytro Laktyushkin <[email protected]> Reviewed-by: Charlene Liu <[email protected]> Acked-by: Bhawanpreet Lakha <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-02-05drm/amd/display: store timing sync info in dc_stream_statusSu Sung Chung2-1/+21
in program_timing_sync, after all the pipes are grouped, store timing sync info in dc_stream_status Signed-off-by: Su Sung Chung <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Bhawanpreet Lakha <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-02-05drm/amd/display: Modify ABM 2.2 Max ReductionJosip Pavic1-2/+2
[Why] Reduced backlight for ABM 2.2 at levels 1 and 2 is desired for power savings. [How] Reduce the max reduction parameters for ABM 2.2 Signed-off-by: Josip Pavic <[email protected]> Reviewed-by: Josip Pavic <[email protected]> Acked-by: Bhawanpreet Lakha <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-02-05drm/amd/display: pass vline_config parameter by reference.Yongqiang Sun4-8/+8
Signed-off-by: Yongqiang Sun <[email protected]> Reviewed-by: Aric Cyr <[email protected]> Acked-by: Bhawanpreet Lakha <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-02-05drm/amd/display: add gpio lock/unlockChiawen Huang6-25/+81
[Why] When querying HPD via GPIO flow, it will create a new gpio object then free in the end of query. There is a irql issue for HPD querying at ISR level. [How] Therefore, creating the HPD gpio object in dc_link and set it as unlcok in default. 1. reducing unnecessary malloc/free when HPD querying. 2. reducing init GPIO flow. 3. add lock/unlock to prevent multi gpio service running. Signed-off-by: Chiawen Huang <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Bhawanpreet Lakha <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-02-05drm/amd/display: 3.2.16Steven Chiu1-1/+1
Signed-off-by: Steven Chiu <[email protected]> Reviewed-by: Aric Cyr <[email protected]> Acked-by: Bhawanpreet Lakha <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-02-05drm/amd/display: determine if a pipe is synced by plane stateWenjing Liu1-4/+4
[why] is_blanked is not a general indicator of if a pipe is synced for all asics. plane state is more accurate and applicable for all asics. [how] Remove is_blanked call and add checking plane_state against NULL instead. Signed-off-by: Wenjing Liu <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Bhawanpreet Lakha <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-02-05drm/amd/display: DGAM enabled for HDRKrunoslav Kovac1-37/+52
[Why] On HW that doesn't have input LUT, we may combine degamma with OS ramp Problem here is that it assumes DGAM is inverse of PQ or SRGB. It doesn't handle linear case, it would default to sRGB and always enable DGAM.. [How] Add handling for linear case. Also check for null ramp and instead of blowing up, assume it's identity. Signed-off-by: Krunoslav Kovac <[email protected]> Reviewed-by: Anthony Koo <[email protected]> Acked-by: Bhawanpreet Lakha <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-02-05drm/amd/display: Check that vrefresh is in freesync rangeIlya Bakoulin1-5/+5
[Why] Setting monitor refresh rate below freesync range would cause the monitor to go blank indefinitely with freesync enabled [How] Set vrr_supported and ignore_msa_timing_param according to whether the refresh rate is above or below the minimum freesync frequency. Signed-off-by: Ilya Bakoulin <[email protected]> Reviewed-by: Nicholas Kazlauskas <[email protected]> Acked-by: Bhawanpreet Lakha <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-02-05drm/amd/display: dmcu is blocking due to wrong disable ABM commandPaul Hsieh1-2/+2
[Why] Second screen to clone/extend mode, driver will send ABM pipe command to DMCU. Change mode from clone/extend to second screen only, driver send ABM level command to disable ABM but this command will not clear ABM pipe data. At this time, change second screen to PC screen only, driver will send first command "ABM_LEVEL", it will turn on ABM with incorrect ABM pile so that DMCU is blocking. [How] When driver try to disable ABM, change command from "ABM LEVEL" to "ABM PIPE" so that it will clear ABM pile data. Signed-off-by: Paul Hsieh <[email protected]> Reviewed-by: Charlene Liu <[email protected]> Acked-by: Bhawanpreet Lakha <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-02-05drm/amd/display: fix issue with DC brightness low with VBAnthony Koo1-10/+24
[Why] The problem is that we accidentally stopped loading some of the IRAM bytes used for the backlight ramping mechanism. This happened when we started reserving some region of IRAM as DMCU FW write only. [How] This change will define a start+end region for the IRAM read only region. So the parameters needed for the backlight operation will be loaded since it will be defined outside of the read only region. Signed-off-by: Anthony Koo <[email protected]> Reviewed-by: Aric Cyr <[email protected]> Acked-by: Bhawanpreet Lakha <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-02-05drm/amd/display: Add monitor patch for backlight offXiaodong Yan2-0/+5
[Why] Different panel need different time from backlight disable to end of valid video data, if the time is too short, panel will flash when dpms off [How] Add monitor patch to control the time from backlight disable to end of valid video data, Signed-off-by: Xiaodong Yan <[email protected]> Reviewed-by: Wenjing Liu <[email protected]> Acked-by: Bhawanpreet Lakha <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-02-05drm/amd/display: Remove FreeSync timing changed debug outputNicholas Kazlauskas1-6/+0
[Why] This provides little debug value and creates a lot of dmesg noise. [How] Remove it. Signed-off-by: Nicholas Kazlauskas <[email protected]> Reviewed-by: David Francis <[email protected]> Acked-by: Bhawanpreet Lakha <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-02-05drm/amd/display: Initialize stream_update to zeroNicholas Kazlauskas1-1/+2
[Why] The stream_update struct is left unitialized but DC will access its fields. This usually results in global state validation occur during any atomic commit with state->allow_modeset = true. [How] Initialize the struct to zero for every stream we check. Signed-off-by: Nicholas Kazlauskas <[email protected]> Reviewed-by: David Francis <[email protected]> Acked-by: Bhawanpreet Lakha <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-02-05drm/amd/display: Reformat dm_determine_update_type_for_commitNicholas Kazlauskas1-61/+65
[Why] The indenting for this function is a few levels too deep and can be simplified a fair bit. This patch is in preparation for functional changes that fix update type determination to occur less frequently and more accurately. [How] Place checks early and exit/continue when possible. This isn't a functional change. Signed-off-by: Nicholas Kazlauskas <[email protected]> Reviewed-by: David Francis <[email protected]> Acked-by: Bhawanpreet Lakha <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-02-05drm/amd/display: Use the right surface for flip and FreeSyncNicholas Kazlauskas1-13/+4
[Why] We were always passing the first surface on the stream status for flip updates when we should be using the surface associated with the plane. [How] Use the dc_plane_state from the plane that's being updated. FreeSync should also only keep track of updates from the primary plane, so the check needed to be updated. The acrtc->stream state doesn't need to be checked for NULL before updating FreeSync either since there needs to be a stream to be inside this function as a prerequisite. Signed-off-by: Nicholas Kazlauskas <[email protected]> Reviewed-by: David Francis <[email protected]> Acked-by: Bhawanpreet Lakha <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-02-05drm/amd/display: Apply all surface updates onto surfacesNicholas Kazlauskas2-17/+96
[Why] Most surface updates weren't propagated onto the surface during dc_commit_updates_for_stream. This makes it more difficult for DC to determine the actual surface update type required. [How] Use copy_surface_update_to_plane to propagate the changes. The FreeSync surface timing information update for BTR has been moved out of amdgpu_dm.c into this function as well. Signed-off-by: Nicholas Kazlauskas <[email protected]> Reviewed-by: Sun peng Li <[email protected]> Acked-by: Bhawanpreet Lakha <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-02-05drm/amd/display: Use udelay when waiting between aux retriesJohn Barberiz1-1/+1
[Why] "IRQ_HPD Pulse Length Test" DP compliance test fails. Test complains that certain DPCD registers are not read within 100 ms. [How] msleep is inaccurate for small values. Used udelay instead for accuracy. Signed-off-by: John Barberiz <[email protected]> Reviewed-by: Wenjing Liu <[email protected]> Acked-by: Bhawanpreet Lakha <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-02-05drm/amdgpu: cleanup VM dw estimation a bitChristian König1-8/+8
No functional change. Signed-off-by: Christian König <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-02-05drm/amdgpu: fix waiting for BO moves with CPU based PD/PT updatesChristian König1-1/+6
Otherwise we open up the possibility to use uninitialized memory. Signed-off-by: Christian König <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-02-05drm/amd/display: Use context parameters to enable FBCShirish S1-1/+1
[What] FBC fails to get enabled when switched between LINEAR(console/VT) and non-LINEAR(GUI) based rendering due to default value of tiling info stored in the current_state which is used for deciding whether or not to turn FBC on or off. [How] Use context structure's tiling information which is coherant with the screen updates. Signed-off-by: Shirish S <[email protected]> Reviewed-by: Roman Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-02-05drm/amd/display: Don't re-enable CRC when CONFIG_DEBUG_FS isn't definedNicholas Kazlauskas1-0/+2
[Why] When CONFIG_DEBUG_FS isn't defined then amdgpu_dm_crtc_set_crc_source is NULL. This causes a compilation error since it's being called unconditionally. [How] Guard the call based on CONFIG_DEBUG_FS - CRC capture isn't supported without this. Cc: Leo Li <[email protected]> Cc: Harry Wentland <[email protected]> Fixes: 43a6a02eb355 ("drm/amd/display: Re-enable CRC capture following modeset") Signed-off-by: Nicholas Kazlauskas <[email protected]> Reviewed-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-02-05drm/amdgpu: add a workaround for GDS ordered append hangs with compute queuesMarek Olšák6-6/+84
I'm not increasing the DRM version because GDS isn't totally without bugs yet. v2: update emit_ib_size Signed-off-by: Marek Olšák <[email protected]> Acked-by: Christian König <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-02-05drm/amdgpu: Add AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIESAndrey Grodzovsky3-2/+15
New chunk for dependency on start of job's execution instead on the end. This is used for GPU deadlock prevention when userspace uses mid-IB fences to wait for mid-IB work on other rings. v2: Fix typo in AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES v3: Bump KMS version v4: put old fence AFTER acquiring the scheduled fence. Signed-off-by: Andrey Grodzovsky <[email protected]> Suggested-by: Christian Koenig <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-02-05drm/amd/powerplay: update soc boot and max level on vega10Kenneth Feng1-0/+7
update soc boot and max level,then uclk isn't stuck at minimum. Bug: https://bugs.freedesktop.org/show_bug.cgi?id=109462 Signed-off-by: Kenneth Feng <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-02-05drm/amd/display: Use memset to initialize variables in fill_plane_dcc_attributesNathan Chancellor1-2/+5
Clang warns: drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:2314:38: warning: suggest braces around initialization of subobject [-Wmissing-braces] struct dc_surface_dcc_cap output = {0}; ^ {} Previous efforts to fix this type of warning by adding or removing braces have been met with some pushback in favor of using memset [1][2]. Do that here, mirroring commit 05794eff1aa6 ("drm/amdgpu/gmc: fix compiler errors [-Werror,-Wmissing-braces] (V2)") in this tree. [1]: https://lore.kernel.org/lkml/[email protected]/ [2]: https://lore.kernel.org/lkml/[email protected]/ Fixes: 7df7e505e82a ("drm/amd/display: Set requested plane state DCC params for GFX9") Signed-off-by: Nathan Chancellor <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-02-05drm/amd/display: Use memset to initialize variables in ↵Nathan Chancellor1-2/+5
amdgpu_dm_atomic_commit_tail Clang warns: drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:5089:60: warning: suggest braces around initialization of subobject [-Wmissing-braces] struct dc_surface_update dummy_updates[MAX_SURFACES] = { 0 }; ^ {} Previous efforts to fix this type of warning by adding or removing braces have been met with some pushback in favor of using memset [1][2]. Do that here, mirroring commit 05794eff1aa6 ("drm/amdgpu/gmc: fix compiler errors [-Werror,-Wmissing-braces] (V2)") in this tree. [1]: https://lore.kernel.org/lkml/[email protected]/ [2]: https://lore.kernel.org/lkml/[email protected]/ Fixes: 02d6a6fcdf68 ("drm/amd/display: Simplify underscan and ABM commit") Signed-off-by: Nathan Chancellor <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-02-05drm/amd/display: Use memset to initialize variable in ↵Nathan Chancellor1-1/+3
wait_for_training_aux_rd_interval Clang warns: drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc_link_dp.c:50:57: warning: suggest braces around initialization of subobject [-Wmissing-braces] union training_aux_rd_interval training_rd_interval = {0}; ^ {} 1 warning generated. Previous efforts to fix this type of warning by adding or removing braces have been met with some pushback in favor of using memset [1][2]. Do that here, mirroring commit 05794eff1aa6 ("drm/amdgpu/gmc: fix compiler errors [-Werror,-Wmissing-braces] (V2)") in this tree. [1]: https://lore.kernel.org/lkml/[email protected]/ [2]: https://lore.kernel.org/lkml/[email protected]/ Fixes: 3cec41769d21 ("drm/amd/display: Fix use of uninitialized union") Signed-off-by: Nathan Chancellor <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-02-05drm/amd/amdgpu: fix spelling mistake "matech" -> "match"Colin Ian King1-1/+1
There is a spelling mistake in a dev_err message. Fix it. Signed-off-by: Colin Ian King <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-02-05drm/i915: W/A for underruns with WM1+ disabled on iclVille Syrjälä2-0/+7
Disabling WM1+ on ICL causes tons of underruns with linear/X-tiled framebuffers. We can avoid this by flipping on a chicken bit affecting the way the hw fill the FIFO. This may not be the final solution but should hopefully avoid some underruns in the meantime. v2: Apparently PIPE_CHICKEN is icl+ only Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Reviewed-by: Matt Roper <[email protected]>
2019-02-05drm/i915: Setup PIPE_CHICKEN for fastsets tooVille Syrjälä1-0/+3
Configure PIPE_CHICKEN during intel_update_pipe_config() to make sure we have our chickens in a row with fastboot too. v2: Apparently PIPE_CHICKEN is icl+ only Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Reviewed-by: Matt Roper <[email protected]>
2019-02-05drm/i915: Extract icl_set_pipe_chicken()Ville Syrjälä1-11/+20
We need configure PIPE_CHICKEN during fastboot as well. Let's extract it to a helper. v2: Apparently PIPE_CHICKEN is icl+ only Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Reviewed-by: Matt Roper <[email protected]>
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