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2022-12-15drm/amd/pm: enable GPO dynamic control support for SMU13.0.7Evan Quan1-0/+2
To better support UMD pstate profilings, the GPO feature needs to be switched on/off accordingly. Signed-off-by: Evan Quan <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Cc: [email protected] # 6.0.x
2022-12-15drm/amd/pm: enable GPO dynamic control support for SMU13.0.0Evan Quan4-1/+22
To better support UMD pstate profilings, the GPO feature needs to be switched on/off accordingly. Signed-off-by: Evan Quan <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Cc: [email protected] # 6.0.x
2022-12-14drm/amdgpu: revert "generally allow over-commit during BO allocation"Christian König2-4/+18
This reverts commit f9d00a4a8dc8fff951c97b3213f90d6bc7a72175. This causes problem for KFD because when we overcommit we accidentially bind the BO to GTT for moving it into VRAM. We also need to make sure that this is done only as fallback after trying to evict first. Signed-off-by: Christian König <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-12-14drm/amdgpu: Remove unnecessary domain argumentLuben Tuikov4-14/+6
Remove the "domain" argument to amdgpu_bo_create_kernel_at() since this function takes an "offset" argument which is the offset off of VRAM, and as such allocation always takes place in VRAM. Thus, the "domain" argument is unnecessary. Cc: Alex Deucher <[email protected]> Cc: Christian König <[email protected]> Cc: AMD Graphics <[email protected]> Signed-off-by: Luben Tuikov <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-12-14drm/amdgpu: Fix size validation for non-exclusive domains (v4)Luben Tuikov1-11/+8
Fix amdgpu_bo_validate_size() to check whether the TTM domain manager for the requested memory exists, else we get a kernel oops when dereferencing "man". v2: Make the patch standalone, i.e. not dependent on local patches. v3: Preserve old behaviour and just check that the manager pointer is not NULL. v4: Complain if GTT domain requested and it is uninitialized--most likely a bug. Cc: Alex Deucher <[email protected]> Cc: Christian König <[email protected]> Cc: AMD Graphics <[email protected]> Signed-off-by: Luben Tuikov <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-12-14drm/amdgpu: Check if fru_addr is not NULL (v2)Luben Tuikov1-2/+4
Always check if fru_addr is not NULL. This commit also fixes a "smatch" warning. v2: Add a Fixes tag. Cc: Alex Deucher <[email protected]> Cc: Dan Carpenter <[email protected]> Cc: kernel test robot <[email protected]> Cc: AMD Graphics <[email protected]> Fixes: afbe5d1e4bd7c7 ("drm/amdgpu: Bug-fix: Reading I2C FRU data on newer ASICs") Signed-off-by: Luben Tuikov <[email protected]> Reviewed-by: Kent Russell <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-12-14drm/amdgpu: rework reserved VMID handlingChristian König3-30/+24
Instead of reserving a VMID for a single process allow that many processes use the reserved ID. This allows for proper isolation between the processes. Signed-off-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-12-14drm/amdgpu: stop waiting for the VM during unreserveChristian König1-16/+0
This is completely pointless since the VMID always stays allocated until the VM is idle. Signed-off-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-12-14drm/amdgpu: cleanup SPM support a bitChristian König3-4/+7
This should probably not access job->vm and also emit the SPM switch under the conditional execute. Signed-off-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-12-14drm/amdgpu: fix GDS/GWS/OA switch handlingChristian König3-43/+54
Bas pointed out that this isn't working as expected and could cause crashes. Fix the handling by storing the marker that a switch is needed inside the job instead. Reported-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-12-14drm/amd/pm: add missing SMU13.0.7 mm_dpm feature mappingEvan Quan1-0/+2
Without this, the pp_dpm_vclk and pp_dpm_dclk outputs are not with correct data. Signed-off-by: Evan Quan <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Cc: [email protected] # 6.0.x
2022-12-14drm/amd/pm: add missing SMU13.0.0 mm_dpm feature mappingEvan Quan1-0/+2
Without this, the pp_dpm_vclk and pp_dpm_dclk outputs are not with correct data. Signed-off-by: Evan Quan <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Cc: [email protected] # 6.0.x
2022-12-14drm/amdgpu: Add notifier lock for KFD userptrsFelix Kuehling6-91/+172
Add a per-process MMU notifier lock for processing notifiers from userptrs. Use that lock to properly synchronize page table updates with MMU notifiers. Signed-off-by: Felix Kuehling <[email protected]> Reviewed-by: Xiaogang Chen<[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-12-14drm/amd/display: Add DCN314 display SG SupportYifan Zhang1-0/+1
Add display SG support for DCN 3.1.4. Signed-off-by: Yifan Zhang <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Cc: [email protected]
2022-12-14drm/amdgpu: WARN when freeing kernel memory during suspendChristian König1-0/+2
When buffers are freed during suspend there is no guarantee that they can be re-allocated during resume. The PSP subsystem seems to be quite buggy regarding this, so add a WARN_ON() to point out those bugs. Signed-off-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Tested-by: Guilherme G. Piccoli <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-12-14drm/amdgpu: fixx NULL pointer deref in gmc_v9_0_get_vm_pteChristian König1-1/+3
We not only need to make sure that we have a BO, but also that the BO has some backing store. Fixes: d1a372af1c3d ("drm/amdgpu: Set MTYPE in PTE based on BO flags") Signed-off-by: Christian König <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Luben Tuikov <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-12-13drm/amdgpu: Add an extra evict_resource call during device_suspend.Shikang Fan1-0/+5
- evict_resource is taking too long causing sriov full access mode timeout. So, add an extra evict_resource in the beginning as an early evict. Signed-off-by: Shikang Fan <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-12-09drm/amdgpu: handle polaris10/11 overlap asics (v2)Alex Deucher1-2/+11
Some special polaris 10 chips overlap with the polaris11 DID range. Handle this properly in the driver. v2: use local flags for other function calls. Acked-by: Luben Tuikov <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Cc: [email protected]
2022-12-09drm/amdgpu: make display pinning more flexible (v2)Alex Deucher1-1/+2
Only apply the static threshold for Stoney and Carrizo. This hardware has certain requirements that don't allow mixing of GTT and VRAM. Newer asics do not have these requirements so we should be able to be more flexible with where buffers end up. Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/2270 Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/2291 Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/2255 Acked-by: Luben Tuikov <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Cc: [email protected]
2022-12-09drm/amd/display: Fix spelling mistake: "dram_clk_chanage" -> "dram_clk_change"Colin Ian King7-20/+20
There is a spelling mistake in the struct field dram_clk_chanage. Fix it. Signed-off-by: Colin Ian King <[email protected]> Signed-off-by: Hamza Mahfooz <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-12-09Merge tag 'amd-drm-next-6.2-2022-12-07' of ↵Dave Airlie37-94/+156
https://gitlab.freedesktop.org/agd5f/linux into drm-next amd-drm-next-6.2-2022-12-07: amdgpu: - DSC fixes for DCN 2.1 - HDMI PCON fixes - PSR fixes - DC DML fixes - Properly throttle on BO allocation - GFX 11.0.4 fixes - MMHUB fix - Make some functions static Signed-off-by: Dave Airlie <[email protected]> From: Alex Deucher <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2022-12-09Merge tag 'amd-drm-next-6.2-2022-12-02' of ↵Dave Airlie67-364/+1697
https://gitlab.freedesktop.org/agd5f/linux into drm-next amd-drm-next-6.2-2022-12-02: amdgpu: - Fix CPU stalls when allocating large amounts of system memory - SR-IOV fixes - BACO fixes - Enable GC 11.0.4 - Enable PSP 13.0.11 - Enable SMU 13.0.11 - Enable NBIO 7.7.1 - Fix reported VCN capabilities for RDNA2 - Misc cleanups - PCI ref count fixes - DCN DPIA fixes - DCN 3.2.x fixes - Documentation updates - GC 11.x fixes - VCN RAS fixes - APU fix for passthrough - PSR fixes - GFX preemption support for gfx9 - SDMA fix for S0ix amdkfd: - Enable KFD support for GC 11.0.4 - Misc cleanups - Fix memory leak Signed-off-by: Dave Airlie <[email protected]> From: Alex Deucher <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2022-12-09Merge tag 'drm-misc-next-fixes-2022-12-08' of ↵Dave Airlie4-35/+16
git://anongit.freedesktop.org/drm/drm-misc into drm-next Some deferred-io and damage worker reworks revert and make a fb function static Signed-off-by: Dave Airlie <[email protected]> From: Maxime Ripard <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/20221208084040.yw4zavsjd25qsltf@houat
2022-12-09Merge tag 'drm-intel-next-fixes-2022-12-01' of ↵Dave Airlie14-65/+113
git://anongit.freedesktop.org/drm/drm-intel into drm-next - Multi-cast register fix (Matt) - Fix workarounds on gen2-3 (Tvrtko) - Bigjoiner fix (Ville) - Make Guc default_list a const data (Jani) - Acquire forcewake before uncore read (Umesh) - Selftest fix (Umesh) - HuC related fixes (Daniele) - Fix some incorrect return values (Janusz) - Fix a memory leak in bios related code (Xia) - Fix VBT send packet port selection (Mikko) - DG2's DMC fix bump for Register noclaims and few restore (Gustavo) Signed-off-by: Dave Airlie <[email protected]> From: Rodrigo Vivi <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2022-12-06drm/amdgpu: fix mmhub register base coding errorYang Wang5-5/+5
fix MMHUB register base coding error. Fixes: ec6837591f992 ("drm/amdgpu/gmc10: program the smallK fragment size") Signed-off-by: Yang Wang <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Cc: [email protected]
2022-12-06drm/amdgpu: add tmz support for GC IP v11.0.4Tim Huang1-0/+1
Add tmz support for GC 11.0.4. Signed-off-by: Tim Huang <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-12-06drm/amdgpu: enable GFX Clock Gating control for GC IP v11.0.4Tim Huang1-0/+1
Enable GFX IP v11.0.4 CG gate/ungate control. Signed-off-by: Tim Huang <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-12-06drm/amdgpu: enable GFX Power Gating for GC IP v11.0.4Tim Huang1-0/+2
Enable GFX Power Gating control for GC IP v11.0.4. Signed-off-by: Tim Huang <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-12-06drm/amdgpu: enable GFX IP v11.0.4 CG supportTim Huang1-1/+17
Add CG support for GFX/MC/HDP/ATHUB/IH/BIF. Signed-off-by: Tim Huang <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-12-06drm/amdgpu: Make amdgpu_ring_mux functions as staticJiadong Zhu1-5/+3
lkp robot reported missing-prototypes and unused-but-set-variable warnings on some functions of amdgpu_mcbp_mux.c. Make them static and remove the unused variable. Reported-by: kernel test robot <[email protected]> Signed-off-by: Jiadong Zhu <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-12-06drm/amdgpu: generally allow over-commit during BO allocationChristian König2-18/+4
We already fallback to a dummy BO with no backing store when we allocate GDS,GWS and OA resources and to GTT when we allocate VRAM. Drop all those workarounds and generalize this for GTT as well. This fixes ENOMEM issues with runaway applications which try to allocate/free GTT in a loop and are otherwise only limited by the CPU speed. The CS will wait for the cleanup of freed up BOs to satisfy the various domain specific limits and so effectively throttle those buggy applications down to a sane allocation behavior again. Signed-off-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Arunpravin Paneer Selvam <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-12-06drm/amd/display: fix array index out of bound error in DCN32 DMLAurabindo Pillai1-1/+1
[Why&How] LinkCapacitySupport array is indexed with the number of voltage states and not the number of max DPPs. Fix the error by changing the array declaration to use the correct (larger) array size of total number of voltage states. Signed-off-by: Aurabindo Pillai <[email protected]> Reviewed-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-12-06drm/amd/display: 3.2.215Aric Cyr1-1/+1
Acked-by: Stylon Wang <[email protected]> Signed-off-by: Aric Cyr <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-12-06drm/amd/display: set optimized required for comp buf changesDillon Varone1-2/+5
[Description] When compressed buffer allocation changes, optimized required flag should be set to trigger an update in optimize bandwidth. Reviewed-by: Aric Cyr <[email protected]> Acked-by: Stylon Wang <[email protected]> Signed-off-by: Dillon Varone <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-12-06drm/amd/display: Add debug option to skip PSR CRTC disableNicholas Kazlauskas3-1/+3
[Why] It's currently tied to Z10 support, and is required for Z10, but we can still support Z10 display off without PSR. We currently need to skip the PSR CRTC disable to prevent stuttering and underflow from occuring during PSR-SU. [How] Add a debug option to allow specifying this separately. Reviewed-by: Robin Chen <[email protected]> Acked-by: Stylon Wang <[email protected]> Signed-off-by: Nicholas Kazlauskas <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-12-06drm/amd/display: correct DML calc error of UrgentLatencyZhongwei3-3/+3
[Why] The input UrgentLatency in CalculateUrgentBurstFactor of prefect check is wrong. [How] Correct to the correct one to keep same as HW formula Reviewed-by: Charlene Liu <[email protected]> Acked-by: Stylon Wang <[email protected]> Signed-off-by: Zhongwei <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-12-06drm/amd/display: correct static_screen_event_maskCharlene Liu7-7/+81
[why] HW register bit define changed. Reviewed-by: Zhan Liu <[email protected]> Reviewed-by: Dmytro Laktyushkin <[email protected]> Acked-by: Stylon Wang <[email protected]> Signed-off-by: Charlene Liu <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-12-06drm/amd/display: Ensure commit_streams returns the DC return codeAlvin Lee1-1/+1
[Description] - Ensure dc_commit_streams returns the correct return code so any failures can be handled properly in DM layer - If set timings fail and we have to remove MPO planes, do so unconditionally but make sure to mark for removal so we report the VSYNC and prevent timeout - Failure to remove MPO plane results in set timings failure due to lack of resources Reviewed-by: Aric Cyr <[email protected]> Acked-by: Stylon Wang <[email protected]> Signed-off-by: Alvin Lee <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-12-06drm/amd/display: read invalid ddc pin status cause engine busyPaul Hsieh1-2/+2
[Why] There is no DDC_6 pin on new asic cause the mapping table is incorrect. When app try to access DDC_VGA port, driver read an invalid ddc pin status and report engine busy. [How] Add dummy DDC_6 pin to align gpio structure. Reviewed-by: Alvin Lee <[email protected]> Acked-by: Stylon Wang <[email protected]> Signed-off-by: Paul Hsieh <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-12-06drm/amd/display: Bypass DET swath fill check for max clocksDillon Varone1-1/+2
[Description] If validating for max voltage level (therefore max clocks) always pass over the DET swath fill latency hiding check. Reviewed-by: Alvin Lee <[email protected]> Acked-by: Stylon Wang <[email protected]> Signed-off-by: Dillon Varone <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-12-06drm/amd/display: Disable uclk pstate for subvp pipesDillon Varone1-5/+5
[Description] When subvp is in use, main pipes should block unintended natural uclk pstate changes to prevent disruption to the state machine. Reviewed-by: Alvin Lee <[email protected]> Acked-by: Stylon Wang <[email protected]> Signed-off-by: Dillon Varone <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-12-06drm/amd/display: Fix DCN2.1 default DSC clocksMichael Strauss1-3/+3
[WHY] Low dscclk in high vlevels blocks some DSC modes. [HOW] Update dscclk to 1/3 of dispclk. Reviewed-by: Charlene Liu <[email protected]> Acked-by: Stylon Wang <[email protected]> Signed-off-by: Michael Strauss <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-12-06drm/amd/display: Enable dp_hdmi21_pcon supportDavid Galiffi3-0/+6
[Why] It is not enabled for DCN3.0.1, 3.0.2, 3.0.3. [How] Add `dc->caps.dp_hdmi21_pcon_support = true` to these DCN versions. Reviewed-by: Martin Leung <[email protected]> Acked-by: Stylon Wang <[email protected]> Signed-off-by: David Galiffi <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-12-06drm/amd/display: prevent seamless boot on displays that don't have the ↵Dmytro Laktyushkin1-0/+3
preferred dig Seamless boot requires VBIOS to select dig matching to link order wise. A significant amount of dal logic makes assumption we are using preferred dig for eDP and if this isn't the case then seamless boot is not supported. Reviewed-by: Martin Leung <[email protected]> Acked-by: Stylon Wang <[email protected]> Signed-off-by: Dmytro Laktyushkin <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-12-06drm/amd/display: trigger timing sync only if TG is runningAurabindo Pillai1-0/+6
[Why&How] If the timing generator isnt running, it does not make sense to trigger a sync on the corresponding OTG. Check this condition before starting. Otherwise, this will cause error like: *ERROR* GSL: Timeout on reset trigger! Fixes: dc55b106ad477c ("drm/amd/display: Disable phantom OTG after enable for plane disable") Reviewed-by: Rodrigo Siqueira <[email protected]> Reviewed-by: Alvin Lee <[email protected]> Acked-by: Stylon Wang <[email protected]> Signed-off-by: Aurabindo Pillai <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-12-06drm/amd/display: Remove DTB DTO on CLK updateChris Park2-38/+1
[Why] DTB DTO is programmed more correctly during link enable. Programming them on CLK update which may arrive frequently and sporadically per flip throws off DTB DTO. [How] Remove DTB DTO programming on clock update. Reviewed-by: Alvin Lee <[email protected]> Acked-by: Jasdeep Dhillon <[email protected]> Signed-off-by: Chris Park <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-12-02drm/amdgpu: expand on GPUVM documentationAlex Deucher1-10/+31
Expand the GPUVM documentation to better describe the hardware functionality and use cases it serves. v2: Fixed a couple of spelling mistakes. Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Luben Tuikov <[email protected]> Reviewed-by: Luben Tuikov <[email protected]>
2022-12-02drm/amdgpu: add GART, GPUVM, and GTT to glossaryAlex Deucher1-0/+23
Add definitions to clarify GPU virtual memory. v2: clarify the terms a bit more Reviewed-by: Christian König <[email protected]> Reviewed-by: Luben Tuikov <[email protected]> Suggested-by: Peter Maucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2022-12-02drm/amdgpu/sdma_v4_0: turn off SDMA ring buffer in the s2idle suspendPrike Liang1-9/+15
In the SDMA s0ix save process requires to turn off SDMA ring buffer for avoiding the SDMA in-flight request, otherwise will suffer from SDMA page fault which causes by page request from in-flight SDMA ring accessing at SDMA restore phase. Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2248 Cc: [email protected] # 6.0,5.15+ Fixes: f8f4e2a51834 ("drm/amdgpu: skipping SDMA hw_init and hw_fini for S0ix.") Signed-off-by: Prike Liang <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Tested-by: Mario Limonciello <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-12-02drm/amdgpu: MCBP based on DRM scheduler (v9)Jiadong.Zhu8-43/+422
Trigger Mid-Command Buffer Preemption according to the priority of the software rings and the hw fence signalling condition. The muxer saves the locations of the indirect buffer frames from the software ring together with the fence sequence number in its fifo queue, and pops out those records when the fences are signalled. The locations are used to resubmit packages in preemption scenarios by coping the chunks from the software ring. v2: Update comment style. v3: Fix conflict caused by previous modifications. v4: Remove unnecessary prints. v5: Fix corner cases for resubmission cases. v6: Refactor functions for resubmission, calling fence_process in irq handler. v7: Solve conflict for removing amdgpu_sw_ring.c. v8: Add time threshold to judge if preemption request is needed. v9: Correct comment spelling. Set fence emit timestamp before rsu assignment. Cc: Christian Koenig <[email protected]> Cc: Luben Tuikov <[email protected]> Cc: Andrey Grodzovsky <[email protected]> Cc: Michel Dänzer <[email protected]> Signed-off-by: Jiadong.Zhu <[email protected]> Acked-by: Luben Tuikov <[email protected]> Acked-by: Huang Rui <[email protected]> Acked-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
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