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2024-05-16Merge branches 'clk-counted', 'clk-imx', 'clk-amlogic', 'clk-binding' and ↵Stephen Boyd41-63/+1037
'clk-rockchip' into clk-next * clk-counted: clk: bcm: rpi: Assign ->num before accessing ->hws clk: bcm: dvp: Assign ->num before accessing ->hws * clk-imx: clk: imx: imx8mp: Convert to platform remove callback returning void clk: imx: imx8mp: Switch to RUNTIME_PM_OPS() clk: imx: add i.MX95 BLK CTL clk driver dt-bindings: clock: support i.MX95 Display Master CSR module dt-bindings: clock: support i.MX95 BLK CTL module dt-bindings: clock: add i.MX95 clock header clk: imx: imx8mp: Add pm_runtime support for power saving * clk-amlogic: clk: meson: s4: fix module autoloading clk: meson: fix module license to GPL only clk: meson: g12a: make VCLK2 and ENCL clock path configurable by CCF clk: meson: add vclk driver clk: meson: pll: print out pll name when unable to lock it clk: meson: s4: pll: determine maximum register in regmap config clk: meson: s4: peripherals: determine maximum register in regmap config clk: meson: a1: pll: determine maximum register in regmap config clk: meson: a1: peripherals: determine maximum register in regmap config * clk-binding: dt-bindings: clock: fixed: Define a preferred node name * clk-rockchip: clk: rockchip: rk3568: Add PLL rate for 724 MHz clk: rockchip: Remove an unused field in struct rockchip_mmc_clock clk: rockchip: rk3588: Add reset line for HDMI Receiver clk: rockchip: rk3568: Add missing USB480M_PHY mux dt-bindings: reset: Define reset id used for HDMI Receiver dt-bindings: clock: rockchip: add USB480M_PHY mux
2024-05-16Merge branches 'clk-stm', 'clk-renesas', 'clk-scmi' and 'clk-allwinner' into ↵Stephen Boyd52-201/+3672
clk-next - STM32MP257 SoC clk driver - Allocate clk_ops dynamically for SCMI clk driver * clk-stm: dt-bindings: clocks: stm32mp25: add access-controllers description clk: stm32: introduce clocks for STM32MP257 platform dt-bindings: clocks: stm32mp25: add description of all parents clk: stm32mp13: use platform device APIs * clk-renesas: clk: renesas: r9a08g045: Add support for power domains clk: renesas: rzg2l: Extend power domain support dt-bindings: clock: renesas,rzg2l-cpg: Update #power-domain-cells = <1> for RZ/G3S dt-bindings: clock: r9a08g045-cpg: Add power domain IDs dt-bindings: clock: r9a07g054-cpg: Add power domain IDs dt-bindings: clock: r9a07g044-cpg: Add power domain IDs dt-bindings: clock: r9a07g043-cpg: Add power domain IDs clk: renesas: shmobile: Remove unused CLK_ENABLE_ON_INIT clk: renesas: r8a7740: Remove unused div4_clk.flags field clk: renesas: r9a07g043: Add clock and reset entry for PLIC clk: renesas: r8a779h0: Add INTC-EX clock clk: renesas: r8a779h0: Add MSIOF clocks clk: renesas: r8a779a0: Fix CANFD parent clock clk: rs9: fix wrong default value for clock amplitude clk: renesas: r8a779h0: Add timer clocks clk: renesas: r8a779h0: Add SCIF clocks clk: renesas: r9a07g044: Mark resets array as const clk: renesas: r9a07g043: Mark mod_clks and resets arrays as const clk: renesas: r8a779h0: Add thermal clock dt-bindings: clock: r9a07g043-cpg: Annotate RZ/G2UL-only core clocks * clk-scmi: clk: scmi: Add support for get/set duty_cycle operations clk: scmi: Add support for re-parenting restricted clocks clk: scmi: Add support for rate change restricted clocks clk: scmi: Add support for state control restricted clocks clk: scmi: Allocate CLK operations dynamically * clk-allwinner: clk: sunxi-ng: fix module autoloading clk: sunxi-ng: a64: Add constraints on PLL-MIPI's n/m ratio and parent rate clk: sunxi-ng: nkm: Support constraints on m/n ratio and parent rate
2024-05-16Merge branches 'clk-cleanup', 'clk-airoha', 'clk-mediatek', 'clk-sophgo' and ↵Stephen Boyd20-301/+4046
'clk-loongson' into clk-next - Airoha EN7581 SoC clk driver - Sophgo CV1800B, CV1812H and SG2000 SoC clk driver - Loongson-2k0500 and Loongson-2k2000 SoC clk driver * clk-cleanup: clk: gemini: Remove an unused field in struct clk_gemini_pci clk: highbank: Remove an unused field in struct hb_clk clk: ti: dpll: fix incorrect #ifdef checks clk: nxp: Remove an unused field in struct lpc18xx_pll * clk-airoha: clk: en7523: Add EN7581 support clk: en7523: Add en_clk_soc_data data structure dt-bindings: clock: airoha: add EN7581 binding * clk-mediatek: clk: mediatek: mt8365-mm: fix DPI0 parent clk: mediatek: pllfh: Don't log error for missing fhctl node * clk-sophgo: clk: sophgo: avoid open-coded 64-bit division clk: sophgo: Make synthesizer struct static clk: sophgo: Add clock support for SG2000 SoC clk: sophgo: Add clock support for CV1810 SoC clk: sophgo: Add clock support for CV1800 SoC dt-bindings: clock: sophgo: Add clock controller of SG2000 series SoC * clk-loongson: clk: clk-loongson2: Add Loongson-2K2000 clock support dt-bindings: clock: loongson2: Add Loongson-2K2000 compatible clk: clk-loongson2: Add Loongson-2K0500 clock support dt-bindings: clock: loongson2: Add Loongson-2K0500 compatible clk: clk-loongson2: Refactor driver for adding new platforms dt-bindings: clock: Add Loongson-2K expand clock index
2024-05-07dt-bindings: clocks: stm32mp25: add access-controllers descriptionGabriel Fernandez1-0/+4
access-controllers is an optional property that allows to refer to domain access controller. The RCC driver will be able to check if we are allowed to register clocks for a peripheral. Signed-off-by: Gabriel Fernandez <[email protected]> Link: https://lore.kernel.org/r/[email protected] Acked-by: Rob Herring (Arm) <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2024-05-06Merge tag 'v6.10-rockchip-clk1' of ↵Stephen Boyd5-1/+9
git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-rockchip Pull some small Rockchip clk driver updates from Heiko Stuebner: - A new PLL rate and missing mux on rk3568 - A missing reset line on rk3588 - Removal of an unused field in struct rockchip_mmc_clock * tag 'v6.10-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: clk: rockchip: rk3568: Add PLL rate for 724 MHz clk: rockchip: Remove an unused field in struct rockchip_mmc_clock clk: rockchip: rk3588: Add reset line for HDMI Receiver clk: rockchip: rk3568: Add missing USB480M_PHY mux dt-bindings: reset: Define reset id used for HDMI Receiver dt-bindings: clock: rockchip: add USB480M_PHY mux
2024-05-04clk: rockchip: rk3568: Add PLL rate for 724 MHzLucas Stach1-0/+1
This rate allows to provide a low-jitter 72,4 MHz pixelclock for a custom eDP panel from the VPLL. Signed-off-by: Lucas Stach <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Heiko Stuebner <[email protected]>
2024-05-04clk: rockchip: Remove an unused field in struct rockchip_mmc_clockChristophe JAILLET1-1/+0
In "struct rockchip_mmc_clock", the 'id' field is unused. Remove it. Found with cppcheck, unusedStructMember. Signed-off-by: Christophe JAILLET <[email protected]> Link: https://lore.kernel.org/r/410bc0f86c7b9f1c80f8a4e9a2a028a9a6ee1ec0.1713970085.git.christophe.jaillet@wanadoo.fr Signed-off-by: Heiko Stuebner <[email protected]>
2024-05-03dt-bindings: clock: fixed: Define a preferred node nameRob Herring (Arm)2-0/+18
Define "clock-<freq>" as the preferred node name for fixed-clock and fixed-factor-clock where <freq> is the output frequency of the clock. There isn't much of an existing pattern for names of these nodes. The most frequent patterns are a prefix or suffix of "clk", but there's a bunch that don't follow any sort of pattern. We could use "clock-controller-.*", but these nodes aren't really a controller in any way. So let's at least align with part of that and use 'clock-'. For now this only serves as documentation as the schema still allows anything to avoid lots of additional warnings for something low priority to fix. Once a "no deprecated" mode is added to the tools, warnings can be enabled selectively. Signed-off-by: Rob Herring (Arm) <[email protected]> Link: https://lore.kernel.org/r/[email protected] Acked-by: Conor Dooley <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2024-05-03Merge tag 'clk-meson-v6.10-1' of https://github.com/BayLibre/clk-meson into ↵Stephen Boyd25-39/+279
clk-amlogic Pull Amlogic clk driver updates from Jerome Brunet: - s4/a1: add regmap maximum register for proper debugfs dump - s4: add MODULE_DEVICE_TABLE() on pll and periph controllers - pll driver: print clock name on lock error to help debug - vclk: finish dsi clock path support - license: fix occurence "GPL v2" as reported by checkpatch * tag 'clk-meson-v6.10-1' of https://github.com/BayLibre/clk-meson: clk: meson: s4: fix module autoloading clk: meson: fix module license to GPL only clk: meson: g12a: make VCLK2 and ENCL clock path configurable by CCF clk: meson: add vclk driver clk: meson: pll: print out pll name when unable to lock it clk: meson: s4: pll: determine maximum register in regmap config clk: meson: s4: peripherals: determine maximum register in regmap config clk: meson: a1: pll: determine maximum register in regmap config clk: meson: a1: peripherals: determine maximum register in regmap config
2024-05-03clk: meson: s4: fix module autoloadingKrzysztof Kozlowski2-0/+2
Add MODULE_DEVICE_TABLE(), so modules could be properly autoloaded based on the alias from of_device_id table. Clocks are considered core components, so usually they are built-in, however these can be built and used as modules on some generic kernel. Signed-off-by: Krzysztof Kozlowski <[email protected]> Reviewed-by: Neil Armstrong <[email protected]> Reviewed-by: Martin Blumenstingl <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Jerome Brunet <[email protected]>
2024-05-01Merge tag 'clk-imx-6.10' of ↵Stephen Boyd7-21/+728
git://git.kernel.org/pub/scm/linux/kernel/git/abelvesa/linux into clk-imx Pull i.MX clk driver updates from Abel Vesa: - Add PM runtime support to i.MX8MP Audiomix - Add i.MX95 BLK CTL clock driver - Add DT schema for i.MX95 Display Master Block Control - Convert to platform remove callback returning void for i.MX8MP Audiomix * tag 'clk-imx-6.10' of git://git.kernel.org/pub/scm/linux/kernel/git/abelvesa/linux: clk: imx: imx8mp: Convert to platform remove callback returning void clk: imx: imx8mp: Switch to RUNTIME_PM_OPS() clk: imx: add i.MX95 BLK CTL clk driver dt-bindings: clock: support i.MX95 Display Master CSR module dt-bindings: clock: support i.MX95 BLK CTL module dt-bindings: clock: add i.MX95 clock header clk: imx: imx8mp: Add pm_runtime support for power saving
2024-05-01clk: imx: imx8mp: Convert to platform remove callback returning voidUwe Kleine-König1-4/+2
The .remove() callback for a platform driver returns an int which makes many driver authors wrongly assume it's possible to do error handling by returning an error code. However the value returned is ignored (apart from emitting a warning) and this typically results in resource leaks. To improve here there is a quest to make the remove callback return void. In the first step of this quest all drivers are converted to .remove_new(), which already returns void. Eventually after all drivers are converted, .remove_new() will be renamed to .remove(). Trivially convert this driver from always returning zero in the remove callback to the void returning variant. Fixes: 1496dd413b2e ("clk: imx: imx8mp: Add pm_runtime support for power saving") Signed-off-by: Uwe Kleine-König <[email protected]> Reviewed-by: Abel Vesa <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Abel Vesa <[email protected]>
2024-05-01clk: imx: imx8mp: Switch to RUNTIME_PM_OPS()Fabio Estevam1-3/+3
Replace SET_RUNTIME_PM_OPS() with its modern alternative RUNTIME_PM_OPS(). The combined usage of pm_ptr() and RUNTIME_PM_OPS() allows the compiler to evaluate if the suspend/resume() functions are used at buid time or are simply dead code. This fixes the following s390 allmodconfig build errors: drivers/clk/imx/clk-imx8mp-audiomix.c:363:12: error: 'clk_imx8mp_audiomix_runtime_resume' defined but not used [-Werror=unused-function] 363 | static int clk_imx8mp_audiomix_runtime_resume(struct device *dev) | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ drivers/clk/imx/clk-imx8mp-audiomix.c:356:12: error: 'clk_imx8mp_audiomix_runtime_suspend' defined but not used [-Werror=unused-function] 356 | static int clk_imx8mp_audiomix_runtime_suspend(struct device *dev) | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ cc1: all warnings being treated as errors Reported-by: Naresh Kamboju <[email protected]> Closes: https://lore.kernel.org/linux-clk/CA+G9fYuP7S+a89Ep5g5_Ad69EMwRkJ8nM+MMTzbEcP+6H2oMXQ@mail.gmail.com/T/#u Fixes: 1496dd413b2e ("clk: imx: imx8mp: Add pm_runtime support for power saving") Signed-off-by: Fabio Estevam <[email protected]> Reviewed-by: Peng Fan <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Abel Vesa <[email protected]>
2024-04-29clk: bcm: rpi: Assign ->num before accessing ->hwsNathan Chancellor1-1/+1
Commit f316cdff8d67 ("clk: Annotate struct clk_hw_onecell_data with __counted_by") annotated the hws member of 'struct clk_hw_onecell_data' with __counted_by, which informs the bounds sanitizer about the number of elements in hws, so that it can warn when hws is accessed out of bounds. As noted in that change, the __counted_by member must be initialized with the number of elements before the first array access happens, otherwise there will be a warning from each access prior to the initialization because the number of elements is zero. This occurs in raspberrypi_discover_clocks() due to ->num being assigned after ->hws has been accessed: UBSAN: array-index-out-of-bounds in drivers/clk/bcm/clk-raspberrypi.c:374:4 index 3 is out of range for type 'struct clk_hw *[] __counted_by(num)' (aka 'struct clk_hw *[]') Move the ->num initialization to before the first access of ->hws, which clears up the warning. Cc: [email protected] Fixes: f316cdff8d67 ("clk: Annotate struct clk_hw_onecell_data with __counted_by") Signed-off-by: Nathan Chancellor <[email protected]> Link: https://lore.kernel.org/r/20240425-cbl-bcm-assign-counted-by-val-before-access-v1-2-e2db3b82d5ef@kernel.org Reviewed-by: Kees Cook <[email protected]> Reviewed-by: Florian Fainelli <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2024-04-29clk: bcm: dvp: Assign ->num before accessing ->hwsNathan Chancellor1-1/+2
Commit f316cdff8d67 ("clk: Annotate struct clk_hw_onecell_data with __counted_by") annotated the hws member of 'struct clk_hw_onecell_data' with __counted_by, which informs the bounds sanitizer about the number of elements in hws, so that it can warn when hws is accessed out of bounds. As noted in that change, the __counted_by member must be initialized with the number of elements before the first array access happens, otherwise there will be a warning from each access prior to the initialization because the number of elements is zero. This occurs in clk_dvp_probe() due to ->num being assigned after ->hws has been accessed: UBSAN: array-index-out-of-bounds in drivers/clk/bcm/clk-bcm2711-dvp.c:59:2 index 0 is out of range for type 'struct clk_hw *[] __counted_by(num)' (aka 'struct clk_hw *[]') Move the ->num initialization to before the first access of ->hws, which clears up the warning. Cc: [email protected] Fixes: f316cdff8d67 ("clk: Annotate struct clk_hw_onecell_data with __counted_by") Signed-off-by: Nathan Chancellor <[email protected]> Link: https://lore.kernel.org/r/20240425-cbl-bcm-assign-counted-by-val-before-access-v1-1-e2db3b82d5ef@kernel.org Reviewed-by: Kees Cook <[email protected]> Reviewed-by: Florian Fainelli <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2024-04-29Merge tag 'renesas-clk-for-v6.10-tag2' of ↵Stephen Boyd14-35/+577
git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-renesas Pull more Renesas clk driver updates from Geert Uytterhoeven: - Miscellaneous fixes and improvements - Add SPI (MSIOF) and external interrupt (INTC-EX) clocks on R-Car V4M - Add interrupt controller (PLIC) clock and reset on RZ/Five - Prepare power domain support for RZ/G2L family members, and add actual support on RZ/G3S SoC * tag 'renesas-clk-for-v6.10-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers: clk: renesas: r9a08g045: Add support for power domains clk: renesas: rzg2l: Extend power domain support dt-bindings: clock: renesas,rzg2l-cpg: Update #power-domain-cells = <1> for RZ/G3S dt-bindings: clock: r9a08g045-cpg: Add power domain IDs dt-bindings: clock: r9a07g054-cpg: Add power domain IDs dt-bindings: clock: r9a07g044-cpg: Add power domain IDs dt-bindings: clock: r9a07g043-cpg: Add power domain IDs clk: renesas: shmobile: Remove unused CLK_ENABLE_ON_INIT clk: renesas: r8a7740: Remove unused div4_clk.flags field clk: renesas: r9a07g043: Add clock and reset entry for PLIC clk: renesas: r8a779h0: Add INTC-EX clock clk: renesas: r8a779h0: Add MSIOF clocks clk: renesas: r8a779a0: Fix CANFD parent clock
2024-04-29Merge tag 'sunxi-clk-for-6.10-1' of ↵Stephen Boyd25-5/+53
https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into clk-allwinner Pull Allwinner clk driver updates from Jernej Skrabec: - Add additional constraints to A64 PLL MIPI clock - Fix autoloading sunxi-ng clocks when build as a module * tag 'sunxi-clk-for-6.10-1' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux: clk: sunxi-ng: fix module autoloading clk: sunxi-ng: a64: Add constraints on PLL-MIPI's n/m ratio and parent rate clk: sunxi-ng: nkm: Support constraints on m/n ratio and parent rate
2024-04-25clk: renesas: r9a08g045: Add support for power domainsClaudiu Beznea1-0/+41
Instantiate power domains for the currently enabled IPs of the R9A08G045 SoC. Signed-off-by: Claudiu Beznea <[email protected]> Reviewed-by: Geert Uytterhoeven <[email protected]> Reviewed-by: Ulf Hansson <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Geert Uytterhoeven <[email protected]>
2024-04-25clk: renesas: rzg2l: Extend power domain supportClaudiu Beznea2-14/+252
RZ/{G2L, V2L, G3S}-based CPG versions have support for saving extra power when clocks are disabled by activating module standby. This is done through MSTOP-specific registers that are part of CPG. Each individual module has one or more bits associated with one MSTOP register (see table "Registers for Module Standby Mode" from HW manuals). Hardware manual associates modules' clocks with one or more MSTOP bits. There are 3 mappings available (identified by researching RZ/G2L, RZ/G3S, RZ/V2L HW manuals): case 1: N clocks mapped to N MSTOP bits (with N={0, ..., X}) case 2: N clocks mapped to 1 MSTOP bit (with N={0, ..., X}) case 3: N clocks mapped to M MSTOP bits (with N={0, ..., X}, M={0, ..., Y}) Case 3 has been currently identified on RZ/V2L for the VCPL4 module. To cover all three cases, the individual platform drivers will provide the clock driver with MSTOP register offsets and associated bits in this register as a bitmask, and the clock driver will apply this bitmask to the proper MSTOP register. The MSTOP support was implemented through power domains. Platform-specific clock drivers will register an array of type struct rzg2l_cpg_pm_domain_init_data, which will be used to instantiate properly the power domains. Signed-off-by: Claudiu Beznea <[email protected]> Reviewed-by: Geert Uytterhoeven <[email protected]> Reviewed-by: Ulf Hansson <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Geert Uytterhoeven <[email protected]>
2024-04-25dt-bindings: clock: renesas,rzg2l-cpg: Update #power-domain-cells = <1> for ↵Claudiu Beznea1-1/+17
RZ/G3S The driver will be modified (in the next commits) to be able to specify individual power domain IDs for each IP. The driver will still support #power-domain-cells = <0>, thus, previous users are not affected. The #power-domain-cells = <1> has been instantiated only for RZ/G3S at the moment, as individual platform clock drivers need to be adapted for this to be supported on the rest of the SoCs. Also, the description for #power-domain-cells is updated with links to per-SoC power domain IDs. Signed-off-by: Claudiu Beznea <[email protected]> Reviewed-by: Rob Herring <[email protected]> Reviewed-by: Geert Uytterhoeven <[email protected]> Reviewed-by: Ulf Hansson <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Geert Uytterhoeven <[email protected]>
2024-04-25dt-bindings: clock: r9a08g045-cpg: Add power domain IDsClaudiu Beznea1-0/+70
Add power domain IDs for the RZ/G3S (R9A08G045) SoC. Signed-off-by: Claudiu Beznea <[email protected]> Reviewed-by: Geert Uytterhoeven <[email protected]> Acked-by: Rob Herring <[email protected]> Reviewed-by: Ulf Hansson <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Geert Uytterhoeven <[email protected]>
2024-04-25dt-bindings: clock: r9a07g054-cpg: Add power domain IDsClaudiu Beznea1-0/+58
Add power domain IDs for the RZ/V2L (R9A07G054) SoC. Signed-off-by: Claudiu Beznea <[email protected]> Reviewed-by: Geert Uytterhoeven <[email protected]> Acked-by: Rob Herring <[email protected]> Reviewed-by: Ulf Hansson <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Geert Uytterhoeven <[email protected]>
2024-04-25dt-bindings: clock: r9a07g044-cpg: Add power domain IDsClaudiu Beznea1-0/+58
Add power domain IDs for the RZ/G2L (R9A07G044) SoC. Signed-off-by: Claudiu Beznea <[email protected]> Reviewed-by: Geert Uytterhoeven <[email protected]> Acked-by: Rob Herring <[email protected]> Reviewed-by: Ulf Hansson <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Geert Uytterhoeven <[email protected]>
2024-04-25dt-bindings: clock: r9a07g043-cpg: Add power domain IDsClaudiu Beznea1-0/+52
Add power domain IDs for the RZ/G2UL (R9A07G043) SoC. Signed-off-by: Claudiu Beznea <[email protected]> Acked-by: Rob Herring <[email protected]> Reviewed-by: Geert Uytterhoeven <[email protected]> Reviewed-by: Ulf Hansson <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Geert Uytterhoeven <[email protected]>
2024-04-25clk: renesas: shmobile: Remove unused CLK_ENABLE_ON_INITGeert Uytterhoeven3-6/+0
CLK_ENABLE_ON_INIT is a relic from the old SH clock framework. It is not used on SH/R-Mobile ARM drivers. Signed-off-by: Geert Uytterhoeven <[email protected]> Link: https://lore.kernel.org/r/f01e60a1007afe9385ddc10c4665752857ba4135.1714032122.git.geert+renesas@glider.be
2024-04-25clk: renesas: r8a7740: Remove unused div4_clk.flags fieldChristophe JAILLET1-13/+12
In "struct div4_clk", the "flags" field is unused. Remove it, and update the "div4_clks" array accordingly. Found with cppcheck, unusedStructMember. Signed-off-by: Christophe JAILLET <[email protected]> Reviewed-by: Geert Uytterhoeven <[email protected]> Tested-by: Geert Uytterhoeven <[email protected]> Link: https://lore.kernel.org/r/658e6b1b23d5b66646bb830361b8c55ccf797771.1713025170.git.christophe.jaillet@wanadoo.fr Signed-off-by: Geert Uytterhoeven <[email protected]>
2024-04-23clk: renesas: r9a07g043: Add clock and reset entry for PLICLad Prabhakar1-0/+9
Add the missing clock and reset entry for PLIC. Also add R9A07G043_NCEPLIC_ACLK to the critical clocks list. Fixes: 95d48d270305ad2c ("clk: renesas: r9a07g043: Add support for RZ/Five SoC") Signed-off-by: Lad Prabhakar <[email protected]> Reviewed-by: Geert Uytterhoeven <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Geert Uytterhoeven <[email protected]>
2024-04-23clk: renesas: r8a779h0: Add INTC-EX clockCong Dang1-0/+1
Add the module clock used by the Interrupt Controller for External Devices (INTC-EX) aka IRQC on the Renesas R-Car V4M (R8A779H0) SoC. Signed-off-by: Cong Dang <[email protected]> Signed-off-by: Geert Uytterhoeven <[email protected]> Link: https://lore.kernel.org/r/e260fd8eac0187c690ac6c62673b29f97e2ad5a4.1713279470.git.geert+renesas@glider.be
2024-04-23clk: renesas: r8a779h0: Add MSIOF clocksCong Dang1-0/+6
Add the module clocks used by the Clock-Synchronized Serial Interfaces with FIFO (MSIOF) on the Renesas R-Car V4M (R8A779H0) SoC. Signed-off-by: Cong Dang <[email protected]> Signed-off-by: Geert Uytterhoeven <[email protected]> Link: https://lore.kernel.org/r/86ce05ae274d384c5221bd136415a7b0a1579592.1713279332.git.geert+renesas@glider.be
2024-04-23clk: renesas: r8a779a0: Fix CANFD parent clockGeert Uytterhoeven1-1/+1
According to Figure 52A.1 ("RS-CANFD Module Block Diagram (in classical CAN mode)") in the R-Car V3U Series User’s Manual Rev. 0.5, the parent clock for the CANFD peripheral module clock is the S3D2 clock. Fixes: 9b621b6adff53346 ("clk: renesas: r8a779a0: Add CANFD module clock") Signed-off-by: Geert Uytterhoeven <[email protected]> Link: https://lore.kernel.org/r/aef9300f44c9141b1465343f91c5cc7303249b6e.1713279523.git.geert+renesas@glider.be
2024-04-22clk: scmi: Add support for get/set duty_cycle operationsCristian Marussi1-0/+49
Provide the CLK framework callbacks related to get/set clock duty cycle if the related SCMI clock supports OEM extended configurations. CC: Michael Turquette <[email protected]> CC: Stephen Boyd <[email protected]> CC: [email protected] Signed-off-by: Cristian Marussi <[email protected]> Link: https://lore.kernel.org/r/[email protected] Reviewed-by: Sudeep Holla <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2024-04-22clk: scmi: Add support for re-parenting restricted clocksCristian Marussi1-1/+6
Some exposed SCMI Clocks could be marked as non-supporting re-parenting changes. Configure a clk_ops descriptor which does not provide the re-parenting callbacks for such clocks when registering with CLK framework. CC: Michael Turquette <[email protected]> CC: Stephen Boyd <[email protected]> CC: [email protected] Signed-off-by: Cristian Marussi <[email protected]> Link: https://lore.kernel.org/r/[email protected] Reviewed-by: Sudeep Holla <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2024-04-22clk: scmi: Add support for rate change restricted clocksCristian Marussi1-1/+6
Some exposed SCMI Clocks could be marked as non-supporting rate changes. Configure a clk_ops descriptors which does not provide the rate change callbacks for such clocks when registering with CLK framework. CC: Michael Turquette <[email protected]> CC: Stephen Boyd <[email protected]> CC: [email protected] Signed-off-by: Cristian Marussi <[email protected]> Link: https://lore.kernel.org/r/[email protected] Reviewed-by: Sudeep Holla <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2024-04-22clk: scmi: Add support for state control restricted clocksCristian Marussi1-7/+15
Some exposed SCMI Clocks could be marked as non-supporting state changes. Configure a clk_ops descriptor which does not provide the state change callbacks for such clocks when registering with CLK framework. CC: Michael Turquette <[email protected]> CC: Stephen Boyd <[email protected]> CC: [email protected] Signed-off-by: Cristian Marussi <[email protected]> Link: https://lore.kernel.org/r/[email protected] Reviewed-by: Sudeep Holla <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2024-04-22clk: scmi: Allocate CLK operations dynamicallyCristian Marussi1-50/+136
SCMI Clocks descriptors expose an increasing number of properties, thing which, in turn, leads to a varying set of supported CLK operations to be associated with each clock. Providing statically pre-defined CLK operations structs for all the possible combinations of allowed clock features is becoming cumbersome and error-prone. Allocate the per-clock operations descriptors dynamically and populate it with the strictly needed set of operations depending on the advertised clock properties: one descriptor is created for each distinct combination of clock operations, so minimizing the number of clk_ops structures to the strictly minimum needed. CC: Michael Turquette <[email protected]> CC: Stephen Boyd <[email protected]> CC: [email protected] Signed-off-by: Cristian Marussi <[email protected]> Link: https://lore.kernel.org/r/[email protected] Reviewed-by: Sudeep Holla <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2024-04-22clk: imx: add i.MX95 BLK CTL clk driverPeng Fan3-0/+446
i.MX95 has BLK CTL modules in various MIXes, the BLK CTL modules support clock features such as mux/gate/div. This patch is to add the clock feature of BLK CTL modules Signed-off-by: Peng Fan <[email protected]> Reviewed-by: Abel Vesa <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Abel Vesa <[email protected]>
2024-04-22dt-bindings: clock: support i.MX95 Display Master CSR modulePeng Fan1-0/+64
i.MX95 DISPLAY_MASTER_CSR includes registers to control DSI clock settings, clock gating, and pixel link select. Add dt-schema for it. Reviewed-by: Krzysztof Kozlowski <[email protected]> Signed-off-by: Peng Fan <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Abel Vesa <[email protected]>
2024-04-22dt-bindings: clock: support i.MX95 BLK CTL modulePeng Fan1-0/+56
i.MX95 includes BLK CTL module in several MIXes, such as VPU_CSR in VPUMIX, CAMERA_CSR in CAMERAMIX and etc. The BLK CTL module is used for various settings of a specific MIX, such as clock, QoS and etc. This patch is to add some BLK CTL modules that has clock features. Reviewed-by: Krzysztof Kozlowski <[email protected]> Signed-off-by: Peng Fan <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Abel Vesa <[email protected]>
2024-04-22dt-bindings: clock: add i.MX95 clock headerPeng Fan1-0/+28
Add clock header for i.MX95 BLK CTL modules Signed-off-by: Peng Fan <[email protected]> Acked-by: Rob Herring <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Abel Vesa <[email protected]>
2024-04-22clk: imx: imx8mp: Add pm_runtime support for power savingShengjiu Wang1-21/+136
Add pm_runtime support for power saving. In pm runtime suspend state the registers will be reseted, so add registers save in pm runtime suspend and restore them in pm runtime resume. Signed-off-by: Shengjiu Wang <[email protected]> Reviewed-by: Peng Fan <[email protected]> Reviewed-by: Marc Kleine-Budde <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Abel Vesa <[email protected]>
2024-04-19clk: rs9: fix wrong default value for clock amplitudeCatalin Popescu1-4/+6
According to 9FGV0241, 9FGV0441 & 9FGV0841 datasheets, the default value for the clock amplitude is 0.8V, while the driver assumes 0.7V. Additionally, define constants for default values for both clock amplitude and spread spectrum and use them. Fixes: 892e0ddea1aa ("clk: rs9: Add Renesas 9-series PCIe clock generator driver") Signed-off-by: Catalin Popescu <[email protected]> Reviewed-by: Marek Vasut <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
2024-04-19clk: gemini: Remove an unused field in struct clk_gemini_pciChristophe JAILLET1-2/+0
In "struct clk_gemini_pci", the 'rate' field is unused. Remove it. Found with cppcheck, unusedStructMember. Signed-off-by: Christophe JAILLET <[email protected]> Link: https://lore.kernel.org/r/556770c7701868f9f1c0569674903bee3eff30cb.1713015940.git.christophe.jaillet@wanadoo.fr Signed-off-by: Stephen Boyd <[email protected]>
2024-04-19clk: highbank: Remove an unused field in struct hb_clkChristophe JAILLET1-1/+0
In "struct hb_clk", the 'parent_name' field is unused. Remove it. Found with cppcheck, unusedStructMember. Signed-off-by: Christophe JAILLET <[email protected]> Link: https://lore.kernel.org/r/90b19f2af3077075d4254e01d5ae919c423d067e.1713016457.git.christophe.jaillet@wanadoo.fr Signed-off-by: Stephen Boyd <[email protected]>
2024-04-19clk: mediatek: mt8365-mm: fix DPI0 parentAlexandre Mergnat1-1/+1
To have a working display through DPI, a workaround has been implemented downstream to add "mm_dpi0_dpi0" and "dpi0_sel" to the DPI node. Shortly, that add an extra clock. It seems consistent to have the "dpi0_sel" as parent. Additionnaly, "vpll_dpix" isn't used/managed. Then, set the "mm_dpi0_dpi0" parent clock to "dpi0_sel". The new clock tree is: clk26m lvdspll lvdspll_X (2, 4, 8, 16) dpi0_sel mm_dpi0_dpi0 Fixes: d46adccb7966 ("clk: mediatek: add driver for MT8365 SoC") Signed-off-by: Alexandre Mergnat <[email protected]> Link: https://lore.kernel.org/r/[email protected] Reviewed-by: AngeloGioacchino Del Regno <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2024-04-19clk: sophgo: avoid open-coded 64-bit divisionArnd Bergmann1-2/+1
On 32-bit architectures, the 64-bit division leads to a link failure: arm-linux-gnueabi-ld: drivers/clk/sophgo/clk-cv18xx-pll.o: in function `fpll_calc_rate': clk-cv18xx-pll.c:(.text.fpll_calc_rate+0x26): undefined reference to `__aeabi_uldivmod' This one is not called in a fast path, and there is already another div_u64() variant used in the same function, so convert it to div64_u64_rem(). Fixes: 80fd61ec4612 ("clk: sophgo: Add clock support for CV1800 SoC") Signed-off-by: Arnd Bergmann <[email protected]> Link: https://lore.kernel.org/r/[email protected] Reported-by: kernel test robot <[email protected]> Closes: https://lore.kernel.org/oe-kbuild-all/[email protected]/ Closes: https://lore.kernel.org/oe-kbuild-all/[email protected]/ Reviewed-by: Inochi Amaoto <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2024-04-19Merge tag 'renesas-clk-for-v6.10-tag1' of ↵Stephen Boyd4-6/+20
git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-renesas Pull Renesas clk driver updates from Geert Uytterhoeven: - Add thermal, serial (SCIF), and timer (CMT/TMU) clocks on R-Car V4M - Miscellaneous fixes and improvements * tag 'renesas-clk-for-v6.10-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers: clk: renesas: r8a779h0: Add timer clocks clk: renesas: r8a779h0: Add SCIF clocks clk: renesas: r9a07g044: Mark resets array as const clk: renesas: r9a07g043: Mark mod_clks and resets arrays as const clk: renesas: r8a779h0: Add thermal clock dt-bindings: clock: r9a07g043-cpg: Annotate RZ/G2UL-only core clocks
2024-04-15clk: sunxi-ng: fix module autoloadingKrzysztof Kozlowski23-0/+23
Add MODULE_DEVICE_TABLE(), so modules could be properly autoloaded based on the alias from of_device_id table. Clocks are considered core components, so usually they are built-in, however these can be built and used as modules on some generic kernel. Signed-off-by: Krzysztof Kozlowski <[email protected]> Acked-by: Jernej Skrabec <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Jernej Skrabec <[email protected]>
2024-04-15clk: sunxi-ng: a64: Add constraints on PLL-MIPI's n/m ratio and parent rateFrank Oltmanns1-5/+7
The Allwinner A64 manual lists the following constraints for the PLL-MIPI clock: - M/N <= 3 - (PLL_VIDEO0)/M >= 24MHz Use these constraints. Reviewed-by: Jernej Skrabec <[email protected]> Signed-off-by: Frank Oltmanns <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Jernej Skrabec <[email protected]>
2024-04-15clk: sunxi-ng: nkm: Support constraints on m/n ratio and parent rateFrank Oltmanns2-0/+23
The Allwinner A64 manual lists the following constraints for the PLL-MIPI clock: - M/N <= 3 - (PLL_VIDEO0)/M >= 24MHz The PLL-MIPI clock is implemented as ccu_nkm. Therefore, add support for these constraints. Reviewed-by: Jernej Skrabec <[email protected]> Signed-off-by: Frank Oltmanns <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Jernej Skrabec <[email protected]>
2024-04-11clk: stm32: introduce clocks for STM32MP257 platformGabriel Fernandez6-15/+2646
This driver is intended for the STM32MP25 clock family and utilizes the stm32-core API, similar to the stm32mp13 clock driver. Signed-off-by: Gabriel Fernandez <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
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