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2020-12-24Merge tag 'amd-drm-fixes-5.11-2020-12-23' of ↵Dave Airlie32-111/+161
git://people.freedesktop.org/~agd5f/linux into drm-next amd-drm-fixes-5.11-2020-12-23: amdgpu: - Vangogh SMU fixes - Arcturus gfx9 fixes - Misc display fixes - Sienna Cichlid SMU update - Fix S3 display memory leak - Fix regression caused by DP sub-connector support amdkfd: - Properly require pcie atomics for gfx10 Signed-off-by: Dave Airlie <[email protected]> From: Alex Deucher <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2020-12-24Merge tag 'drm-misc-next-fixes-2020-12-22' of ↵Dave Airlie6-21/+21
git://anongit.freedesktop.org/drm/drm-misc into drm-next Short summary of fixes pull: * dma-buf: Include <linux/vmalloc.h> for building on MIPS * komeda: Fix order of operation in commit tail; Fix NULL-pointer and out-of-bounds access; Cleanups * ttm: Fix an unused-function warning Signed-off-by: Dave Airlie <[email protected]> From: Thomas Zimmermann <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/X+JFYlW1SEZa6ShA@linux-uq9g
2020-12-23Merge tag 'sound-fix-5.11-rc1' of ↵Linus Torvalds10-22/+70
git://git.kernel.org/pub/scm/linux/kernel/git/tiwai/sound Pull sound fixes from Takashi Iwai: "A collection of small fixes that came up recently for 5.11. The majority of fixes are usual HD-audio and USB-audio quirks, with a few PCM core fixes for addressing the information leak and yet more UBSAN fixes in the core side" * tag 'sound-fix-5.11-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tiwai/sound: ALSA/hda: apply jack fixup for the Acer Veriton N4640G/N6640G/N2510G ALSA: hda/realtek: Apply jack fixup for Quanta NL3 ALSA: usb-audio: Add implicit feeback support for the BOSS GT-1 ALSA: usb-audio: Add alias entry for ASUS PRIME TRX40 PRO-S ALSA: core: Remove redundant comments ALSA: hda/realtek: Add quirk for MSI-GP73 ALSA: pcm: oss: Fix a few more UBSAN fixes ALSA: pcm: Clear the full allocated memory at hw_params ALSA: memalloc: Align buffer allocations in page size ALSA: usb-audio: Disable sample read check if firmware doesn't give back ALSA: pcm: Remove snd_pcm_lib_preallocate_dma_free() ALSA: usb-audio: Add VID to support native DSD reproduction on FiiO devices ALSA: core: memalloc: add page alignment for iram ALSA: hda/realtek - Supported Dell fixed type headset ALSA: hda/realtek: Remove dummy lineout on Acer TravelMate P648/P658
2020-12-23Merge tag 'tag-chrome-platform-for-v5.11' of ↵Linus Torvalds3-78/+427
git://git.kernel.org/pub/scm/linux/kernel/git/chrome-platform/linux Pull chrome platform updates from Benson Leung: "cros_ec_typec: - A series from Prashant for Type-C to implement TYPEC_STATUS, parsing USB PD Partner ID VDOs, and registering partner altmodes. cros_ec misc: - Don't treat RTC events as wakeup sources in cros_ec_proto" * tag 'tag-chrome-platform-for-v5.11' of git://git.kernel.org/pub/scm/linux/kernel/git/chrome-platform/linux: platform/chrome: cros_ec_typec: Tolerate unrecognized mux flags platform/chrome: cros_ec_typec: Register partner altmodes platform/chrome: cros_ec_typec: Parse partner PD ID VDOs platform/chrome: cros_ec_typec: Introduce TYPEC_STATUS platform/chrome: cros_ec: Import Type C host commands platform/chrome: cros_ec_typec: Clear partner identity on device removal platform/chrome: cros_ec_typec: Fix remove partner logic platform/chrome: cros_ec_typec: Relocate set_port_params_v*() functions platform/chrome: Don't treat RTC events as wakeup sources
2020-12-23Merge tag 'linux-watchdog-5.11-rc1' of ↵Linus Torvalds17-370/+104
git://www.linux-watchdog.org/linux-watchdog Pull watchdog updates from Wim Van Sebroeck: - Removal of the pnx83xx driver - Add a binding for A100's watchdog controller - Add Rockchip compatibles to snps,dw-wdt.yaml - hpwdt: Disable NMI in Crash Kernel - Fix potential dereferencing of null pointer in watchdog_core - Several other small fixes and improvements * tag 'linux-watchdog-5.11-rc1' of git://www.linux-watchdog.org/linux-watchdog: (23 commits) watchdog: convert comma to semicolon watchdog: iTCO_wdt: use dev_*() instead of pr_*() for logging dt-binding: watchdog: add Rockchip compatibles to snps,dw-wdt.yaml watchdog: coh901327: add COMMON_CLK dependency dt-bindings: watchdog: sun4i: Add A100 compatible watchdog: qcom: Avoid context switch in restart handler watchdog: iTCO_wdt: use module_platform_device() macro watchdog: Fix potential dereferencing of null pointer watchdog: wdat_wdt: Fix missing kerneldoc reported by W=1 watchdog/hpwdt: Reflect changes watchdog/hpwdt: Disable NMI in Crash Kernel wdt: sp805: add watchdog_stop on reboot watchdog: sbc_fitpc2_wdt: add __user annotations watchdog: geodewdt: remove unneeded break watchdog: rti-wdt: fix reference leak in rti_wdt_probe watchdog: qcom_wdt: set WDOG_HW_RUNNING bit when appropriate watchdog: remove pnx83xx driver watchdog: stm32_iwdg: don't print an error on probe deferral watchdog: sprd: change to use usleep_range() instead of busy loop watchdog: sprd: check busy bit before new loading rather than after that ...
2020-12-23drm/i915/gem: Optimistically prune dma-resv from the shrinker.Chris Wilson5-5/+37
As we shrink an object, also see if we can prune the dma-resv of idle fences it is maintaining a reference to. Signed-off-by: Chris Wilson <[email protected]> Reviewed-by: Mika Kuoppala <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2020-12-23drm/i915/gt: Prefer recycling an idle fenceChris Wilson1-2/+20
If we want to reuse a fence that is in active use by the GPU, we have to wait an uncertain amount of time, but if we reuse an inactive fence, we can change it right away. Loop through the list of available fences twice, ignoring any active fences on the first pass. Signed-off-by: Chris Wilson <[email protected]> Reviewed-by: Mika Kuoppala <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2020-12-23drm/i915/gt: Consolidate the CS timestamp clocksChris Wilson17-256/+205
Pull the GT clock information [used to derive CS timestamps and PM interval] under the GT so that is it local to the users. In doing so, we consolidate the two references for the same information, of which the runtime-info took note of a potential clock source override and scaling factors. Signed-off-by: Chris Wilson <[email protected]> Reviewed-by: Mika Kuoppala <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2020-12-23drm/i915/selftests: Confirm CS_TIMESTAMP / CTX_TIMESTAMP share a clockChris Wilson1-1/+202
We assume that both timestamps are driven off the same clock [reported to userspace as I915_PARAM_CS_TIMESTAMP_FREQUENCY]. Verify that this is so by reading the timestamp registers around a busywait (on an otherwise idle engine so there should be no preemptions). v2: Icelake (not ehl, nor tgl) seems to be using a fixed 80ns interval for, and only for, CTX_TIMESTAMP -- or it may be GPU frequency and the test is always running at maximum frequency?. As far as I can tell, this isolated change in behaviour is undocumented. Signed-off-by: Chris Wilson <[email protected]> Cc: Mika Kuoppala <[email protected]> Reviewed-by: Mika Kuoppala <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2020-12-23drm/i915/selftests: Remove redundant live_context for evictionChris Wilson1-13/+5
We just need the context image from the logical state to force eviction of many contexts, so simplify by avoiding the GEM context container. Signed-off-by: Chris Wilson <[email protected]> Reviewed-by: Matthew Auld <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2020-12-23drm/amdgpu: drop psp ih programming for sriov guest on naviHawking Zhang1-16/+2
the psp access ih path is not needed in navi Signed-off-by: Hawking Zhang <[email protected]> Acked-by: Alex Deucher <[email protected]> Reviewed-by: Jane Jian <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-12-23drm/amd/display: Use common error handling code in dc_create()Markus Elfring1-9/+6
Adjust a jump target so that a bit of exception handling can be better reused at the end of this function. Signed-off-by: Markus Elfring <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-12-23drm/amd/display: Return directly after a failed kzalloc() in dc_create()Markus Elfring1-4/+2
* Return directly after a call of the function “kzalloc” failed at the beginning. * Delete a label which became unnecessary with this refactoring. Signed-off-by: Markus Elfring <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-12-23drm/amdkfd: check both client id and src id in interrupt handlersAlex Deucher1-11/+35
We can have the same src ids for different client ids so make sure to check both the client id and the source id when handling interrupts. Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-12-23drm/amdgpu: fix handling of irq domains on soc15 and newer GPUsAlex Deucher1-1/+2
We need to take into account the client id otherwise we'll end up sending generic events for any src id that is registered. We only support irq domains on pre-soc15 parts so client is always legacy. Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-12-23drm/amdgpu: de-initialize software ih ringHawking Zhang3-0/+3
tear down software ih ring and its state. Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: Feifei Xu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-12-23drm/amdgpu: set ih soft ring enabled flag for vega and naviHawking Zhang2-0/+6
software ih ring is enabled in vega10 and navi ih block by default. Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: Feifei Xu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-12-23drm/amdgpu: enable software ih ring for vega20 ih blockHawking Zhang1-0/+7
software ih ring will be used as a workaround in case hardware ih ring 1 and ring 2 don't work Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: Feifei Xu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-12-23drm/amd/pm: support overdrive vddgfx offset setting(V2)Evan Quan4-2/+70
This is supported by Sienna Cichlid, Navy Flounder and Dimgrey Cavefish. For these ASICs, the target voltage calculation can be illustrated by "voltage = voltage calculated from v/f curve + overdrive vddgfx offset". V2: limit the smu_version check for Sienna Cichlid only Here are some sample usages about this new OD setting: 1. Check current vddgfx offset setting by cat /sys/class/drm/card0/device/pp_od_clk_voltage ... ... OD_VDDGFX_OFFSET: 0mV ... ... 2. Set new vddgfx offset by echo "vo 10" > /sys/class/drm/card0/device/pp_od_clk_voltage cat /sys/class/drm/card0/device/pp_od_clk_voltage ... ... OD_VDDGFX_OFFSET: 10mV ... ... 3. Commit the new setting by echo "c" > /sys/class/drm/card0/device/pp_od_clk_voltage Signed-off-by: Evan Quan <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-12-23drm/amd/pm: enable Sienna Cichlid overdrive supportEvan Quan2-1/+243
Enable Sienna Cichlid gfxclk/uclk overdrive support. Signed-off-by: Evan Quan <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-12-23drm/amd/pm: populate Sienna Cichlid default overdrive table settingsEvan Quan1-0/+38
Populate the bootup overdrive table settings. Signed-off-by: Evan Quan <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-12-23drm/amd/pm: Add interface for request WGPsJinzhou Su3-3/+41
When user specifies a reduced WGP(CU) config via disalbe_cu module parameter, this does not disable the clocks which uses additional power. This interface send active WGP number to SMU and SMU will cooperate with RLC to power off relative WGPs. v2: Add request active WGPs in Vangogh smu post init. Signed-off-by: Jinzhou.Su <[email protected]> Reviewed-by: Jiansong Chen <[email protected]> Reviewed-by: Lijo Lazar <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-12-23drm/amd/pm: add pptable_funcs documentation (v3)Ryan Taylor1-0/+526
Documents the hooks in struct pptable_funcs. v2: Improved documentation accuracy. v3: Improved set_default_od_settings() definition. Signed-off-by: Ryan Taylor <[email protected]> Reviewed-by: Evan Quan <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-12-23drm/amdgpu: don't create ih ring 1 and ring 2 for APUHawking Zhang1-11/+12
APUs don't support ih ring 1 and ring 2. Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-12-23drm/amdgpu: drop ih reroute function from psp v11Hawking Zhang1-36/+0
For all the ASICs that integrate psp v11, vega20 doesn't support ih reroute. arcturus and later will allow kernel driver to program ih_cfg_index/data through mmio directly. navi1x and onwards will only support grb_ih_set command in sriov configuration. psp_v11_0_reroute_ih is not needed any more. Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-12-23drm/amdgpu: drop IH_CHICKEN programming from vega10 ih blockHawking Zhang1-3/+1
except for RENOIR, it is not correct to have IH_CHICKEN programming in vega10 ih block. Signed-off-by: Hawking Zhang <[email protected]> Acked-by: Christian König <[email protected]> Acked-by: Felix Kuehling <[email protected]> Reviewed-by: Dennis Li <[email protected]> Reviewed-by: Feifei Xu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-12-23drm/amdgpu: correct ih_chicken programming for vega10/vega20 ih blocksHawking Zhang2-6/+0
IH_CHICKEN.MC_SPACE_FBPA_ENABLE field is only valid when IH_RB_CNTL.MC_SPACE is programed to 0x3, frame buffer physical address. For both bus address and gpu virtual address, don't program MC_SPACE_FBPA_ENABLE field Signed-off-by: Hawking Zhang <[email protected]> Acked-by: Christian König <[email protected]> Acked-by: Felix Kuehling <[email protected]> Reviewed-by: Dennis Li <[email protected]> Reviewed-by: Feifei Xu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-12-23drm/amdgpu: retire the vega20 code path from navi10 ih blockHawking Zhang1-38/+2
already switched to vega20 ih block for vega20 and arcturus. no need to add vega20 support in navi10 ih block Signed-off-by: Hawking Zhang <[email protected]> Acked-by: Christian König <[email protected]> Acked-by: Felix Kuehling <[email protected]> Reviewed-by: Dennis Li <[email protected]> Reviewed-by: Feifei Xu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-12-23drm/amdgpu: switch to vega20 ih block for vega20/arcturusHawking Zhang1-4/+5
replace navi10 ih block with vega20 ih block for vega20 and arcturus Signed-off-by: Hawking Zhang <[email protected]> Acked-by: Christian König <[email protected]> Acked-by: Felix Kuehling <[email protected]> Reviewed-by: Dennis Li <[email protected]> Reviewed-by: Feifei Xu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-12-23drm/amdgpu: reroute vmc/utcl2 interrupts to ih ring 1 for arcturusHawking Zhang1-0/+34
in case page faults overwhlem the interrupt handlers and the driver lost the valuable interrupt information Signed-off-by: Hawking Zhang <[email protected]> Acked-by: Christian König <[email protected]> Acked-by: Felix Kuehling <[email protected]> Reviewed-by: Dennis Li <[email protected]> Reviewed-by: Feifei Xu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-12-23drm/amdgpu: create vega20 ih blocksHawking Zhang3-0/+692
vega20 ih blocks will be used for vega20/arcturus Signed-off-by: Hawking Zhang <[email protected]> Acked-by: Christian König <[email protected]> Acked-by: Felix Kuehling <[email protected]> Reviewed-by: Dennis Li <[email protected]> Reviewed-by: Feifei Xu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-12-23drm/amdgpu: add osssys v4_2 ip headers (v2)Hawking Zhang2-0/+1645
v1: add osssys v4_2 register offset and shift masks header files. vega20 and arcturus will refer to these ip headers. (Hawking) v2: clean up osssys v4_2 registers (Alex) Signed-off-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Acked-by: Christian König <[email protected]> Acked-by: Felix Kuehling <[email protected]> Reviewed-by: Dennis Li <[email protected]> Reviewed-by: Feifei Xu <[email protected]>
2020-12-23drm/amdgpu: switch to common decode iv helperHawking Zhang2-92/+2
The iv format is the same for all the soc15 adpater and onwards and can share a common function to decode iv. Signed-off-by: Hawking Zhang <[email protected]> Acked-by: Christian König <[email protected]> Acked-by: Felix Kuehling <[email protected]> Reviewed-by: Dennis Li <[email protected]> Reviewed-by: Feifei Xu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-12-23drm/amdgpu: add a helper function to decode ivHawking Zhang2-1/+46
since from soc15, all the chips share the same iv format. create a common helper to decode iv Signed-off-by: Hawking Zhang <[email protected]> Acked-by: Christian König <[email protected]> Acked-by: Felix Kuehling <[email protected]> Reviewed-by: Dennis Li <[email protected]> Reviewed-by: Feifei Xu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-12-23drm/amdgpu: use cached ih rb control reg offsets for navi10Hawking Zhang1-38/+14
all the ih rb control register offsets are cached at the beginning of navi10 ih_sw_init. Signed-off-by: Hawking Zhang <[email protected]> Acked-by: Christian König <[email protected]> Acked-by: Felix Kuehling <[email protected]> Reviewed-by: Dennis Li <[email protected]> Reviewed-by: Feifei Xu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-12-23drm/amdgpu: switch to ih_enable_ring for navi10Hawking Zhang1-90/+12
use navi10_ih_enable_ring to enable all the available ring buffers for navi1x and onwards Signed-off-by: Hawking Zhang <[email protected]> Acked-by: Christian König <[email protected]> Acked-by: Felix Kuehling <[email protected]> Reviewed-by: Dennis Li <[email protected]> Reviewed-by: Feifei Xu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-12-23drm/amdgpu: switch to ih_toggle_interrupts for navi10Hawking Zhang1-133/+33
replace ih_enable_interrupts and ih_disable_interrupts with ih_toggle_interrupts Signed-off-by: Hawking Zhang <[email protected]> Acked-by: Christian König <[email protected]> Acked-by: Felix Kuehling <[email protected]> Reviewed-by: Dennis Li <[email protected]> Reviewed-by: Feifei Xu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-12-23drm/amdgpu: switch to ih_init_register_offset for navi10Hawking Zhang1-0/+3
Initialize ih control registers offset through helper function navi10_ih_init_register_offset. Signed-off-by: Hawking Zhang <[email protected]> Acked-by: Christian König <[email protected]> Acked-by: Felix Kuehling <[email protected]> Reviewed-by: Dennis Li <[email protected]> Reviewed-by: Feifei Xu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-12-23drm/amdgpu: add helper to toggle ih ring interrupts for navi10Hawking Zhang1-0/+45
navi10_ih_toggle_ring_interrupts will be used to enable/disable an ih ring interrupts for navi1x and onwards Signed-off-by: Hawking Zhang <[email protected]> Acked-by: Christian König <[email protected]> Acked-by: Felix Kuehling <[email protected]> Reviewed-by: Dennis Li <[email protected]> Reviewed-by: Feifei Xu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-12-23drm/amdgpu: add helper to enable an ih ring for navi10Hawking Zhang1-0/+52
navi10_ih_enable_ring will be used to enable an ih ring for navi1x and onwards Signed-off-by: Hawking Zhang <[email protected]> Acked-by: Christian König <[email protected]> Acked-by: Felix Kuehling <[email protected]> Reviewed-by: Dennis Li <[email protected]> Reviewed-by: Feifei Xu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-12-23drm/amdgpu: add helper to init ih ring regs for navi10Hawking Zhang1-0/+47
navi10_ih_init_register_offset will be used to init register offset for all the available ih rings Signed-off-by: Hawking Zhang <[email protected]> Acked-by: Christian König <[email protected]> Acked-by: Felix Kuehling <[email protected]> Reviewed-by: Dennis Li <[email protected]> Reviewed-by: Feifei Xu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-12-23drm/amdgpu: correct ih cg programming for vega10 ih blockHawking Zhang1-6/+2
vega10/12 and RAVEN don't support soft override ih_buffer_mem_clk. Signed-off-by: Hawking Zhang <[email protected]> Acked-by: Christian König <[email protected]> Acked-by: Felix Kuehling <[email protected]> Reviewed-by: Dennis Li <[email protected]> Reviewed-by: Feifei Xu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-12-23drm/amdgpu: use cached ih rb control reg offsets for vega10Hawking Zhang1-40/+14
all the ih rb control register offsets are cached at the beginning of ih_sw_init. Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: Christian König <[email protected]> Acked-by: Felix Kuehling <[email protected]> Reviewed-by: Dennis Li <[email protected]> Reviewed-by: Feifei Xu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-12-23drm/amdgpu: switch to ih_enable_ring for vega10Hawking Zhang1-87/+8
use vega10_ih_enable_ring to enable all the available ring buffers for vega10/12, RAVEN series and RENOIR APUs Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: Christian König <[email protected]> Acked-by: Felix Kuehling <[email protected]> Reviewed-by: Dennis Li <[email protected]> Reviewed-by: Feifei Xu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-12-23drm/amdgpu: switch to ih_toggle_interrupts for vega10Hawking Zhang1-134/+34
replace ih_enable_interrupts and ih_disable_interrupts with ih_toggle_interrupts Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: Christian König <[email protected]> Acked-by: Felix Kuehling <[email protected]> Reviewed-by: Dennis Li <[email protected]> Reviewed-by: Feifei Xu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-12-23drm/amdgpu: switch to ih_init_register_offset for vega10Hawking Zhang1-0/+3
Initialize ih control registers offset through helper function vega10_ih_init_register_offset. Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: Christian König <[email protected]> Acked-by: Felix Kuehling <[email protected]> Reviewed-by: Dennis Li <[email protected]> Reviewed-by: Feifei Xu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-12-23drm/amdgpu: add helper to toggle ih ring interrupts for vega10Hawking Zhang1-0/+45
vega10_ih_toggle_ring_interrupts will be used to enable/disable an ih ring interrupts for vega10/12, RAVEN series and RENOIR APUs Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: Christian König <[email protected]> Acked-by: Felix Kuehling <[email protected]> Reviewed-by: Dennis Li <[email protected]> Reviewed-by: Feifei Xu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-12-23drm/amdgpu: add helper to enable an ih ring for vega10Hawking Zhang1-0/+52
vega10_ih_enable_ring will be used to enable an ih ring for vega10/12, RAVEN series and RENOIR. Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: Christian König <[email protected]> Acked-by: Felix Kuehling <[email protected]> Reviewed-by: Dennis Li <[email protected]> Reviewed-by: Feifei Xu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-12-23drm/amdgpu: add helper to init ih ring regs for vega10Hawking Zhang1-0/+47
vega10_ih_init_register_offset will be used to init register offset for all the available ih rings Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: Christian König <[email protected]> Acked-by: Felix Kuehling <[email protected]> Reviewed-by: Dennis Li <[email protected]> Reviewed-by: Feifei Xu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-12-23drm/amdgpu: add amdgpu_ih_regs structureHawking Zhang1-0/+13
amdgpu_ih_regs holds all the registers for an ih ring Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: Christian König <[email protected]> Acked-by: Felix Kuehling <[email protected]> Reviewed-by: Dennis Li <[email protected]> Reviewed-by: Feifei Xu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
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